JP4754763B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP4754763B2
JP4754763B2 JP2002168959A JP2002168959A JP4754763B2 JP 4754763 B2 JP4754763 B2 JP 4754763B2 JP 2002168959 A JP2002168959 A JP 2002168959A JP 2002168959 A JP2002168959 A JP 2002168959A JP 4754763 B2 JP4754763 B2 JP 4754763B2
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layer
semiconductor
electrode
semiconductor chip
semiconductor device
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JP2002373910A (en
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和孝 柴田
茂幸 上田
俊夫 江南
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Rohm Co Ltd
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Rohm Co Ltd
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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Description

【０００１】
【発明の属する技術分野】
本発明は、複数の半導体チップを対面させて電気的に接続する、いわゆるチップオンチップ（chip on chip、以下ＣＯＣという）タイプの半導体装置など、電極パッドと外部リードなどとワイヤで接続する構造の半導体装置に関する。さらに詳しくは、ワイヤボンディングの際に圧力が余りかからないようにすることにより、電極パッドの下にも回路素子を形成することができると共に、マルチチップ化し、第１の半導体チップの表面に複数個の第２半導体チップが直接接続される場合に、第２の半導体チップ間同士で接続する配線が、第１の半導体の内部設計に依存することなく、第２の半導体チップ間で自由に接続を変更し得る半導体装置に関する。
【０００２】
【従来の技術】
従来、たとえばメモリ素子とその論理回路の組合せなどのように、回路の組合せにより半導体装置が構成される場合、立体化による占有面積の縮小化、高周波回路の寄生容量などの低減化、回路の一部の汎用化（たとえばメモリ素子部を汎用化して駆動回路部分を用途に応じて変更する）、大集積回路では、その回路部分により製造条件の厳しさが異なり１チップ化が困難な場合があるなどのため、半導体回路を複数個のチップにより製造し、一方の半導体チップ（親チップ）上に他の半導体チップ（子チップ）を接続する構造の、ＣＯＣタイプの半導体装置が用いられることがある。近年では、図１１に示されるように、この子チップが複数個設けられるマルチチップ化の傾向にある。
【０００３】
図１１において、第１半導体チップ（親チップ）１の電極端子１２上に第２半導体チップ（子チップ）２ａ、２ｂの電極端子２２が、それぞれのバンプ電極１１、２１を介して接続されている。親チップ１は、リードフレームからなる図示しないアイランドにボンディングされ、親チップ１の外周側に設けられる図示しない各電極パッドは、アイランドの周囲に設けられる図示しないリードとそれぞれ金線などのワイヤにより電気的に接続され、その周囲が図示しない樹脂によりモールドされる。なお、１７はパシベーション膜である。
【０００４】
このように、ＣＯＣタイプの半導体装置は、親チップ１と子チップ間はそれぞれ電極端子上に設けられるバンプ電極１１、２１などを介して接続され、親チップ１の周囲に設けられる電極パッドを介して、外部リードとワイヤを介して接続されている。したがって、親チップ１と子チップ２間の信号伝達に関しては、それぞれのバンプ電極を介して信号の授受が行われる。しかし、複数個ある子チップ２ａ、２ｂ間で信号の授受を行う場合、親チップ１の半導体層中、または半導体層表面の絶縁膜中に配線を形成しておき、その配線の一部を電極端子として絶縁膜から露出させ、前述の子チップの電極端子と接続することによりお互いに信号の授受を行っている。
【０００５】
【発明が解決しようとする課題】
前述のように、ＣＯＣタイプの半導体装置で、親チップと子チップ間で信号の授受を行う場合には、親チップと子チップとのバンプ電極により接続することで問題ないが、複数個ある子チップ間で信号を授受する場合、一々親チップ内に形成される配線を介して行わなければならない。そのため、せっかく親チップなどを汎用化して、用途に応じた回路を子チップで形成するような場合でも、搭載する子チップに応じて、親チップ内に配線を形成する必要があり、親チップの汎用化に制約を受けるという問題がある。
【０００６】
さらに、子チップの１つに外部から信号を伝達する必要のある場合があるが、その場合でも、親チップの電極パッドを介して親チップ内の配線を通じて子チップに伝達しなければならず、親チップの汎用性の妨げとなっている。
【０００７】
さらに、前述の親チップと子チップとの接続は、Ａｕなどのバンプ電極を介して行われるため、４５０℃程度の高温で行わないと、良好な電気的接続が得られない。しかし、その際、半導体基板も高温になると共に、バンプ電極にかかる圧力が半導体基板にもかかるため、バンプ電極の下側には、双方のチップ共に素子を形成することができず、半導体基板の利用効率が低下するという問題がある。
【０００８】
本発明の目的は、ワイヤボンディングするための金線などのワイヤと電極パッドとの接合を温度の過度な上昇や超音波などによる圧力の印加を招かないで行い得る構造とし、その電極パッドの下側にも素子形成を可能として、集積度を向上し得る半導体装置を提供することにある。
【０００９】
【課題を解決するための手段】
本発明による半導体装置は、半導体層に回路素子が形成された半導体基板と、該半導体基板の表面に形成された電極パッドと、前記半導体基板の表面に形成され、電極パッドを露出する開口を有する絶縁膜と、前記電極パッドと外部リードとを電気的に接続するためのＡｕワイヤと、前記電極パッドに接して設けられたバリアメタル層と、該バリアメタル層上に形成されるＡｕ層と、該Ａｕ層上に設けられるＳｎ層またはＡｕ-Ｓｎ合金層とを有し、前記バリアメタル層と前記Ａｕワイヤとの間にＡｕ-Ｓｎ合金層が形成され、前記電極パッドの下の前記半導体基板にも回路素子が形成されている。
【００１０】
この構造にすることにより、ワイヤボンディングの際に、超音波によりボンディングパッド部を擦る必要がなくなり、圧力も殆どかからないで接続作業をすることができるため、ワイヤボンディングをする電極パッドの下の半導体層に、トランジスタなどの素子を形成しても、ボンディングの際に素子が損傷するという問題はなくなる。その結果、同じ半導体チップ内に沢山の素子を形成することができ、集積度を向上させることができる。
【００１１】
【発明の実施の形態】
つぎに、図面を参照しながら本発明の半導体装置について説明をする。本発明による半導体装置は、図１０にその一実施形態である一部の断面構造が示されているように、基板の表面に電極パッド１３ａが形成され、その基板の表面に電極パッド１３ａが露出するように開口を有する絶縁膜１７ａが形成され、電極パッド１３ａと外部リードとがＡｕワイヤ６により電気的に接続されている。この電極パッド１３ａとＡｕワイヤ６との間にＡｕ-Ｓｎ合金層が形成されている。
【００１２】
このワイヤボンディングをする外部接続用電極パッド１３ａの表面にＡｕ層とＳｎ被膜とを設ける方法は、後述するＣＯＣタイプの半導体装置に限らず、また、絶縁膜最表面に配線を形成する半導体装置に限らず、通常の半導体装置に適用することができる。この例が図１０に示されるように、ＣＯＣタイプでなくても、半導体装置では必ず外部リードとＡｕ線などで接続するため、ワイヤボンディングされる電極パッドを有しているが、このワイヤボンディングをする場合、超音波で擦りつけながら加熱して行っている。そのため、半導体層にも圧力がかかり、外部接続用電極パッド１３ａの下の半導体層にはトランジスタなどの素子を形成することはできず、半導体チップの縮小化に限界がある。しかし、この電極パッド１３ａ上にもＡｕ層１９ａを０.５〜１μｍ程度、Ｓｎ被膜１９ｂを０.２〜０.４μｍ程度づつ設けておくことにより、前述のバンプ電極の接続と同様に、ワイヤボンディング時の２５０〜３５０℃への加熱によりＡｕ-Ｓｎ合金層が形成され、超音波で擦ることなく、容易にボンディングすることができる。なお、図１０において、１７ａは絶縁膜、１４は前述と同様のＴｉＷなどからなるバリアメタル層である。
【００１３】
この構造にすることにより、電極パッド１３ａ下の半導体層にトランジスタなどの回路素子２０を形成しても、破損させたり、特性変動を来したりすることはない。その結果、ワイヤボンディング工程が容易になると共に、接着の信頼性が向上すると共に、その電極パッドの下にも素子形成をすることができるため、集積度の向上を図ることができる。
【００１４】
前述の基板側は、親チップ上に１個または複数個の子チップを搭載するＣＯＣタイプの構造や、配線膜構造など、種々の構造に形成することができ、以下にその例を説明する。図１にその一例である断面構造ならびに配線部の断面および平面の説明図が示されるように、第１半導体チップ１の表面側に複数個の第２半導体チップ２ａ、２ｂがバンプ電極１１、２１を介して接合される場合に、複数個の第２半導体チップのうち、２個の第２半導体チップ２ａ、２ｂの電極端子２２ａ、２２ｂ同士を直接接続する配線９が、第１半導体チップ１のパシベーション膜１７の最表面に形成されている。
【００１５】
図１に示される例では、その配線部の拡大説明図が図１（ｂ）に示されるように、第１半導体チップ１および第２半導体チップ２ａ、２ｂ共に、バンプ電極１１、２１が５〜３０μｍ程度の厚さに形成され、第１半導体チップ１のバンプ電極１１の形成と同時に、第２半導体チップ２ａ、２ｂ間で直接接続する必要のある電極端子２１ａ、２１ｂに対応する電極端子１２ａ間に配線９が形成されている。バンプ電極１１、２１自身は、従来と同様に形成され、たとえば図１（ｂ）に示されるように、Ａｌなどからなる電極端子１２上に、バリアメタル層１４がスパッタリング、真空蒸着などにより２層または３層構造で成膜してパターニングすることにより形成される。バリアメタル層１４の第１層にはＴｉまたはＣｒが、第２層にはＷ、Ｐｔ、Ａｇ、Ｃｕ、Ｎｉなどが、第３層にはＡｕなどが用いられ、全体で０.２〜２μｍ程度の厚さに形成される。そして、その上にバンプ電極１１が、Ａｕ、Ｃｕなどの金属を電解メッキなどの方法により前述の厚さに形成される。なお、第２半導体チップ２のバンプ電極２１も同様に形成される。なお、図１では、電極端子が直接半導体層に設けられているように示されているが、半導体層に接続される場合も、層間絶縁膜内の配線に接続される場合もある。
【００１６】
このバンプ電極１１を形成する際に、第２半導体チップ２ａ、２ｂを直接接続する必要のある電極端子２２ａ、２２ｂに対応する第１半導体チップ１の電極端子１２ａ同士が連結されるように、バリアメタル層１４およびバンプ電極材料が設けられることにより、配線９が形成されている。したがって、バリアメタル層１４をパターニングする際に、配線が形成されるようにパターニングするだけで、従来のバンプ電極１１形成工程の作業だけで同時に配線９を形成することができる。この配線９は、バンプ電極１１のように幅広に形成する必要はなく、図１（ｃ）に配線９部の平面説明図が示されるように、配線部の幅が狭くなるようにパターニングされてもよい。
【００１７】
バンプ１１、２１の接続部は、図２に説明図が示されるように、Ａｕからなるバンプ電極１１上にＳｎ被膜１１ａが設けられることにより、Ａｕの融点は、１０６４℃程度（同一金属同士であるため、加圧しながら加熱することにより、４５０℃程度で融着する）であるのに対して、Ｓｎの融点は、２３２℃程度であり、２３０℃程度になると溶融し、Ａｕと共晶を形成して合金化し、２８０℃程度でＡｕ-Ｓｎ合金からなる合金層３がその接合面に形成されて、両者のバンプ電極１１、２１が溶着する。すなわち、半導体基板に形成される回路素子などに対しては支障のない低い温度で両バンプ電極１１、２１を融着させることができる。
【００１８】
このように、バンプ電極１１、２１には融点の高い金属を用い、融点の低い金属と合金化しやすい金属被膜をその接合面に設けて合金化させることにより、低い温度で接着することができ、しかもバンプとしては融点の高い金属で高い強度を維持することができる。すなわち、ハンダ付けの温度に対しては支障のない低い温度で両バンプ電極１１、２１を融着させることができる。なお、配線９上にはＳｎ被膜が設けられないようにしてもよいし、設けられても構わない。また、第２半導体チップ側のバンプ電極のみにＳｎ被膜を設けるようにしてもよい。また、この観点からは、ＡｕとＳｎとに限られるものではない。
【００１９】
前述の図２に示されるように、Ｓｎ被膜１１ａは一方のバンプ電極１１のみに形成されることが、接合面の合金層を形成しやすいため好ましい。すなわち、ＡｕとＳｎとの接触部が合金化して接合するため、両方のバンプにＳｎ被膜が設けられていると、Ｓｎ被膜とＳｎ被膜との接触部が直ちには接合せず、バンプ電極表面のＡｕ層とＳｎ被膜との接触部から合金化し、Ａｕが接合部に拡散して合金化することにより接合するため、Ａｕ層とＳｎ被膜とが接触するように形成されることが好ましい。しかし、両方のバンプ電極に設けるＳｎ被膜を非常に薄くすることにより、容易にＡｕが拡散するため、両方のバンプ電極に形成してもよい。また、接合するバンプ電極同士に大小がある場合、小さい方のバンプ電極にＳｎ被膜を設ける方が、接合部の合金化部分が少なく、後で分離する可能性のある場合には都合がよい。
【００２０】
一方、接合した２つの半導体チップを取り外す可能性がなく、しっかりと接続するためには、図３に示されるように、バンプ電極１１の上面だけではなく、側面周囲全体も被覆するようにＳｎ被膜１１ａを形成することにより、合金化すれば合金層３は小さいバンプ電極１１の周囲から大きい方のバンプ電極２１にフィレット３ａを形成し、強力に接合することができる。なお、図３において、電極パッドなどは省略して図示すると共に、図２と同じ部分には同じ符号を付してある。また、前述のバンプ電極の上面のみにＳｎ被膜を設ける場合でも、バンプ電極に大小がある場合、大きい方のバンプ電極に形成すれば、接着強度を強くすることができる。
【００２１】
前述の合金層は、完全な共晶合金になると、Ａｕ８０ｗｔ％（重量％、以下同じ）、Ｓｎ２０ｗｔ％になるが、接合時に充分に温度を上げる訳ではないため、接合部は完全な共晶合金にはなりにくい。しかし、完全な共晶合金にならなくても、Ａｕが６５ｗｔ％以上であれば、強固な接合が得られると共に、分離する場合でも３００℃程度に加熱することにより、接合部のみを分離することができる。また、合金層を形成しないで、Ａｕ層のみが存在することが、機械的強度が強く好ましい。ＳｎよりＡｕの拡散が１０倍程度以上大きいため、たとえば接合時の温度、時間、Ｓｎ層の量などの調整により、Ａｕが６５ｗｔ％以上の合金層で、Ａｕ層が１００ｗｔ％の部分が残るように接合することができる。さらに好ましくは、Ａｕ-Ｓｎ共晶層が０.８μｍ以上５μｍ以下であることが好ましい。このようにするには、Ｓｎ被膜の厚さを０.１〜４μｍ程度にすることにより得られる。この際、完全なＡｕ層を残すためには、Ａｕ層（バンプ電極）の厚さを厚く形成することにより得られる。
【００２２】
第１半導体チップ１は、たとえばデジタル信号プロセッサなどの論理回路などが半導体基板に形成され、その表面には層間絶縁膜や配線膜などが設けられ、最終的にメモリ素子などの第２半導体チップ２との接続用電極端子１２と、外部リードとの接続用の電極パッド１３がＡｌなどによりその表面に形成されている。この際、その表面に接続する第２半導体チップと直接には接続する必要はないが、複数の第２半導体チップ２ａ、２ｂ間で接続する電極端子２２ａ、２２ｂに対応する部分にも電極端子１２ａを形成しておく。この電極端子１２、１２ａ上に前述のようにバリアメタル層１４を介してバンプ電極１１が形成されると共に、第２半導体チップ２ａ、２ｂ間で接続する電極端子２２ａ、２２ｂに対応する電極端子１２ａ同士を接続する配線９を、バンプ電極１１と同じ材料で同時に形成する。なお、通常の第２半導体チップ２ａ、２ｂと直接接続する電極端子１２には、配線は形成されないで、バンプ電極１１のみが形成される。この回路素子（半導体素子）や半導体基板の表面に形成される配線、電極端子、絶縁膜などは、通常の半導体装置の製造工程と同様に形成される。なお、通常のシリコン基板でなくても、ＧａＡｓなど化合物半導体基板に形成されてもよい。
【００２３】
第２半導体チップ２は、たとえばメモリ素子がマトリクス状に形成されたもので、第１半導体チップ１と接続される部分、複数個ある第２半導体チップ同士で接続される部分、外部リードなどに接続される部分などが電極端子２２として半導体基板の表面に形成され、その電極端子２２の表面にも前述の第１半導体チップ１と同様に、Ａｕなどによりバンプ電極２１が形成されている。このバンプ電極２１の表面にも、前述のＳｎ被膜が形成されていてもよい。また、第１半導体チップ１にはＳｎ皮膜が形成されないで、第２半導体チップ２のバンプ電極２１のみにＳｎ被膜が形成されてもよい。この第２半導体チップ２は、このようなＩＣでなくても、トランジスタ、ダイオード、キャパシタなどのディスクリート部品などで、半導体基板に形成されないものでもかまわない。とくに、静電破壊防止用の複合半導体装置にする場合、ディスクリートの保護ダイオードなどを第２半導体チップとして搭載することが、大容量の保護素子を内蔵することができるため好ましい。
【００２４】
この第１半導体チップ１と第２半導体チップ２のバンプ電極１１、２１同士の接続は、たとえば第１半導体チップ１を加熱し得る基板ステージ上に載置して、マウンターにより第２半導体チップ２をそのバンプ同士が一致するように位置合せをして、加圧しながら３００℃程度に加熱することにより、融着することができる。
【００２５】
第１および第２の半導体チップ１、２の隙間には、後述するように、エポキシ樹脂、エポキシ-フェノール樹脂またはエラストマーなどからなる絶縁性樹脂が充填される。この接合された半導体チップ１、２ａ、２ｂは、通常の半導体装置の製造と同様に、リードフレームからなるダイアイランド４上にボンディングされ、さらに各リード５と金線などのワイヤ６によりボンディングされ、モールド成形により樹脂パッケージ８が形成される。そして、リードフレームから各リードが切断分離された後に、フォーミングされることにより、図１（ａ）に示されるような形状の半導体装置が得られる。
【００２６】
図１に示される例は、第２半導体チップ２ａ、２ｂの電極端子の接続部のみが示されているが、図４に、第１半導体チップ１の平面説明図が示されるように、第１半導体チップ１の電極パッド１３ａから、第１半導体チップ１の内部配線を経由しないで、直接第２半導体チップ２ｂ、２ｃに接続する配線９ｃを形成することもできるが、この点については後述する図９で詳述する。すなわち、図４に示される例では、たとえば３個の第２半導体チップ２ａ〜２ｃが搭載される構造になっており、第２半導体チップ２ａ、２ｂ、２ｃ間、および第２半導体チップ２ｂ、２ｃと電極パッド１３ａ間での電極端子の接続が複数組形成されており、このような場合でも、その第２半導体チップ２ａと２ｂ、２ｂと２ｃ同士で接続する電極端子に対応する第１半導体チップ１の電極端子１２ａ間、および電極端子１２ｂと電極パッド１３ａとの間を接続する配線９、９ｃが、そのバンプ電極１１と同時に形成されている。なお、図４では、バンプ電極１１の下側の電極端子１２、１２ａ、１２ｂの符号も付してある。図４において、１３は通常の外部リードと接続用の電極パッドである。
【００２７】
本発明の半導体装置でＣＯＣタイプにする場合、第１半導体チップ上に複数個の第２半導体チップを接続することができ、第２半導体チップ同士を接続する必要のある電極端子を、それぞれの電極端子に対応する第１半導体チップの部分に電極端子を形成しておき、その電極端子にバンプを形成する際、またはバンプと接合し得る金属膜を形成する際に、そのバンプまたは金属膜と同じ材料で、同時にその電極端子間を接続する配線を形成し、バンプ電極により第１半導体チップと第２半導体チップとを接合することにより、第２半導体チップ間の接続を行っているため、第２半導体チップの内容を変えることにより第２半導体チップ間の接続関係が変化させても、第１半導体チップの配線設計などを変更することなく、バンプ形成の際のパターニングを変えるだけで所望の接続をすることができる。
【００２８】
すなわち、半導体層、またはその表面の絶縁膜中に配線を形成する方法では、第１半導体装置の設計を変形する必要があり、第１半導体チップの設計を変更しなければならないが、本発明によれば、パシベーション膜の最表面に接続用の配線を形成しているため、バンプ電極またはバンプ電極と接合し得る金属膜を設ける際に所望のパターンの配線を形成するだけで、第１半導体チップの設計仕様を全然変更する必要がない。
【００２９】
前述の例では、第１半導体チップ１および第２半導体チップ２（２ａ、２ｂ）の両方の電極端子にバンプ電極１１、２１が形成されていたが、バンプ電極はその接続部にあれば一方だけでもよい。また、配線９は、前述のようにバンプ電極１１の厚さと同じ厚さにする必要はなく、通常の配線と同様の数μｍ以下でよい。この観点から、たとえば図５に示されるように、バンプ電極は第２半導体チップ２（２ａ、２ｂ）のみに設け、第１半導体チップ１には、バリア層１４と第２半導体チップ２のバンプ電極と同じ材料であるＡｕ膜１５を形成し、配線９もバリア層１４とＡｕ膜１５により形成されてもよい。
【００３０】
すなわち、図５において、第２半導体チップ２ａ、２ｂ間を直接接続する電極端子２２ａ、２２ｂに対応する第１の半導体チップ１における電極端子１２ａの上およびその間には、バリアメタル層１４を介して、たとえばＡｕなどからなる０.２〜０.７μｍ程度の厚さの金属膜（Ａｕ膜）１５が設けられている（バリア層１４は前述の例と同じ）。そして、第２半導体チップ２には、前述と同様にＡｕからなるバンプ電極２１およびＳｎ被膜２３が形成されており、そのバンプ電極２１と電極端子１２ａ上のＡｕ膜１５とが融着する構造になっている。この例では、バンプ電極２１上にＳｎ被膜２３が形成されているが、このようにバンプ電極２１上またはＡｕ膜１５上にＳｎ被膜が形成されることにより、バンプとの融着温度を下げることができる。なお、図示しない第１半導体チップ１と第２半導体チップ２との間で接続する電極端子１２も同様にバリア層１４およびＡｕ膜１５が形成され、Ｓｎ被膜などを介して第２半導体チップ２側に設けられるバンプ電極２１とにより融着される。
【００３１】
また、図６に示される例は、両方にバンプ電極がなく、配線同士のみで接続する例である。すなわち、第１半導体チップ１の配線９ａと第２半導体チップ２の配線９ｂとがその一部の表面にＳｎ被膜が形成され、他の部分には、たとえばポリイミド、ＳｉＯ2などの絶縁膜３１が設けられることにより、Ｓｎ被膜の設けられた部分のみで接合部３２が形成され、接続することができる。この構造では、配線のＡｕ層がバンプのように厚くなく、薄くなるため、接合後にＳｎが拡散しないＡｕ層のみの部分ができない可能性が大きいが、わざわざバンプ電極を形成しなくてもよいため、工数低減を図れると共に、絶縁層を介して接合されるため、接合部のみに力がかかるという問題もなくなる。
【００３２】
前述のように、第１半導体チップ１と第２半導体チップ２との間隙部には、絶縁性樹脂が充填されることが好ましい。すなわち、図７に示されるように、第１半導体チップ１と第２半導体チップ２とを接合した後に、その間隙部にポリイミドなどからなる絶縁性樹脂を滴下して硬化させることにより、アンダーフィル（絶縁性樹脂層）７を形成する。このようなアンダーフィル７が形成されることにより、面全体で両チップが接触するため、パンプ電極の下側の半導体層に形成される素子に損傷を来すという問題がなくなる。すなわち、半導体チップ周囲がモールド樹脂によりパッケージングされる際に、半導体チップ間の隙間にはモールド樹脂が侵入し難い。そのため、隙間が生じていると樹脂パッケージ８により両半導体チップが押し付けられ、バンプ電極部分のみでその圧力を吸収する必要があるため、前述のような問題が生じるが、アンダーフィル７が設けられることにより、そのような問題を引き起こすことがなくなる。
【００３３】
この場合、ポリイミド（弾性率４.５ＧＰａ）を用いることがＡｕの弾性率と近いため好ましい。アンダーフィル７の弾性率がバンプ電極１１、２１と近いと、バンプ電極を融着してから温度が下がった場合でも、バンプ電極にかかる圧縮力と半導体チップの他の部分にかかる圧縮力とが均等になるため、力が分散してバンプ電極と共に面として第２半導体チップ２を支持することができ、バンプ電極部分のみに特別な力がかかることがなくなる。
【００３４】
さらに、アンダーフィル７として使用する樹脂は、熱収縮率（熱膨張率）が４％以下のものを使用することが好ましい。熱収縮率が大きいと、硬化時に３００℃程度に上げた温度が室温に下がったときに、バンプ電極であるＡｕの熱収縮率より大きくなり、バンプ電極部分のみに圧縮力として働き、その下の半導体層へのダメージが大きくなるからである。
【００３５】
また、図１に示される例では、電極パッド１２ａ表面と絶縁膜１７表面とで段差があり、その上に設けられる配線９も平坦にならないため、接合を行いにくいという問題がある。これを解消するため、図８に示されるように、絶縁膜１７上に、たとえばポリイミドなどからなる絶縁膜３３を形成してから、配線９を形成することにより平坦な配線９となり、接合しやすくなるというメリットがある。
【００３６】
上述の例は、子チップである第２半導体チップ同士を配線で接続する例であったが、第２半導体チップに直接外部から信号を伝達したい場合もある。そのような場合でも、従来は、親チップである第１半導体チップにその接続用配線を絶縁膜内、または半導体層中に形成しておき、その配線端部の電極端子に第２半導体チップの電極端子を接続しなければならなかった。このような問題を解決する実施形態が図９に示されている。すなわち、第１半導体チップ１および第２半導体チップ２の接続は図１に示される例と同様であるが、第１半導体チップ１の外部接続用電極パッド１３ａに接続して、絶縁膜１７の最表面に図１に示される配線９と同様の配線９ｃが形成され、第２半導体チップ２ｃが接続されることにより、電極パッド１３ａに接続される外部リードから直接第２半導体チップ２ｃに信号を伝達することができる。なお、６は外部リードと接続するワイヤであり、この配線９ｃおよび電極パッド１３ａは、図４の平面説明図に同じ符号で示されている部分と対応する。
【００３７】
なお、このワイヤ６をボンディングする電極パッド１３ａにも、図９に示されるように、配線９ｃを連続して形成し、Ａｕ層およびＳｎ被膜を形成しておくことにより、ワイヤボンディングの際に、超音波などで表面を擦りながらボンディングしなくても、容易にワイヤボンディングすることができる。
【００３８】
この構造にすることにより、親チップである第１半導体チップの設計変更をすることなく、子チップである第２半導体チップの変更により、直接第２半導体チップに信号を外部から伝達する必要のある場合でも、第１半導体チップの外表面に配線を形成することにより、直接信号を伝達できるようになる。なお、この配線９ｃも、前述の図１に示される配線９と同様に、バンプ形成の際に同時に形成することができる。
【００３９】
以上の各例では、第１半導体チップ１の電極端子にバリア層とＡｕ膜を設けたが、Ａｕ膜には限定されず、第２半導体チップ２に設けられるバンプ電極と融着しやすいバンプと接合し得る材料であればよい。
【００４０】
【発明の効果】
以上説明したように、本発明によれば、外部からの信号などでもワイヤボンディングにより外部リードとの接続用電極パッドに簡単に接続することができ、第１半導体チップ上に２個以上の第２半導体チップをマウントするＣＯＣタイプの半導体装置にする場合でも、また、複数個の第２半導体チップ間で接続する必要がある場合でも、第１半導体チップのパシベーション膜の最表面に配線を形成することにより接続しているため、第２半導体チップを変更することに伴う第２半導体チップ間同士の配線仕様が異なっても、第１半導体チップの内部設計などを変更することなく、簡単に組み立てることができる。その結果、第１半導体チップの汎用性が向上し、種々のタイプの半導体装置に用いることができる。
【００４１】
また、第２半導体チップ間の接続のみならず、外部リードとの接続用電極パッドと第２半導体チップを接続するための電極端子との間にも、絶縁膜の最表面に配線を形成することにより、第２の半導体チップに直接外部から信号を伝達する場合でも、第１半導体チップをそれ専用に作製しなくても、簡単に外部から信号を伝送することができる。
【００４２】
さらに、接続部にＡｕ層とＳｎ層またはＡｕ-Ｓｎ合金層を設けて行うことにより、Ａｕ-Ｓｎ共晶合金層が低温で形成されるため、接続の際に、超音波などを印加したり、高温にしたりしなくてもよいため、電極パッドの直ぐ下の半導体層にも素子形成をすることができ、集積密度を向上させることができる。
【００４３】
また、ワイヤボンディングをするための電極パッドにもＡｕ層とＳｎ層またはＡｕ-Ｓｎ合金層を設けることにより、ワイヤボンディング時に超音波などにより圧力をかけなくても容易にワイヤボンディングをすることができる。その結果、電極パッドの下まで素子を形成することができ、半導体素子の集積度を向上させることができる。
【図面の簡単な説明】
【図１】 本発明による半導体装置の基板側をＣＯＣタイプにした場合におけるＣＯＣ部分の断面説明図および配線部の拡大説明図である。
【図２】 バンプ電極の接合部をＡｕ-Ｓｎ合金層で形成した場合の説明図である。
【図３】 図１のバンプ電極にＳｎ被膜を一方のバンプ電極の全面に設ける場合の説明図である。
【図４】 本発明による半導体装置の第１半導体チップの平面説明図である。
【図５】 本発明による半導体装置のＣＯＣ部分の他の例を示す配線部の拡大説明図である。
【図６】 第１半導体チップと第２半導体チップとの接合部にバンプを形成しないで接合する例の説明図である。
【図７】 第１半導体チップと第２半導体チップとの隙間に絶縁性樹脂を充填した例の説明図である。
【図８】 図１に示される例の変形例を示す説明図である。
【図９】 本発明による半導体装置の他の実施形態を説明する図である。
【図１０】 本発明の半導体装置の一実施形態である、ワイヤボンディング用電極パッドにＡｕ層とＳｎ層とを設けてワイヤボンディングする例の説明図である。
【図１１】 従来のＣＯＣタイプで２個のチップを１個のチップにマウントした例のチップ間の接続部を説明する図である。
【符号の説明】
１ 第１半導体チップ
２(2a,2b) 第２半導体チップ
９ 配線
１１ バンプ電極
１２ 電極端子
１７ パシベーション膜
２１ バンプ電極
２２ 電極端子[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a so-called chip on chip (hereinafter referred to as COC) type semiconductor device in which a plurality of semiconductor chips face each other and are electrically connected.Semiconductor devices with a structure that connects the electrode pads and external leads with wiresAbout. For more details,By avoiding excessive pressure during wire bonding, circuit elements can be formed under the electrode pads,When multiple chips are formed and a plurality of second semiconductor chips are directly connected to the surface of the first semiconductor chip, the wiring connected between the second semiconductor chips depends on the internal design of the first semiconductor chip. The present invention relates to a semiconductor device that can freely change the connection between second semiconductor chips.
[0002]
[Prior art]
  Conventionally, when a semiconductor device is configured by a combination of circuits such as a combination of a memory element and a logic circuit thereof, for example, the occupied area is reduced by three-dimensionalization, the parasitic capacitance of a high-frequency circuit is reduced, and the circuit Generalization of parts (for example, the memory element part is generalized and the drive circuit part is changed according to the application). In a large integrated circuit, the manufacturing conditions differ depending on the circuit part and it may be difficult to make a single chip. For this reason, a COC type semiconductor device having a structure in which a semiconductor circuit is manufactured by a plurality of chips and another semiconductor chip (child chip) is connected to one semiconductor chip (parent chip) may be used. . In recent years, as shown in FIG. 11, there is a trend toward multi-chips in which a plurality of child chips are provided.
[0003]
  In FIG. 11, the electrode terminals 22 of the second semiconductor chips (child chips) 2 a and 2 b are connected to the electrode terminals 12 of the first semiconductor chip (parent chip) 1 via the respective bump electrodes 11 and 21. . The parent chip 1 is bonded to an island (not shown) made of a lead frame, and each electrode pad (not shown) provided on the outer peripheral side of the parent chip 1 is electrically connected by a lead (not shown) provided around the island and a wire such as a gold wire. Are connected to each other, and the periphery thereof is molded with a resin (not shown). Reference numeral 17 denotes a passivation film.
[0004]
  Thus, in the COC type semiconductor device, the parent chip 1 and the child chip are connected via the bump electrodes 11 and 21 provided on the electrode terminals, respectively, and the electrode pads provided around the parent chip 1 are connected. And connected to the external lead through a wire. Therefore, regarding the signal transmission between the parent chip 1 and the child chip 2, signals are exchanged via the respective bump electrodes. However, when signals are exchanged between a plurality of child chips 2a and 2b, wiring is formed in the semiconductor layer of the parent chip 1 or in the insulating film on the surface of the semiconductor layer, and a part of the wiring is connected to the electrode. Signals are exchanged by exposing them from the insulating film as terminals and connecting them to the electrode terminals of the aforementioned child chips.
[0005]
[Problems to be solved by the invention]
  As described above, in a COC type semiconductor device, when signals are exchanged between a parent chip and a child chip, there is no problem by connecting the bump electrodes between the parent chip and the child chip. When signals are exchanged between chips, they must be performed via wiring formed in the parent chip. Therefore, even when the parent chip is generalized and a circuit corresponding to the application is formed by the child chip, it is necessary to form wiring in the parent chip according to the mounted child chip. There is a problem of being restricted by generalization.
[0006]
  Furthermore, it may be necessary to transmit a signal from the outside to one of the child chips, but even in that case, the signal must be transmitted to the child chip through the wiring in the parent chip via the electrode pad of the parent chip. This hinders the versatility of the parent chip.
[0007]
  Furthermore, since the connection between the parent chip and the child chip described above is performed via a bump electrode such as Au, good electrical connection cannot be obtained unless the connection is performed at a high temperature of about 450 ° C. However, at that time, the temperature of the semiconductor substrate also becomes high, and the pressure applied to the bump electrode is also applied to the semiconductor substrate. Therefore, an element cannot be formed on both chips under the bump electrode. There is a problem that usage efficiency decreases.
[0008]
  An object of the present invention is to provide a structure in which a wire such as a gold wire for wire bonding and an electrode pad can be bonded without causing an excessive increase in temperature or application of pressure due to ultrasonic waves. Another object is to provide a semiconductor device capable of improving the degree of integration by enabling element formation on the side.
[0009]
[Means for Solving the Problems]
  A semiconductor device according to the present invention includes:Semiconductor with circuit elements formed in the semiconductor layerA substrate and the substratesemiconductorAn electrode pad formed on the surface of the substrate;semiconductorAn insulating film formed on the surface of the substrate and having an opening exposing the electrode pad; an Au wire for electrically connecting the electrode pad and an external lead;A barrier metal layer provided in contact with the electrode pad, an Au layer formed on the barrier metal layer, an Sn layer or an Au—Sn alloy layer provided on the Au layer,And saidBarrier metal layerAnd an Au—Sn alloy layer between the Au wire and the Au wireAnd circuit elements are also formed on the semiconductor substrate under the electrode pads.ing.
[0010]
  With this structure, it is not necessary to rub the bonding pad portion with ultrasonic waves during wire bonding, and connection work can be performed with little pressure applied, so the semiconductor layer under the electrode pad for wire bonding In addition, even if an element such as a transistor is formed, the problem that the element is damaged during bonding is eliminated. As a result, many elements can be formed in the same semiconductor chip, and the degree of integration can be improved.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
  Next, the semiconductor device of the present invention will be described with reference to the drawings. A semiconductor device according to the present invention includes:As shown in FIG. 10 that shows a partial cross-sectional structure as an embodiment of the present invention, an electrode pad 13a is formed on the surface of the substrate, and an insulation is provided so that the electrode pad 13a is exposed on the surface of the substrate. A film 17 a is formed, and the electrode pad 13 a and the external lead are electrically connected by the Au wire 6. An Au—Sn alloy layer is formed between the electrode pad 13 a and the Au wire 6.
[0012]
  The method of providing the Au layer and the Sn coating on the surface of the external connection electrode pad 13a for wire bonding is as follows:To be described laterThe present invention is not limited to a COC type semiconductor device, and is not limited to a semiconductor device in which a wiring is formed on the outermost surface of an insulating film, and can be applied to a normal semiconductor device.This exampleAs shown in FIG. 10, even if it is not a COC type, a semiconductor device always has an electrode pad to be wire-bonded in order to connect it with an external lead and an Au wire or the like. It is heated while being rubbed with ultrasonic waves. Therefore, pressure is also applied to the semiconductor layer, and an element such as a transistor cannot be formed in the semiconductor layer under the external connection electrode pad 13a, and there is a limit to downsizing of the semiconductor chip. However, the Au layer 19a is provided on the electrode pad 13a by about 0.5 to 1 μm, and the Sn coating 19b is provided by about 0.2 to 0.4 μm, so that the wire is connected in the same manner as the connection of the bump electrode. An Au—Sn alloy layer is formed by heating to 250 to 350 ° C. during bonding, and bonding can be easily performed without rubbing with ultrasonic waves. In FIG. 10, 17a is an insulating film, and 14 is a barrier metal layer made of TiW or the like as described above.
[0013]
  With this structure, even if the circuit element 20 such as a transistor is formed in the semiconductor layer under the electrode pad 13a, it may be damaged or the characteristics may be changed.DoThere is nothing. As a result, the wire bonding process is facilitated, the reliability of adhesion is improved, and the element can be formed under the electrode pad, so that the degree of integration can be improved.
[0014]
  The substrate side described above can be formed in various structures such as a COC type structure in which one or a plurality of child chips are mounted on a parent chip, and a wiring film structure. Examples thereof will be described below.One of them in Figure 1ExampleA plurality of second semiconductor chips 2a and 2b are bonded to the front surface side of the first semiconductor chip 1 via bump electrodes 11 and 21, as shown in FIG. In this case, among the plurality of second semiconductor chips, the wiring 9 that directly connects the electrode terminals 22a and 22b of the two second semiconductor chips 2a and 2b is the outermost portion of the passivation film 17 of the first semiconductor chip 1. It is formed on the surface.
[0015]
  In the example shown in FIG. 1, as shown in an enlarged explanatory view of the wiring portion in FIG. 1B, the bump electrodes 11, 21 are 5 to 5 in both the first semiconductor chip 1 and the second semiconductor chips 2 a, 2 b. Between the electrode terminals 12a corresponding to the electrode terminals 21a and 21b which are formed to a thickness of about 30 μm and need to be directly connected between the second semiconductor chips 2a and 2b simultaneously with the formation of the bump electrodes 11 of the first semiconductor chip 1 A wiring 9 is formed on the substrate. The bump electrodes 11 and 21 themselves are formed in the same manner as in the prior art. For example, as shown in FIG. 1B, a barrier metal layer 14 is formed on the electrode terminal 12 made of Al or the like by sputtering, vacuum deposition or the like. Alternatively, it is formed by forming a film with a three-layer structure and patterning. Ti or Cr is used for the first layer of the barrier metal layer 14, W, Pt, Ag, Cu, Ni or the like is used for the second layer, Au or the like is used for the third layer, and the total is 0.2 to 2 μm. It is formed to a thickness of about. A bump electrode 11 is formed on the above-described thickness by a method such as electrolytic plating with a metal such as Au or Cu. The bump electrode 21 of the second semiconductor chip 2 is formed in the same manner. In FIG. 1, the electrode terminals are shown as directly provided in the semiconductor layer. However, the electrode terminals may be connected to the semiconductor layer or to the wiring in the interlayer insulating film.
[0016]
  When the bump electrode 11 is formed, a barrier is provided so that the electrode terminals 12a of the first semiconductor chip 1 corresponding to the electrode terminals 22a and 22b that need to be directly connected to the second semiconductor chips 2a and 2b are connected to each other. The wiring 9 is formed by providing the metal layer 14 and the bump electrode material. Therefore, when patterning the barrier metal layer 14, the wiring 9 can be formed simultaneously only by the work of the conventional bump electrode 11 forming process only by patterning so that the wiring is formed. The wiring 9 does not need to be formed as wide as the bump electrode 11, and is patterned so that the width of the wiring portion becomes narrow, as shown in FIG. Also good.
[0017]
  As shown in FIG. 2, the connection part of the bumps 11 and 21 is provided with the Sn coating 11a on the bump electrode 11 made of Au, so that the melting point of Au is about 1064 ° C. Therefore, the melting point of Sn is about 232 ° C., and when it reaches about 230 ° C., it melts and eutectic with Au. When formed and alloyed, an alloy layer 3 made of an Au—Sn alloy is formed on the bonding surface at about 280 ° C., and both the bump electrodes 11 and 21 are welded. That is, the bump electrodes 11 and 21 can be fused at a low temperature that does not hinder circuit elements and the like formed on the semiconductor substrate.
[0018]
  Thus, the bump electrodes 11 and 21 can be bonded at a low temperature by using a metal having a high melting point and forming a metal film that is easy to alloy with a metal having a low melting point on the bonding surface to form an alloy. In addition, the bumps can maintain high strength with a metal having a high melting point. That is, both the bump electrodes 11 and 21 can be fused at a low temperature that does not hinder the soldering temperature. The Sn film may not be provided on the wiring 9 or may be provided. Further, an Sn coating may be provided only on the bump electrode on the second semiconductor chip side. From this point of view, it is not limited to Au and Sn.
[0019]
  As shown in FIG. 2 described above, it is preferable that the Sn coating 11a is formed only on one bump electrode 11 because an alloy layer on the bonding surface can be easily formed. That is, since the contact portion between Au and Sn is alloyed and bonded, if the Sn coating is provided on both bumps, the contact portion between the Sn coating and the Sn coating is not immediately bonded, and the surface of the bump electrode is not bonded. It is preferable that the Au layer and the Sn coating are formed in contact with each other since the alloy is formed from the contact portion between the Au layer and the Sn coating and the Au is diffused and alloyed in the joint. However, since the Au film is easily diffused by making the Sn coating provided on both bump electrodes very thin, it may be formed on both bump electrodes. In addition, when the bump electrodes to be joined are large and small, it is convenient to provide the Sn coating on the smaller bump electrode when there are few alloyed portions of the joint and there is a possibility of separation later.
[0020]
  On the other hand, there is no possibility of removing two bonded semiconductor chips, and in order to make a firm connection, as shown in FIG. 3, not only the upper surface of the bump electrode 11 but also the entire periphery of the side surface is covered with the Sn coating. If the alloy layer 3 is alloyed by forming 11a, the fillet 3a can be formed on the larger bump electrode 21 from the periphery of the small bump electrode 11 and strongly bonded. In FIG. 3, electrode pads and the like are omitted, and the same parts as those in FIG. Even when the Sn coating is provided only on the upper surface of the bump electrode, if the bump electrode is large or small, if it is formed on the larger bump electrode, the adhesive strength can be increased.
[0021]
  When the above alloy layer becomes a complete eutectic alloy, it becomes Au 80 wt% (wt%, the same applies hereinafter) and Sn 20 wt%. However, since the temperature is not sufficiently increased at the time of bonding, the bonded portion is a complete eutectic alloy. It is hard to become. However, even if it is not a complete eutectic alloy, if Au is 65 wt% or more, strong bonding can be obtained, and even when separated, only the joint is separated by heating to about 300 ° C. Can do. Further, it is preferable that only an Au layer exists without forming an alloy layer because of its high mechanical strength. Since the diffusion of Au is about 10 times larger than Sn, for example, by adjusting the bonding temperature, time, amount of Sn layer, etc., an alloy layer with Au of 65 wt% or more and a portion with 100 wt% of Au layer remains. Can be joined. More preferably, the Au—Sn eutectic layer is 0.8 μm or more and 5 μm or less. For this purpose, the thickness of the Sn coating is obtained by setting it to about 0.1 to 4 μm. At this time, in order to leave a complete Au layer, it can be obtained by forming the Au layer (bump electrode) thick.
[0022]
  The first semiconductor chip 1 includes, for example, a logic circuit such as a digital signal processor formed on a semiconductor substrate, and an interlayer insulating film, a wiring film, and the like are provided on the surface, and finally a second semiconductor chip 2 such as a memory element. And electrode pads 13 for connection to external leads are formed on the surface with Al or the like. At this time, it is not necessary to directly connect to the second semiconductor chip connected to the surface, but the electrode terminal 12a is also provided in a portion corresponding to the electrode terminals 22a and 22b connected between the plurality of second semiconductor chips 2a and 2b. Is formed. As described above, the bump electrode 11 is formed on the electrode terminals 12 and 12a via the barrier metal layer 14, and the electrode terminals 12a corresponding to the electrode terminals 22a and 22b connected between the second semiconductor chips 2a and 2b. Wirings 9 that connect each other are simultaneously formed of the same material as the bump electrodes 11. Note that no wiring is formed on the electrode terminals 12 directly connected to the normal second semiconductor chips 2a and 2b, and only the bump electrodes 11 are formed. The circuit elements (semiconductor elements), wirings formed on the surface of the semiconductor substrate, electrode terminals, insulating films, and the like are formed in the same manner as in a normal semiconductor device manufacturing process. Note that it may be formed on a compound semiconductor substrate such as GaAs instead of a normal silicon substrate.
[0023]
  The second semiconductor chip 2 is formed, for example, in a matrix of memory elements, and is connected to a portion connected to the first semiconductor chip 1, a portion connected between a plurality of second semiconductor chips, an external lead, and the like. A portion to be formed or the like is formed as an electrode terminal 22 on the surface of the semiconductor substrate, and a bump electrode 21 is formed on the surface of the electrode terminal 22 with Au or the like, similarly to the first semiconductor chip 1 described above. The aforementioned Sn film may also be formed on the surface of the bump electrode 21. Further, the Sn coating may be formed only on the bump electrode 21 of the second semiconductor chip 2 without forming the Sn coating on the first semiconductor chip 1. The second semiconductor chip 2 may not be such an IC but may be a discrete component such as a transistor, a diode, or a capacitor that is not formed on the semiconductor substrate. In particular, in the case of a composite semiconductor device for preventing electrostatic breakdown, it is preferable to mount a discrete protection diode or the like as the second semiconductor chip because a large-capacity protection element can be incorporated.
[0024]
  The connection between the bump electrodes 11 and 21 of the first semiconductor chip 1 and the second semiconductor chip 2 is performed, for example, by placing the first semiconductor chip 1 on a substrate stage that can be heated and mounting the second semiconductor chip 2 by a mounter. The bumps can be fused by aligning the bumps so that they coincide with each other and heating to about 300 ° C. while applying pressure.
[0025]
  As will be described later, the gap between the first and second semiconductor chips 1 and 2 is filled with an insulating resin made of an epoxy resin, an epoxy-phenol resin, an elastomer, or the like. The bonded semiconductor chips 1, 2a, and 2b are bonded onto the die island 4 formed of a lead frame in the same manner as in the manufacture of a normal semiconductor device, and further bonded to each lead 5 with a wire 6 such as a gold wire, A resin package 8 is formed by molding. Then, after each lead is cut and separated from the lead frame, forming is performed to obtain a semiconductor device having a shape as shown in FIG.
[0026]
  In the example shown in FIG. 1, only the connection portions of the electrode terminals of the second semiconductor chips 2 a and 2 b are shown. As shown in FIG. 4, the first semiconductor chip 1 is illustrated in plan view. It is also possible to form the wiring 9c directly connected to the second semiconductor chips 2b and 2c from the electrode pad 13a of the semiconductor chip 1 without going through the internal wiring of the first semiconductor chip 1, but this point will be described later. 9 will be described in detail. That is, in the example shown in FIG. 4, for example, three second semiconductor chips 2a to 2c are mounted, and between the second semiconductor chips 2a, 2b, and 2c and between the second semiconductor chips 2b and 2c. A plurality of pairs of electrode terminals are formed between the electrode pads 13a and the electrode pads 13a. Even in such a case, the first semiconductor chips corresponding to the electrode terminals connected between the second semiconductor chips 2a and 2b, 2b and 2c are formed. Wirings 9 and 9c that connect between one electrode terminal 12 a and between the electrode terminal 12 b and the electrode pad 13 a are formed simultaneously with the bump electrode 11. In addition, in FIG. 4, the code | symbol of the lower electrode terminals 12, 12a, 12b of the bump electrode 11 is also attached | subjected. In FIG. 4, 13 is a normal external lead and an electrode pad for connection.
[0027]
  Semiconductor device of the present inventionWhen using the COC type, Connecting a plurality of second semiconductor chips on the first semiconductor chipIt is possibleThe electrode terminals that need to be connected to each other between the second semiconductor chips are formed on the first semiconductor chip portions corresponding to the respective electrode terminals, and bumps are formed on the electrode terminals, or the bumps When forming a metal film that can be bonded to the bump, a wiring that connects the electrode terminals is formed at the same time using the same material as the bump or the metal film, and the first semiconductor chip and the second semiconductor chip are bonded by the bump electrode. Thus, since the connection between the second semiconductor chips is performed, even if the connection relationship between the second semiconductor chips is changed by changing the contents of the second semiconductor chip, the wiring design of the first semiconductor chip can be changed. Without changing, it is possible to achieve a desired connection simply by changing the patterning during bump formation.
[0028]
  That is, in the method of forming a wiring in the semiconductor layer or the insulating film on the surface thereof, it is necessary to change the design of the first semiconductor device and the design of the first semiconductor chip must be changed. According to the above, since the wiring for connection is formed on the outermost surface of the passivation film, the first semiconductor chip can be formed only by forming the wiring of a desired pattern when providing the bump electrode or the metal film that can be bonded to the bump electrode. There is no need to change the design specifications.
[0029]
  In the above example, the bump electrodes 11 and 21 are formed on the electrode terminals of both the first semiconductor chip 1 and the second semiconductor chip 2 (2a, 2b). But you can. Further, the wiring 9 does not need to have the same thickness as the bump electrode 11 as described above, and may be several μm or less, which is the same as a normal wiring. From this point of view, for example, as shown in FIG. 5, the bump electrode is provided only on the second semiconductor chip 2 (2a, 2b), and the first semiconductor chip 1 includes the barrier layer 14 and the bump electrode of the second semiconductor chip 2. The Au film 15, which is the same material as the above, may be formed, and the wiring 9 may also be formed by the barrier layer 14 and the Au film 15.
[0030]
  That is, in FIG. 5, the barrier metal layer 14 is interposed between and between the electrode terminals 12a in the first semiconductor chip 1 corresponding to the electrode terminals 22a and 22b that directly connect the second semiconductor chips 2a and 2b. For example, a metal film (Au film) 15 made of Au or the like and having a thickness of about 0.2 to 0.7 μm is provided (the barrier layer 14 is the same as the above example). The second semiconductor chip 2 is formed with a bump electrode 21 and an Sn film 23 made of Au as described above, and the bump electrode 21 and the Au film 15 on the electrode terminal 12a are fused. It has become. In this example, the Sn coating 23 is formed on the bump electrode 21. By forming the Sn coating on the bump electrode 21 or the Au film 15 in this way, the fusion temperature with the bump is lowered. Can do. The electrode terminal 12 connected between the first semiconductor chip 1 and the second semiconductor chip 2 (not shown) is similarly formed with a barrier layer 14 and an Au film 15, and the second semiconductor chip 2 side through an Sn coating or the like. And a bump electrode 21 provided on the substrate.
[0031]
  Further, the example shown in FIG. 6 is an example in which both have no bump electrode and are connected only by wiring. That is, the Sn film is formed on a part of the surface of the wiring 9a of the first semiconductor chip 1 and the wiring 9b of the second semiconductor chip 2, and polyimide, SiO, etc. are formed on the other part.2By providing the insulating film 31 or the like, the joint portion 32 can be formed and connected only at the portion where the Sn film is provided. In this structure, since the Au layer of the wiring is not as thick and thin as the bump, there is a high possibility that only the Au layer where Sn does not diffuse after bonding is formed, but it is not necessary to form a bump electrode. In addition to reducing the man-hours, since the bonding is performed through the insulating layer, there is no problem of applying a force only to the bonding portion.
[0032]
  As described above, the gap between the first semiconductor chip 1 and the second semiconductor chip 2 is preferably filled with an insulating resin. That is, as shown in FIG. 7, after bonding the first semiconductor chip 1 and the second semiconductor chip 2, an insulating resin made of polyimide or the like is dropped and cured in the gap, thereby underfill ( Insulating resin layer) 7 is formed. By forming such an underfill 7, both chips are in contact with each other over the entire surface, so that the problem of damaging elements formed in the semiconductor layer below the pump electrode is eliminated. That is, when the periphery of the semiconductor chip is packaged with the mold resin, the mold resin hardly enters the gap between the semiconductor chips. Therefore, if there is a gap, both semiconductor chips are pressed by the resin package 8 and it is necessary to absorb the pressure only by the bump electrode portion. This causes the above-mentioned problem, but the underfill 7 is provided. Therefore, such a problem is not caused.
[0033]
  In this case, it is preferable to use polyimide (elastic modulus 4.5 GPa) because it is close to the elastic modulus of Au. If the elastic modulus of the underfill 7 is close to that of the bump electrodes 11 and 21, the compressive force applied to the bump electrode and the compressive force applied to the other part of the semiconductor chip even when the temperature drops after the bump electrode is fused. Since the force is evenly distributed, the second semiconductor chip 2 can be supported as a surface together with the bump electrode, and no special force is applied only to the bump electrode portion.
[0034]
  Furthermore, it is preferable that the resin used as the underfill 7 has a thermal shrinkage rate (thermal expansion coefficient) of 4% or less. When the heat shrinkage rate is large, when the temperature raised to about 300 ° C. at the time of curing is lowered to room temperature, it becomes larger than the heat shrinkage rate of Au as a bump electrode, and acts as a compressive force only on the bump electrode portion. This is because damage to the semiconductor layer is increased.
[0035]
  Further, in the example shown in FIG. 1, there is a step between the surface of the electrode pad 12a and the surface of the insulating film 17, and the wiring 9 provided thereon is not flat, so that there is a problem that bonding is difficult. In order to solve this problem, as shown in FIG. 8, an insulating film 33 made of, for example, polyimide is formed on the insulating film 17, and then the wiring 9 is formed to form a flat wiring 9, which is easy to join. There is a merit that
[0036]
  The above example is an example in which the second semiconductor chips which are the child chips are connected to each other by wiring. However, there is a case where it is desired to directly transmit a signal from the outside to the second semiconductor chip. Even in such a case, conventionally, the connection wiring is formed in the insulating film or in the semiconductor layer in the first semiconductor chip which is the parent chip, and the second semiconductor chip is connected to the electrode terminal at the end of the wiring. The electrode terminals had to be connected. An embodiment for solving such a problem is shown in FIG. That is, the connection between the first semiconductor chip 1 and the second semiconductor chip 2 is the same as in the example shown in FIG. 1, but it is connected to the external connection electrode pad 13a of the first semiconductor chip 1 and A wiring 9c similar to the wiring 9 shown in FIG. 1 is formed on the surface, and the second semiconductor chip 2c is connected to transmit a signal directly from the external lead connected to the electrode pad 13a to the second semiconductor chip 2c. can do. Reference numeral 6 denotes a wire connected to an external lead, and the wiring 9c and the electrode pad 13a correspond to the portions indicated by the same reference numerals in the plan explanatory view of FIG.
[0037]
  In addition, as shown in FIG. 9, the wire 9c is continuously formed on the electrode pad 13a for bonding the wire 6, and the Au layer and the Sn film are formed. Even if bonding is not performed while rubbing the surface with ultrasonic waves, wire bonding can be easily performed.
[0038]
  With this structure, it is necessary to directly transmit a signal from the outside to the second semiconductor chip by changing the second semiconductor chip as the child chip without changing the design of the first semiconductor chip as the parent chip. Even in this case, signals can be directly transmitted by forming wiring on the outer surface of the first semiconductor chip. The wiring 9c can be formed at the same time as the bump formation, similarly to the wiring 9 shown in FIG.
[0039]
  In each of the above examples, the barrier layer and the Au film are provided on the electrode terminal of the first semiconductor chip 1. However, the invention is not limited to the Au film, and the bump electrode provided on the second semiconductor chip 2 is easily fused. Any material that can be joined may be used.
[0040]
【The invention's effect】
  As explained above, according to the present invention,Even external signals can be easily connected to electrode pads for connection to external leads by wire bonding.COC type semiconductor device in which two or more second semiconductor chips are mounted on the first semiconductor chipEven if you want toEven when it is necessary to connect a plurality of second semiconductor chips, since the connection is made by forming a wiring on the outermost surface of the passivation film of the first semiconductor chip, the second semiconductor chip is changed. Even if the wiring specifications between the second semiconductor chips are different, it can be easily assembled without changing the internal design of the first semiconductor chip. As a result, the versatility of the first semiconductor chip is improved and it can be used for various types of semiconductor devices.
[0041]
  Further, not only the connection between the second semiconductor chips but also the wiring on the outermost surface of the insulating film is formed between the electrode pad for connection with the external lead and the electrode terminal for connecting the second semiconductor chip. Thus, even when a signal is directly transmitted from the outside to the second semiconductor chip, the signal can be easily transmitted from the outside without producing the first semiconductor chip exclusively for the second semiconductor chip.
[0042]
  Furthermore, since an Au—Sn eutectic alloy layer is formed at a low temperature by providing an Au layer and an Sn layer or an Au—Sn alloy layer at the connection portion, ultrasonic waves or the like are applied at the time of connection.ApplyOr high temperatureShishishiSince it is not necessary, elements can also be formed in the semiconductor layer immediately below the electrode pad, and the integration density can be improved.
[0043]
  Also, by providing an Au layer and an Sn layer or an Au—Sn alloy layer on the electrode pad for wire bonding, wire bonding can be easily performed without applying pressure by ultrasonic waves or the like during wire bonding. . As a result, the element can be formed up to the bottom of the electrode pad, and the degree of integration of the semiconductor element can be improved.
[Brief description of the drawings]
FIG. 1 shows a semiconductor device according to the present invention.Of the COC part when the substrate side is COC typeIt is a sectional explanatory view and an enlarged explanatory view of a wiring part.
FIG. 2 is an explanatory diagram when a bump electrode joint is formed of an Au—Sn alloy layer.
FIG. 3 is an explanatory diagram in the case where an Sn film is provided on the entire surface of one bump electrode on the bump electrode of FIG. 1;
FIG. 4 is an explanatory plan view of a first semiconductor chip of a semiconductor device according to the present invention.
FIG. 5 shows a semiconductor device according to the present invention.Of the COC partotherExampleFIG.
FIG. 6 is an explanatory diagram of an example in which the first semiconductor chip and the second semiconductor chip are bonded without forming bumps at the bonding portion.
FIG. 7 is an explanatory diagram of an example in which an insulating resin is filled in a gap between a first semiconductor chip and a second semiconductor chip.
FIG. 8 is an explanatory diagram showing a modification of the example shown in FIG. 1;
FIG. 9 is a diagram illustrating another embodiment of a semiconductor device according to the present invention.
FIG. 10One embodiment of a semiconductor device of the present invention,It is explanatory drawing of the example which provides an Au layer and Sn layer in the electrode pad for wire bonding, and performs wire bonding.
FIG. 11 is a diagram for explaining a connecting portion between chips in an example in which two chips are mounted on one chip in a conventional COC type.
[Explanation of symbols]
    1 First semiconductor chip
  2 (2a, 2b) second semiconductor chip
    9 Wiring
  11 Bump electrode
  12 electrode terminals
  17 Passivation membrane
  21 Bump electrode
  22 Electrode terminal

Claims (13)

半導体層に回路素子が形成された半導体基板と、該半導体基板の表面に形成された電極パッドと、前記半導体基板の表面に形成され、電極パッドを露出する開口を有する絶縁膜と、前記電極パッドと外部リードとを電気的に接続するためのＡｕワイヤと、前記電極パッドに接して設けられたバリアメタル層と、該バリアメタル層上に形成されるＡｕ層と、該Ａｕ層上に設けられるＳｎ層またはＡｕ-Ｓｎ合金層とを有し、前記バリアメタル層と前記Ａｕワイヤとの間にＡｕ-Ｓｎ合金層が形成され、前記電極パッドの下の前記半導体基板にも回路素子が形成されてなる半導体装置。A semiconductor substrate having circuit elements formed on the semiconductor layer, and the electrode pads formed on the surface of the semiconductor substrate, is formed on a surface of the semiconductor substrate, an insulating film having an opening exposing the electrode pad, the electrode pad An Au wire for electrically connecting the external lead and the external lead, a barrier metal layer provided in contact with the electrode pad, an Au layer formed on the barrier metal layer, and provided on the Au layer A Sn layer or an Au—Sn alloy layer , an Au—Sn alloy layer is formed between the barrier metal layer and the Au wire, and a circuit element is also formed on the semiconductor substrate under the electrode pad. ing Te semiconductor device. 第２半導体チップが前記半導体基板の表面上にバンプ電極を介して接合され、前記半導体基板がダイアイランドにボンディングされ、前記半導体基板および前記第２半導体チップが樹脂パッケージに封止されて、外部リードの一部が前記樹脂パッケージから外部に露出している請求項１記載の半導体装置。 A second semiconductor chip is bonded onto the surface of the semiconductor substrate via a bump electrode, the semiconductor substrate is bonded to a die island, the semiconductor substrate and the second semiconductor chip are sealed in a resin package, and external leads the semiconductor device of part according to claim 1, wherein exposed to the outside from the resin package. 前記バリアメタル層が３層構造を有し、前記半導体基板側の第１層がＴｉまたはＣｒ、前記第１層の上の第２層がＷ、Ｐｔ、Ａｇ、ＣｕおよびＮｉの少なくとも１種、該第２層上の第３層がＡｕ、である請求項１または２記載の半導体装置。The barrier metal layer has a three-layer structure, the first layer on the semiconductor substrate side is Ti or Cr, the second layer on the first layer is at least one of W, Pt, Ag, Cu, and Ni, the semiconductor device according to claim 1 or 2, wherein the third layer on the second layer are Au,. 前記バリアメタル層上の前記Ａｕ層上に前記Ｓｎ層が設けられ、該Ｓｎ層上に前記Ａｕワイヤがボンディングされることにより、前記Ａｕ層または前記ＡｕワイヤのＡｕおよび前記Ｓｎ層のＳｎのそれぞれの少なくとも一部により前記Ａｕ-Ｓｎ合金層が形成されてなる請求項１〜３のいずれか１項に記載の半導体装置。The barrier is provided the Sn layer on the Au layer on the metal layer by the Au wire on said Sn layer is bonded, each of Sn of the Au layer or the Au wire Au and the Sn layer The semiconductor device according to claim 1, wherein the Au—Sn alloy layer is formed by at least a part of the semiconductor device. 前記バリアメタル層上の前記Ａｕ層上に前記Ａｕ-Ｓｎ合金層が設けられ、該Ａｕ-Ｓｎ合金層上に前記Ａｕワイヤがボンディングされてなる請求項１〜３のいずれか１項に記載の半導体装置。It said barrier said Au-Sn alloy layer on the Au layer on the metal layer is provided, the Au wire to the Au-Sn alloy layer is according to any one of claims 1 to 3 formed by bonding Semiconductor device. 前記半導体基板の表面に、前記電極パッドとは異なる第２半導体チップと接続するための電極端子を有し、該電極端子上にバンプ電極が形成されてなる請求項１〜５のいずれか１項に記載の半導体装置。The surface of the semiconductor substrate, an electrode terminal for connecting to a different second semiconductor chip and the electrode pads, any one of claim 1 to 5 bump electrode on the electrode terminal is formed the semiconductor device according to. 前記第２半導体チップが、前記半導体基板の表面上に前記バンプ電極を介して接合されてなる請求項６記載の半導体装置。The semiconductor device according to claim 6, wherein the second semiconductor chip is bonded to the surface of the semiconductor substrate via the bump electrode. 前記第２半導体チップがバンプ電極を有しており、該バンプ電極と前記電極端子上のバンプ電極とが接合されてなる請求項７記載の半導体装置。The semiconductor device according to claim 7, wherein the second semiconductor chip has a bump electrode, and the bump electrode and the bump electrode on the electrode terminal are joined. 前記半導体基板の表面に、前記電極端子とはさらに異なり、前記第２半導体チップとは異なる他の第２半導体チップと接続するための第２電極端子を有し、該第２電極端子と前記電極端子とを接続する配線が前記絶縁膜上に形成されてなる請求項７または８記載の半導体装置。Wherein a surface of said semiconductor substrate, Ri further Unlike the electrode terminal, a second electrode terminal for connecting to a different other of the second semiconductor chip and the second semiconductor chip, a second electrode terminal 9. The semiconductor device according to claim 7, wherein a wiring for connecting the electrode terminal is formed on the insulating film. 前記半導体基板と前記第２半導体チップとの間隙部に絶縁性樹脂が充填されてなる請求項７〜９のいずれか１項に記載の半導体装置。The semiconductor device according to any one of the semiconductor substrate and the second semiconductor chip and the insulating resin into the gap portion of the is filled claims 7-9. 前記絶縁性樹脂がポリイミドである請求項１０記載の半導体装置。The semiconductor device according to claim 10 , wherein the insulating resin is polyimide. 前記半導体基板の表面に設けられる前記電極パッドと接続して、前記絶縁膜上に延伸する配線が形成され、前記第２半導体チップと接続されてなる請求項７〜１１のいずれか１項に記載の半導体装置。Connected with the electrode pads provided on a surface of the semiconductor substrate, the wiring that extends over the insulating film is formed, according to any one of the second semiconductor chip and connected comprising claims 7-11 Semiconductor device. 前記配線が、前記電極端子と前記第２電極端子とを連結するように形成され、平面視で該２つの電極端子の間の配線部の幅が、前記電極端子部分の幅より狭くなるように形成されてなる請求項９記載の半導体装置。Said wiring, said formed so that the electrode terminal and coupling the second electrode terminal, so that the width of the wiring portion between the two electrode terminals in plan view becomes narrower than the width of the electrode terminal portions The semiconductor device according to claim 9 formed.
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