JPH0588020B2 - - Google Patents

Info

Publication number
JPH0588020B2
JPH0588020B2 JP61068291A JP6829186A JPH0588020B2 JP H0588020 B2 JPH0588020 B2 JP H0588020B2 JP 61068291 A JP61068291 A JP 61068291A JP 6829186 A JP6829186 A JP 6829186A JP H0588020 B2 JPH0588020 B2 JP H0588020B2
Authority
JP
Japan
Prior art keywords
processor
data transfer
delay time
transfer delay
load distribution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61068291A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62226264A (ja
Inventor
Ryuzo Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP61068291A priority Critical patent/JPS62226264A/ja
Publication of JPS62226264A publication Critical patent/JPS62226264A/ja
Publication of JPH0588020B2 publication Critical patent/JPH0588020B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Exchange Systems With Centralized Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
JP61068291A 1986-03-28 1986-03-28 マルチプロセツサシステムのデ−タ転送遅延時間選択方式 Granted JPS62226264A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61068291A JPS62226264A (ja) 1986-03-28 1986-03-28 マルチプロセツサシステムのデ−タ転送遅延時間選択方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61068291A JPS62226264A (ja) 1986-03-28 1986-03-28 マルチプロセツサシステムのデ−タ転送遅延時間選択方式

Publications (2)

Publication Number Publication Date
JPS62226264A JPS62226264A (ja) 1987-10-05
JPH0588020B2 true JPH0588020B2 (fr) 1993-12-20

Family

ID=13369522

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61068291A Granted JPS62226264A (ja) 1986-03-28 1986-03-28 マルチプロセツサシステムのデ−タ転送遅延時間選択方式

Country Status (1)

Country Link
JP (1) JPS62226264A (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6629253B1 (en) 1999-12-30 2003-09-30 Intel Corporation System for efficient management of memory access requests from a planar video overlay data stream using a time delay
DE10056036A1 (de) * 2000-11-11 2002-05-29 Bosch Gmbh Robert Anker
JP4000479B2 (ja) 2003-05-22 2007-10-31 日本電気株式会社 データ通信システム、通信装置、及びその通信プログラム

Also Published As

Publication number Publication date
JPS62226264A (ja) 1987-10-05

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