JPH0586582B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention always makes the memory contents on the standby side of the duplex controller equal to those on the control side, thereby minimizing the influence on the process when switching control authority. The present invention relates to a control method for a duplex controller suitable for.

[Conventional technology]

A duplex controller that shares only a process input/output device (hereinafter abbreviated as PI/O) is known, for example, from Japanese Patent Laid-Open No. 57-86972. Japanese Patent Laid-Open No. 57-86972 discloses that a duplex control unit captures a destination address at which a controller having control authority (hereinafter referred to as control authority) performs a writing operation to a blunt database within its own controller, The data stored in the destination address is read from the control side and written to the corresponding address of a controller that does not have control authority (hereinafter abbreviated as standby side). In this method, only the control side performs control calculations, and by writing all changed data on the control side, the memory contents of both controllers are matched.

Furthermore, a method is known in which, in a dual-system controller, both the control side and the standby side perform calculations in synchronization according to the same input.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, in Japanese Patent Application Laid-Open No. 57-86972, since the standby side controller is not operated, all memory contents that have changed on the control side must be written to the standby side, and the redundant controller is , high speed is required, and dedicated hardware is required to realize it. In addition, when performing control calculations by synchronizing both the control side and the standby side, a control unit is required to synchronize the control side and the standby side, and failure of the synchronization control unit will cause problems for both systems of the redundant controller. Leads to down. In addition, the latter does not have a synchronization control section and the coupling between both controllers is loose, and the PI/O
In this method, only the data fetched from the control side is sent to the standby side, and the standby side performs calculations based on the above data. Since the standby side does not have a synchronization control section, the control performance start timing on the standby side depends on the timing when the above data is received from the control side. In this case, the control calculation on the standby side will not be able to perform calculations based on the same data as the control side, leading to a mismatch in the memory contents of both controllers, and the control calculation will be delayed. When the power is switched, there is a risk of disturbance to the process.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for controlling a redundant controller that can minimize the influence on processes when switching control rights between controllers.

[Means for solving problems]

The control side controller inputs process data from the PI/O at each predetermined control cycle and performs control calculations, and also sends the process data input from the PI/O to the standby side controller, and the standby side controller receives the process data. Control calculations are executed at a predetermined calculation cycle each time the signal is received.

[Effect]

The control side controller performs control calculations every control cycle, and the standby side controller performs control calculations at the timing when it receives process data from the control side controller.
Control calculations for one control cycle are performed. As a result, the control calculation results of both controllers become equal with a certain phase delay. Therefore, the content of the plant database can be made to follow the control-side controller without copying the entire plant database of both controllers.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows the overall configuration of this embodiment. Controllers A and B are duplex controllers that share a PI/O (process input/output device) 11 through a PI/O bus 10. The two controllers are connected by a dataway 12 and a switching logic bus 9, and the former is used not only between controllers A and B, but also for exchanging data with the man-machine system and other controllers. transmission line, the latter is
This is a bus for communicating the diagnostic results of the diagnostic circuits 6A and 6B of both controllers. Furthermore, the data way 12 is duplicated in this embodiment, making transmission between both controllers more reliable. 1A and 1B are central processing units (hereinafter referred to as CPU)
), and input/output devices to the PI/O 11 according to the programs in the memories 2A and 2B, respectively.
It controls data transmission/reception processing and control calculation processing through the data way 12. Furthermore, CPU1A,
The CPU 1B has a periodic timer and can start each of the above programs at regular intervals. 2A, 2B
is a memory, which includes PI/O data input processing that performs input/output processing to the PI/O 11, PI/O output processing, control calculation processing, and data transmission processing and reception processing that performs data transmission and reception through the data way 12. Each program, the work data area necessary for executing each program, and the substance of the plant database are stored. The memory maps of memories 2A and 2B are the same. 3A and 3B are transmission interfaces (hereinafter abbreviated as transmission I/F), and 4A and 4B are transmission controllers, which transmit and receive data between the data way 12 and the transmission and reception buffers in the memories 2A and 2B. 6A and 6B are diagnostic circuits, each connected to CPU1 in its own controller.
A, 1B, memories 2A, 2B, transmission controllers 4A, 4B self-diagnosis, and through the switching logic bus 9, the other controller is notified of the diagnosis results of the own controller, and the other controller's diagnosis results are recognized. 7A and 7B are process input/output interfaces (hereinafter abbreviated as PI/OIF)
, and each performs input/output control when the CPUs 1A and 1B perform input/output processing to the PI/O 11. 8A,
8B is a switching circuit, and each diagnostic circuit 6A, 6
When it is determined in B that the own controller has control authority, it is turned on to enable access to PI/O11, and when it is determined that the own controller does not have control authority, it is turned off and access to PI/O is enabled. is not allowed.
In addition, these CPUs, memory, diagnostic circuits, PL/O
IF is system bus 5A for controller A,
The controllers B are connected to each other via a system bus 5B, allowing data and control signals to be exchanged. Especially transmission controllers 4A and 4B
When receiving data from the data way 12, the CPUs 1A and 1B each generate an interrupt as a control signal to notify data reception.

FIG. 2 is a conceptual diagram showing the flow of data in an embodiment of the present invention. Since the following operations and configurations are the same for both controllers A and B, controller A will be described as the controller. Processing 21
a, 21b, and 21c are PI/O data input processing, control calculation, and PI/O output processing, respectively, which are processed by the CPU 1A in this order every time they are activated.
Processes 25 and 26 are PI/O import data reception processing, respectively.
This is PI/O capture data transmission processing. These processes are stored in the memory 2A as a program. In addition, 23 is a PI/O output data storage area,
24 is the PI/O import data storage area, 27, 28
are a transmission buffer and a reception buffer, respectively, and areas for both are secured on the memory 2A. Reference numeral 29 is a control right flag, which is a register that reflects whether or not the own controller has the control right, and is present in the diagnostic circuit 6A and can be referenced from the CPU 1A via the system bus 5A.

First, the operation will be explained assuming that the own controller has control authority.

The CPU 1A performs the periodic timer process shown in FIG. 3 every time the periodic timer counts up. In other words, each time the periodic timer is activated, step S
At step 31, the control cycle counter is updated. If it matches the control period specified in step S32, the control period counter is reset in step S33. Thereafter, in step S34, it is determined by referring to the control right flag 29 whether or not the own controller has the control right. When there is control authority, the process of step S35 is performed, and processes 21a to 21a are executed.
21c is started. That is, the processes 21a to 21c are activated every control cycle when there is control authority. Among these activated processes, process 21a performs PI/O data input processing.

Figure 4 shows the detailed flow of the PI/O data input process. In step S41, it is determined whether there is a control right based on the control right flag 29. If there is a control right, in step S42, the process data is transferred from the PI/O 11 via the PI/O bus 10, the switching circuit 8A, and the PI/OIF 7A. is transferred to the PI/O capture data storage area in process 24, and the PI/O data is transferred to controller B in step S43.
Requests to send captured data. Specifically, the PI/O capture data transmission process that receives the PI/O capture request transfers the PI/O capture data to the transmission buffer 27 to the PI/O capture data storage area in process 24 . The above data is transferred from the transmission buffer 27 to the transmission controller 4A, to the transmission I/F 3A, to the dataway 1.
2 to controller B. To transfer the PI/O capture data to the sending buffer 27,
In this embodiment, the control period and data way 1
This is because the transmission to 2 is asynchronous. Next, in process 21b, control calculation processing, input correction calculation, DDC (Direct Digital Control) calculation, and sequence control calculation are performed using the data in the PI/O capture data storage area 24 as input. The calculation result of the process 21b is set in the PI/O output data storage area 23. After processing 21b is completed, processing 21c, PI/O output processing, is performed. The flow of this process is as shown in FIG. That is, referring to the control right flag 29, if there is a control right, the calculation result of the control calculation process is output from the PI/O output data storage area 23 to the PI/O 11 as a control output.

Next, the operation when the own controller does not have control authority will be explained. If the own controller does not have control authority, the transmission controller 4A transfers the PI/O import data received from the controller B via the data way 12 to the memory 2 via the transmission I/F 3A.
After storing it in the reception buffer 28 in A, the interrupt is notified to the CPU 1A via the system bus 5A (hereinafter,
This interrupt is called a reception interrupt). The CPU 1A, which has been notified of the reception interrupt, executes the reception interrupt processing shown in FIG. In this reception interrupt processing, step S61
The control right flag 29 is referred to. If the control authority exists, the received data is read as invalid data. If there is no control right, the process 25 performs PI/O capture data reception processing, transfers the received data from the reception buffer 28 to the PI/O capture data storage area 24, and starts processes 21a to 21c in step S62. . Here, the processes 21a to 21c are activated by the periodic timer process shown in FIG. 3 when the own controller has control authority. If the own controller does not have control authority, the activation process of step S35 is passed in the determination process of step S34, so that processes 21a to 21c are not activated in each control cycle. In other words, when there is no control right, the activation factor for the processes 21a to 21c is only a reception interrupt from the partner controller. The process 21a determines in step S41 that there is no control right. Therefore, steps S42 and S43 are passed. Therefore, the PI/O captured data received via the data way 12 is set in the PI/O captured data storage area 24.
In the control calculation process of process 21b, the same calculation is performed regardless of the presence or absence of control authority. This process is P
Calculations are performed by referring to the 24 PI/O input data storage area without inputting them directly from the I/O, and the calculation results are not output to the PI/O by the PI/O in process 23.
Since it is only set in the output data storage area,
Calculations can be performed without being aware of the presence or absence of control rights. Processing 2
1c, as shown in Figure 5, without control right,
Pass the PI/O output of the calculation result.

The following operation is shown in a time chart as shown in FIG. 7. In Fig. 7, time t _o , t _o+1
is the time determined to be the control period in the periodic timer process shown in FIG. At this point, the controllers on the control side and the standby side check the time due to the time difference between the timers.
There is a time difference of Δt between t _o and t _o+1 . According to the present invention, hatching is applied to the time chart on the standby side. In the present invention, at timing 71 when the PI/O import data is received from the control side, a series of processes 21a to 21c are performed based on the received data, so the standby side process 21b
is performed using the same input data as that on the control side, and with a time delay shown at 72, the memory contents on the standby side match those on the control side. Here, suppose that the standby controller also starts the PI/O data input processing to PI/O output processing (processes 21a' to 21c' are not hatched in the time chart) at time t _o in the same way as the control right. If so, process 21
At the start of b′, the PI/O capture data that the control side captured from the PI/O 11 at time t _o has not arrived, so when the control side control calculation process 21b ends and the standby side control calculation process 21b′ The memory contents at the time of termination do not match. The result of the control calculation process started at time t _o is also referred to as the previous value in the process started at time t _o+1 , and mismatches in memory contents are accumulated. This discrepancy occurs when control is switched.
This may cause disturbance to the controlled process, and it is difficult to equalize the memory contents of both controllers by only transmitting PI/O input data. As described above, by applying the method of the present invention, only the PI/O input data is sent from the control side to the standby side, making it possible to match the memory contents of both controllers, making it possible to 2. Minimizes the impact of dual system switching on the process without using additional hardware.
You can configure multiple controllers.

〔Effect of the invention〕

According to the present invention, by transmitting only the input data from the PI/O from the control side controller to the standby side controller, it is possible to track the memory contents related to control calculation processing other than the above data on the standby side. , it is possible to configure a redundant controller in which the transfer of control rights has less influence on the plant without using specific hardware.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram showing an embodiment of the present invention;
Figure 2 is a conceptual diagram showing the flow of data, Figure 3 is a flow diagram of periodic timer processing, Figure 4 is a flow diagram of PI/O data input processing, Figure 5 is a flow diagram of PI/O output processing, and Figure 6 is a flow diagram of PI/O output processing. The figure is a reception interrupt processing flowchart, and FIG. 7 is a time chart showing the operation of the present invention. 1A, 1B...Central processing unit (CPU), 2
A, 2B...Memory, 3A, 3B...Transmission interface (transmission I/F), 4A, 4B...Transmission controller, 5A, 5B...System bus, 6A, 6B...
Diagnostic circuit, 7A, 7B...process input/output device interface (PI/OIF), 8A, 8B...switching circuit,
9...Switching logic bus, 10...Process input/output device bus (PI/O bus), 11...Process input/output device (PI/O).

Claims (1)

[Claims] 1 In a redundant controller in which two controllers that share a process input/output device are connected by a transmission line, and both controllers perform control calculations based on the contents of their respective memories, the controller that has control authority among both controllers The control-side controller takes in process data from the process input/output device at predetermined control intervals, performs control calculation processing, and controls the process data input from the process input/output device to a standby-side controller that does not have control authority. The duplex controller is configured to transmit data every cycle, and each time the standby controller receives process data from the control controller, it performs control calculations for one control cycle based on the received data. control method.