JPH10187472A - Data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processing system with a confirming means for confirming synchronous operation from data on a common bus while reducing a hardware amount and influences upon an output bus. SOLUTION: Concerning the data processing system connecting plural processor elements(PE) in the same configuration to the common bus, one of these plural PE is defined as master equipment 1a, for example, the other PE is defined as slave equipment 1b, and a pair PE 'pairing' the master equipment 1a and the slave equipment 1b exists. A means 10 is provided for suppressing the output of data from the slave equipment 1b during the output of data from the master equipment 1a to the common bus when synchronously operating the master equipment 1a and the slave equipment 1b of this pair PE, holding the data outputted from this master equipment 1a to the common bus and comparing the held data with the data outputted from the slave equipment 1b and the comparing means 10 discriminates coincidence so that the synchronous operation can be maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system and, more particularly, to a common bus that includes a plurality of processor elements having the same configuration and a response device that outputs response data in response to a start command from each processor element. In a data processing system connected to a plurality of processor elements, for example, there is a pair processor element in which one is a master device, the other is a slave device, and the master device and the slave device are paired. The present invention relates to means for confirming a synchronous operation between a master device and a slave device of the pair processor element in a system.

[0002]

2. Description of the Related Art FIG. 6 is a diagram for explaining a conventional data processing system. As shown in this figure, for example,
A plurality of processor elements (PE) 1 including a central processing unit (CPU), an input / output unit, and a bus control unit, and output response data to a start command from the processor element (PE) 1 In a data processing system in which a responding device (for example, a memory controller (MC) 2) is connected to a common bus 3, the plurality of processor elements (P
One or a plurality of pair processor elements (pair PEs) in which one is the master device 1a and the other is the slave device 1b, and the master device 1a and the slave device 1b are “paired”. In the case of existing data processing systems, each conventional pair processor element (pair P
As shown in FIG. 6, the means for confirming that the master device 1a and the slave device 1b of E) are operating synchronously includes a master device 1a and a slave device 1b of each pair processor element (pair PE). For example, when a comparator 4 for comparing bus data for synchronization confirmation is provided between output buses, and the comparator 4 detects a mismatch between the bus data output from the master device 1a and the slave device 1b. ,
The synchronous operation is stopped or an upper-level host (not shown) is interrupted to request a failure recovery process.

[0003]

Accordingly, in a conventional data processing system, a pair processor element (pair P
Master device 1a and slave device 1b constituting E)
In order to confirm the synchronization operation between the processors, the comparator 4 that compares the data on the common bus 3 is connected to each processor element (P
E) It is necessary to provide the comparator 4 in addition to 1. Each time the number of pair processor elements (pair PEs) constituting a “pair” increases, the comparator 4 is added, and the amount of hardware increases. There was a problem.

In addition, it is necessary to bypass the output buses of the master device 1a and the slave device 1b and connect them to the comparator 4, which increases the wiring area of the output bus on the printed circuit board and increases the output by the bypass connection. As the bus length increases, there is a problem that the operating frequency of each processor element (PE) 1 may be restricted.

A plurality of processor elements (PE) 1
In the data processing system, each processor element (PE) 1 is a “paired” processor element (PE)
When changing the configuration to a multiprocessor system in which each processor element (PE) 1 operates independently from a state in which synchronization is performed between 1s, it is necessary to suppress the comparison means in the comparator 4 described above. , Each processor element (PE) 1
There is a problem that it is necessary to control the corresponding comparator 4 from the master device 1a and the slave device 1b constituting the pair processor element (pair PE).

In view of the above-mentioned conventional disadvantages, the present invention can confirm the synchronous operation without providing any special hardware outside the processor element (PE) and without increasing the output bus length. It is an object of the present invention to provide a data processing system capable of constructing a multiprocessor system in which each processor element (PE) operates independently under a simple control.

[0007]

The above-mentioned problems are solved by a data processing system configured as follows.

(1) A plurality of processor elements (PE) 1 having the same configuration and a response device that outputs response data in response to a start command from each processor element (PE) 1 (for example, a memory controller (MC)) For example, in a data processing system in which a plurality of processor elements (PE) 1 are connected to a common bus 3, one of the plurality of processor elements (PE) 1 is a master device 1 a, the other is a slave device 1 b, and the master device 1 a A system in which one or a plurality of pair processor elements (pair PEs) in which the device 1b is a "pair" exists, wherein a master device 1a and a slave device constituting the pair processor elements (pair PE) are provided.
During synchronous operation between 1b, while the master device 1a is outputting data to the common bus 3, the slave device 1b suppresses the data output and holds the data output by the master device 1a to the common bus 3. And a comparing unit 10 for comparing the held data with the data output from the slave device 1b.
The configuration is such that the maintenance of the synchronous operation between the master device 1a and the slave device 1b is determined.

(2) A plurality of processor elements (PE) 1 having the same configuration and a response device that outputs response data in response to a start command from each processor element (PE) 1 (for example, a memory controller (MC)) For example, in a data processing system in which a plurality of processor elements (PE) 1 are connected to a common bus 3, one of the plurality of processor elements (PE) 1 is a master device 1 a, the other is a slave device 1 b, and the master device 1 a A system in which one or a plurality of pair processor elements (pairs PE) in which the device 1b is a “pair” exists, wherein the master device 1a and the slave device
Signal generated inside 1b (bus cycle signal)
Between the processor elements (PE) forming a “pair” via dedicated signal lines, and in each of the master device 1a and the slave device 1b, the transmitted signal is Determining means 11 for determining whether or not they match each other, wherein the determination means 11 determines the match to determine whether to maintain the synchronous operation between the master device 1a and the slave device 1b. I do.

(3) The data processing system according to the above (1) or (2), wherein after receiving a response from the response device (MC) 2 connected to the common bus 3, In the operation cycle, the comparison means 10 starts the determination of the match or the determination means 11 determines the match.

(4) The data processing system according to the above (1) or (2), wherein the operation mode setting means 12 is provided in the processor element (PE) 1 connected to the common bus 3. By setting a predetermined operation mode (multiprocessor mode) in the operation mode setting means 12, each processor element (PE) 1 performs data processing independently.

With such a configuration, the operation of comparing the data on the output bus can be summarized in the slave device 1b, and the number of comparators accompanying the increase in the number of pair processor elements (pair PEs) can be increased. A master device that constitutes each pair processor element (pair PE) without the influence on the output bus of the processor element (PE) 1 (the increase in the output bus length and the limitation of the operating frequency due to the increase in the output bus length) Synchronous operation can be performed between the slave device 1a and the slave device 1b.

Further, by simply setting a predetermined operation mode (multiprocessor mode) in an operation mode setting means (mode register, mode setting pin) 12 provided in each processor element (PE) 1, the corresponding processor is set. Element (PE) 1 can be operated independently.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing an embodiment of the present invention, showing an example of a duplex configuration of a pair processor element (pair PE). FIG. 2 is an example of operation in the input / output system (at the time of read access). An example of the operation time chart of
FIG. 3 shows a configuration example of the multiprocessor system, FIG. 4 shows an example of an operation time chart of the multiprocessor system, and FIG. 5 shows a format example of a start command and a reply command.

In this embodiment, the split system common bus, that is, the master device 1a adds an identifier (DID) of the memory controller (MC) 2, which is one of the phase devices, to the common bus 3 for a predetermined activation. When sending a command, release the common bus 3 without confirming reception at the partner device ｛memory controller (MC)｝ 2 and proceed to the next process.
An example will be described in which the use efficiency of the common bus 3 is improved by repeating between the transmitting and receiving devices. However, the data processing system of the present invention is not limited to this, and an interlocking common bus, that is, It goes without saying that the present invention may be applied to a system in which the common bus 3 cannot be released until a command is transmitted to the partner device and a response from the partner device is confirmed.

Further, in the present embodiment, a plurality of processor elements (PE) 1 having the same configuration and one of response devices which output response data to a start command from each processor element (PE) 1 are provided. A memory controller (MC) 2
In the data processing system connected to the common bus 3, for example, one of the plurality of processor elements (PE) 1 is defined as a master device 1 a and the other
1b, a system in which one or a plurality of pair processor elements (pair PEs) in which the master device 1a and the slave device 1b are “paired” exists, and constitutes the pair processor element (pair PE). When performing synchronous operation between the master device 1a and the slave device 1b
While the master device 1a is outputting data to the common bus 3,
The slave device 1b suppresses the output of data, holds the data output by the master device 1a to the common bus 3, and compares the held data with the data output by the slave device 1b. Each master device 1a
Means for transmitting a signal (bus cycle signal) generated inside the slave device 1b between the processor elements forming a “pair” via a dedicated signal line, and a transmission device for each master device 1a and the slave device 1b. In each case, the internally generated signal comparison determination unit 11 that determines whether the received signal matches its own signal, from the response device (MC) 2 connected to the common bus 3, for example, the first In the operation cycle after the response is received, means for starting the determination of a match by the internally generated signal comparison / determination section 11 and the determination of a match by the bus data comparison / determination section 10 are connected to the common bus 3. Processor element (PE)
A mode register (or a mode setting pin) 12 for setting an operation mode is provided in 1 and a predetermined operation mode (multiprocessor mode) is set in the mode register (or a mode setting pin) 12 so that The means by which the processor element (PE) 1 performs data processing independently is a means necessary for the present embodiment. Note that the same reference numerals throughout the drawings denote the same object, the comparing means described in the claims corresponds to the bus data comparing and determining section 10, the determining means corresponds to the internally generated signal comparing and determining section 11, and the operation mode The setting means corresponds to the mode register (or mode setting pin) 12, the first processor element corresponds to the master device 1a, and the second processor element corresponds to the slave device 1b.

The configuration and operation of the data processing system according to the present invention will be described below with reference to FIGS. FIG. 1 shows an example of the configuration of a duplex system, in which one of a plurality of processor elements (PE) 1 connected to a common bus 3 or a plurality of unillustrated processor elements (PE) 1 is, for example, a master device.
1a, the other as slave device 1b, and the master device
A pair processor element (pair PE) in which the slave processor 1a and the slave device 1b are "paired" is formed, and the contents are the same. The correspondence between the first processor element and the master device 1a and the second processor element The correspondence between the processor element and the slave device 1b is merely an example, and the present invention is not limited to this. The following operations are performed by instructions from a central processing unit (CPU) via an internal bus indicated by a double line.

In this embodiment, a read access will be described as an example. FIG. 2 shows an operation time chart at the time of the read access in the duplex operation. In the read access, when using the split-type common bus, the master device 1a acquires the common bus 3 and
Main memory (MM) for read access to the start command
Sent to the memory controller (MC) 2 that controls
The memory controller (MC) 2 stores the identifier (ID) of the transmission source of the start command in the memory controller (MC) 2.
The read data requested by the start command is stored in the input buffer 14 of the master device 1a and the slave device 1b based on the identifier (ID) of the request source that issued the start command based on the reply command from Then, the synchronous operation of the read access is completed.

Hereinafter, the read access during the duplex operation will be specifically described. First, mode data indicating that the system is a duplex system is set in the mode register 12 from the central processing unit (CPU). The mode register 12 may be a predetermined mode setting pin as described later.
The mode register 12 may be set so that mode data indicating a duplex system is set as a default value when the power is turned on.

Next, each processor element (PE) 1 connected to the common bus 3 monitors a bus request (BR) line (not shown) of the common bus 3 to determine acquisition of bus ownership.

That is, each processor element (PE) 1 has a bus request (B) for all device modules such as all processor elements (PE) 1 connected to the common bus 3.
R) line is connected, and a bus arbiter (distributed bus arbiter) for analyzing the bus request (BR) line is provided, and the user uses the common bus 3 based on the state of the bus request (BR) line. When it is determined that the common bus 3 can be obtained, the common bus 3 is acquired at the timing (phase) shown in FIG. 2 (a), and the bus is transmitted to all the device modules connected to the common bus 3 such as another processor element (PE) 1. Communicates the request (BR). At this time,
The partner device, in this example, for example, a memory controller (MC)
2 is the identifier of the master device 1a that has acquired the common bus 3 (I
Recognize and hold D). Such a bus acquisition operation is called distributed arbitration.

The phase shown in FIG. 2B is a phase of a start command of the master device 1a constituting the pair processor element (pair PE), and is sent from the central processing unit (CPU) to the output buffer 15 of the master device 1a. The stored start command is output to the common bus 3 via the gate 17b.

At this time, the gate 17b of the slave device 1b
Is closed, and the start command stored in the output buffer 15 of the slave device 1b is not output on the common bus 3. FIG. 5A shows an example of the format of the start command. When the start command is output, the destination ID (DID) of the start command, the transfer size (8-byte data / 16-byte data), The command type (type: read / write, etc.), access address (physical address), and the like are valid.

In this phase, the bus cycle signal generated by the bus cycle generation unit 13 is transmitted to the partner device forming the pair processor element (pair PE) by the transmission means, and the internally generated signal comparison determination unit 11 transmits the bus cycle signal. ,
When each of the master device 1a and the slave device 1b compares and determines each other and detects an abnormality (mismatch),
The synchronization operation is stopped or a higher-level device (not shown) is notified.

At this time, since the common bus 3 is used by the split method, the bus state (TG) is set to "SC &E" in this phase (b), and after one of the start commands is transmitted, Indicates that common bus 3 is to be released.

Next, in the phase shown in FIG. 2C, the slave device 1b stores the bus data (start command) output from the master device 1a onto the common bus 3 in the input buffer 14, and the slave device 1b The bus data comparison / determination unit 10 compares the comparison buffer 16 storing the bus data (start command) stored in the output buffer 15 with the contents of the input buffer 14 and detects an abnormality (mismatch). The synchronization operation is stopped or a higher-level device (not shown) is notified.

In the phase of FIG. 2D, it is determined that the bus ownership is acquired by the distributed arbitration, and the address of the start command (for example, DI of the start command)
D), the memory controller (M
C) 2 sets the bus request signal (BR).

The phase of FIG. 2E is a phase of a reply command whose format is shown in FIG. 5B, and the memory controller (MC) 2 selected by the address of the start command transmits the start command. When received, the identifier (ID) of the issuer of the start command is stored by looking at the bus request (BR) line of the common bus 3 and used as the destination ID (DID) of the reply command. At this time, in the data processing system of the present invention, the master device 1a that issues the start command and the slave device 1b that is the partner device have the same identifier (ID), and the destination ID (D
Master device 1a and slave device
1b Both are selected. At this time, the bus status (TG) is
As "MC &S", it is instructed to acquire a phase for transmitting data in the phase following the phase in which the reply command is transmitted.

In the phase shown in FIG. 2 (f), a device (replier) requested to perform a service such as read / write from another device via the common bus 3, in this example, the memory controller (MC) 2 Drive the read data. In this phase (f), the master device 1a and the slave device 1b
Sets the storage timing of the read data driven by the memory controller (MC) 2 in the input buffer 14. At this time, the bus state (TG) is set to "CE &E", and after transmitting data to the common bus 3, an instruction is given to release the bus.

Then, in the phase of FIG. 2 (g), the master device 1a and the slave device 1b store the read data, which was driven by the memory controller (MC) 2 as a reply, in the input buffer 14 at the storage timing. .

In this manner, a synchronous operation by read access is performed between the master device 1a and the slave device 1b. The comparison between the internally generated signal performed in the phase of FIG. 2 (b) and the comparison of the bus data (start command) of the common bus 3 performed in FIG. 2 (c) is performed when the data processing system is initialized. As a countermeasure against synchronization deviation due to differences in reset timing not shown in
For example, when the data processing system starts synchronous operation, the above comparison is performed in the operation cycle after the timing when the reply data of the reply command for the first start command is returned to both devices (master device 1a and slave device 1b). You may make it start.

In the above-described embodiment, since the synchronous operation is performed by using the split-type common bus 3 as described above, the phase (a) is used as shown in the time chart of FIG. ) To (c) and phases (d) to (g) can be used by other device modules such as another pair processor element (pair PE) and the common bus.
3 shows that the effective use of the common bus 3 is possible. However, the data processing system of the present invention is not limited to the use of the common bus 3 of the split system, but uses the common bus of the interlock system described above. It is needless to say that the present invention can be applied to the data processing system described above.

As described above, in the data processing system according to the present invention, for example, the master device 1 performs a duplex synchronous operation.
By combining means for checking duplicate comparison in the slave device 1b of the pair processor element (pair PE) composed of the slave processor 1a and the slave device 1b, multiple connections of the pair processor element (pair PE) can be facilitated. Further, only a pair processor element (pair PE) has a plurality of memory controllers (M
C) 2 only needs to recognize the difference from the identifier (ID) of the pair processor element (pair PE) connected to the common bus 3.

Next, FIG. 3 shows a configuration example of a multiprocessor system, and FIG. 4 shows a time chart when the operation in the multiprocessor system is read access to a memory.

First, the operation mode setting means in each processor element (PE) 1, for example, the mode register 1 shown in FIG.
2 or a multiprocessor mode is set to a mode setting pin (not shown) or other means. In the present embodiment, the mode register 12 will be described, but it is needless to say that the present invention is not limited to this.

Each device connected to the common bus 3, that is, the processor element (PE) 1 and the processor element (PE) that has determined to acquire the bus ownership by the bus request signal (BR) of the memory controller (MC) 2 PE) 1 is shown in Fig. 4 (a)
In this phase, a bus request (BR) is set and transmitted to all device modules connected on the common bus 3, such as each processor element (PE) 1.

The phase of FIG. 4B is a phase of a start command of the processor element (PE) 1, in which the start command stored in the output buffer 15 of the processor element (PE) 1 that has acquired the common bus 3 is transmitted. Gate 17b
Via the common bus 3. At this time, FIG.
The destination ID (DID), data size, start command type (type), address, etc. of the start command shown in (a) are valid. Also, in this phase,
In the case of the multiprocessor system, the operation of the internally generated signal comparison / judgment unit 11 is suppressed based on the multiprocessor mode data set in the mode register 12 and does not operate.

Also in the phase of FIG. 4C, in the case of the multiprocessor system, the operation of the bus data comparison judging unit 10 is similarly suppressed and does not operate. In the phase of FIG. 4 (d), the memory controller (MC) 2 selected by the address (for example, DID) of the start command is determined to have acquired the bus ownership by the distributed arbitration described above.
Set the bus request (BR) and set each processor element (PE) 1
And so on to all the device modules connected to the common bus 3.

The phase shown in FIG. 4E is a reply command phase. The format of the reply command is shown in FIG. Here, "reply" indicates the type of the reply command.

The address of the start command (for example,
When the memory controller (MC) 2 selected by (DID) receives the start command, the memory controller (MC) 2
Based on (BR), the identifier (ID) of the processor element (PE) 1 that issued the activation command is stored and used as a destination ID (DID) when issuing the reply command. At this time, in the case of a multiprocessor system, the identifier (I
In D), that is, in the destination ID (DID), one identifier (ID) is assigned to one processor element (PE) 1.

In the phase shown in FIG. 4F, the replyer, in this example, the memory controller (MC) 2 drives the read data. Further, in this phase (f), the processor element (PE) 1 which has transmitted the start command transmits the timing of storing the read data driven by the memory controller (MC) 2 in the input buffer 14.

4 (g), the processor element (PE) 1 stores the read data driven by the memory controller (MC) 2 in the input buffer 14.

Thus, each processor element
(PE) 1 uses its own acquired bus timing,
Access operations such as read and write can be executed independently. Note that the bus state (TG) in FIG. 4 indicates the same as in the case of FIG.

As described above, in the data processing system of the present invention, a predetermined operation mode, for example, a multiprocessor mode is set in the mode register 12 in each processor element (PE) 1 so that each processor element (P
E) 1 will be able to operate independently. That is, it is possible to easily operate as a different data processing system simply by changing the operation mode without changing the configuration of the data processing system. When the processor element (PE) 1 is added, only the processor element (PE) 1 has a plurality, and the memory controller (MC) 2 has the identifier of the processor element (PE) 1 connected to the common bus 3. It is only necessary to recognize the difference from (ID).

As described above, according to the data processing system of the present invention, in a data processing system in which a plurality of processor elements (PE) having the same configuration are connected to a common bus, for example, of the plurality of processor elements (PE), A system in which one or a plurality of pair processor elements (pairs PE) in which one is a master device and the other is a slave device, and the master device and the slave device are “paired”. When performing a synchronous operation between the master device and the slave device constituting the (pair PE), while the master device is outputting data to the common bus, the slave device suppresses the data output and outputs the data to the master device. A device for holding data output to the common bus by the device, and comparing the held data with data output by the slave device, It is characterized in that it is configured to determine the maintenance of the synchronous operation by determining the coincidence by the comparing means, and it is also possible to operate as a multiprocessor system only by changing the operation mode.

[0046]

As described above, according to the data processing system of the present invention, for example, the slave device 1
b, the comparison operation of the bus data can be summarized, and the effect on the output bus of the processor element (PE) 1 can be increased without increasing the number of comparators due to the increase of the pair processor element (pair PE). , The operating frequency is limited by the increase of the output bus length), and the synchronous operation in each pair processor element (pair PE) can be performed.

The operation mode setting means (mode register, mode setting pin) 12 provided in each processor element (PE) 1 is simply set to a predetermined operation mode (multiprocessor mode). Element (PE) 1 can be operated independently.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention.

FIG. 2 is a diagram showing an example of an operation time chart of a redundant system.

FIG. 3 is a diagram illustrating a configuration example of a multiprocessor system;

FIG. 4 is a diagram showing an example of an operation time chart of a multiprocessor system.

FIG. 5 is a diagram showing a format example of a start command and a reply command.

FIG. 6 is a diagram illustrating a conventional data processing system.

[Explanation of symbols]

1 Processor element (PE) 1a Master device, 1st processor element 1b Slave device, 2nd processor element 2 Memory controller (MC) 3 Common bus 4 Comparator 10 Comparison means, bus data comparison / judgment unit 11 Judgment means, internal Generated signal comparison / determination section 12 Operation mode setting means, mode register 13 Bus cycle generation section 14 Input buffer 15 Output buffer 16 Comparison buffer 17a, 17b Gate Bus cycle signal Bus control signal transmission means Start command Reply command

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Atsushi Funaki 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Satoshi Shinohara 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture No. 1 Inside Fujitsu Limited

Claims (4)

[Claims] In a data processing system, a plurality of processor elements having the same configuration and a response device for outputting response data to a start command from each processor element are connected to a common bus. Is a first processor element, the other is a second processor element, and there is a pair processor element in which the first processor element and the second processor element are paired. When performing the synchronous operation between the first processor element and the second processor element of the paired processor element, the second processor element outputs the data while the first processor element is outputting data to the common bus. And the first processor element is shared. A comparing unit that holds the data output to the communication bus and compares the held data with the data output by the second processor element; A data processing system for determining whether to maintain synchronous operation with a second processor element. 2. A data processing system in which a plurality of processor elements having the same configuration and a response device for outputting response data to a start command from each processor element are connected to a common bus. Is a first processor element, the other is a second processor element, and there is a pair processor element in which the first processor element and the second processor element are paired. Transmitting means for transmitting a signal generated inside the first processor element and the second processor element through a dedicated signal line between the processor elements forming a “pair”; and the first processor element. And in each of the second processor elements, Determining means for determining whether or not the signal matches its own signal; and determining the match by the determining means, whereby the synchronous operation between the first processor element and the second processor element is performed. A data processing system for determining whether to maintain the data. 3. The data processing system according to claim 1, wherein said comparison means determines whether or not said data is received by said comparison means in an operation cycle after receiving a response from a response device connected to said common bus. A data processing system, which starts the determination of (i) or performs determination of a match by the determination means. 4. The data processing system according to claim 1, wherein an operation mode setting means is provided in a processor element connected to said common bus, and A data processing system characterized in that each of the processor elements performs data processing independently by setting the operation mode of (1).