JP5900360B2 - Duplex programmable controller and synchronization method thereof - Google Patents

Description

  The present invention relates to a duplex programmable controller that performs system switching when an abnormality occurs in a CPU unit in a monitoring control system or the like.

  The dual programmable controller has two CPU units (Central Processing Units) that can operate in parallel with each other, and is used for processes such as process control that require a high degree of reliability that causes serious damage due to system down. Widely used.

  In the dual programmable controller, when the first CPU unit is set to the control system and the second CPU unit is set to the standby system among the two CPU units, an abnormality occurs in the first CPU unit of the control system. The second CPU unit of the standby system is automatically switched to the control system to prevent the system from going down, and has a function of automatically continuing the system.

  In the duplex programmable controller, it is necessary to perform synchronization to ensure that the first CPU unit and the second CPU unit execute the same program with the same contents. If there is an interrupt instruction that executes an interrupt event from the outside during program execution, the control system and standby system must be executed in order to execute the same program that reflects the interrupt event result in the control system and standby system. It is necessary to confirm that there is no deviation in the timing of accessing the outside. In other words, the interrupt counter is executed when the program counter of the program being executed is different, and the program counter that is the timing to execute the interrupt event is checked in order to prevent different program results from being obtained in the control system and standby system. However, it is necessary to execute an interrupt instruction from the outside in accordance with the same program counter in the control system and the standby system.

  Therefore, in the conventional dual programmable controller, when there is an interrupt instruction from the outside, the first CPU unit and the second CPU unit are checked whether the interrupt instruction is generated by the same program counter and are not the same. In some cases, the same program counter is used, and then an interrupt event corresponding to the interrupt instruction is executed from the outside (see, for example, Patent Document 1).

  In other words, every time an external interrupt instruction is generated, the program being executed is interrupted, and after confirming that the same interrupt event is executed at the same timing in the first CPU unit and the second CPU unit, the interrupt event After executing, restart the program. By doing so, in the conventional duplex programmable controller, the first CPU unit and the second CPU unit are synchronized to ensure that the program is executed with the same contents.

JP-T-2006-512634

  In the conventional duplex programmable controller, each time an external interrupt command is generated, both the first CPU unit and the second CPU unit interrupt the program and perform synchronization. That is, the time during which both the first CPU unit and the second CPU unit interrupt the program while confirming that the same interrupt event is executed by the same program counter in the first CPU unit and the second CPU unit. Will occur. Although the processing time of the program can be greatly shortened as the capacity of the controller is increased by improving the CPU processing capacity, it is necessary for the synchronization processing from the first CPU unit to the second CPU unit via the network. Time to communicate synchronization information is increasing. For this reason, there is a problem that the time for both the first CPU unit and the second CPU unit to interrupt the program increases and the program execution time becomes long.

  The present invention has been made in order to solve the above-described problems, and a duplicated program controller and a synchronization method thereof that suppress an increase in program execution time due to an increase in time for communicating synchronization information. The purpose is to provide.

When the duplex programmable controller according to the present invention executes the first program counter, the first CPU, and the control program corresponding to the event, the contents of the event are changed to the value of the first program counter and the first branch counter. A first transmission / reception buffer that is stored as synchronization information in association with the value of the first CPU unit, a second program counter, a second CPU, and a transmission from the first transmission / reception buffer. A second transmission / reception buffer for storing the synchronized information, and a comparison unit that always compares the value of the second program counter with the synchronization information stored in the second transmission / reception buffer. And a communication path for transmitting synchronization information from the first transmission / reception buffer to the second transmission / reception buffer. Event, at least one of the execution of the synchronized instruction and interrupt command by the first CPU, or a is accepted interrupt, further second CPU unit, if the comparison result of the ratio較部match, match A control program corresponding to the synchronization information associated with the values of the first program counter and the first branch number counter is executed.

  According to this invention, the contents executed by the first CPU unit of the control system are transmitted as synchronization information from the first transmission / reception buffer to the second transmission / reception buffer provided in the second CPU unit of the standby system, Since the second CPU unit executes the synchronization program based on the synchronization information, the second CPU unit can follow the program having the same contents as the first CPU unit and can perform synchronization. In other words, the second CPU unit is the content executed by the first CPU unit and can execute a synchronization program based on the synchronization information reflecting the external interrupt instruction. Therefore, the second CPU unit is synchronized every time an external interrupt instruction is generated. Therefore, there is an effect that the program execution time can be shortened without requiring communication time for making the program.

It is a block diagram which shows the structure of the duplex programmable controller which concerns on Embodiment 1 of this invention. 4 is a time chart showing an operation when a program is executed in the duplex programmable controller according to the first embodiment of the present invention. In the duplex programmable controller according to the first embodiment of the present invention, an example when the synchronization information is stored in the first transmission / reception buffer when the first CPU unit of the control system executes the instruction to be synchronized is described. FIG. In the duplex programmable controller according to the first embodiment of the present invention, an example when the synchronization information is stored in the first transmission / reception buffer when the first CPU unit of the control system executes the external interrupt instruction is described. FIG. In the duplex programmable controller according to the first embodiment of the present invention, an example when the synchronization information is stored in the first transmission / reception buffer when the first CPU unit of the control system executes the synchronization timer interrupt will be described. FIG. In the duplex programmable controller which concerns on Embodiment 1 of this invention, the block diagram for demonstrating the standby-system process which 2nd CPU unit of a standby system performs based on synchronization information is shown. 5 is a time chart for explaining a system switching method due to a failure of a control system CPU unit in the duplex programmable controller according to the first embodiment of the present invention. In the duplex programmable controller which concerns on Embodiment 2 of this invention, it is a time chart explaining the system switching method by a system switching command.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a duplex programmable controller according to Embodiment 1 of the present invention. The duplex programmable controller of the present embodiment includes a first controller 10a that is a control system and a standby system for executing a program 50 (not shown in FIG. 1 and shown in FIG. 2) that is the same control program. A second controller 10b. That is, FIG. 1 of the present embodiment shows a state in which the first controller 10a functions as a control system and the second controller 10b functions as a standby system. The first controller 10a includes a first CPU unit 11a and a first communication unit 12a, and the second controller 10b includes a second CPU unit 11b and a second communication unit 12b.

  As shown in FIG. 1, in the duplex programmable controller of the present embodiment, the first transmission / reception buffer 13a is provided in the first CPU unit 11a of the control system, and the second transmission / reception buffer 13b is provided in the second CPU unit 11b. Are provided as dedicated areas. These dedicated areas are composed of a RAM (Randam Access Memory) provided for synchronous transfer performed between the control system and the standby system.

  The first CPU unit 11a includes a first CPU (not shown), a first program counter (PC) 16a, a first comparison unit 17a, and a first branch counter 15a. With. The first comparison unit 17a includes later-described synchronization information, which is data stored in the first transmission / reception buffer 13a, and the value of the first program counter 16a corresponding to the data (and, if necessary, the first program counter 16a). A function of comparing the value of the branch number counter 15a).

  Further, the second CPU unit 11b includes a second CPU (not shown), a second program counter (PC) 16b, a second comparison unit 17b, and a second branch number counter 15b. With. The second comparison unit 17b compares the data stored in the second transmission / reception buffer 13b with the value of the second program counter 16b (and, if necessary, the value of the second branch number counter 15b). Is provided.

  The first CPU unit 11a and the second CPU unit 11b are connected via a communication path by the first connector 14a and the second connector 14b. In other words, the duplex programmable controller of the present embodiment has a configuration capable of transferring data for synchronization between the first controller 10a and the second controller 10b through a communication path. In FIG. 1 of the present embodiment, the tracking cable 20 is used as a communication path. However, two CPU units of a control system and a standby system are connected on the same bus, and data transfer for synchronization is performed via the bus. It may be configured.

  The first communication unit 12a of the first controller 10a and the second communication unit 12b of the second controller 10b are connected to the communication network 21. For example, in FIG. 1, an interrupt command such as interrupt event execution issued from the external CPU unit 31 of the external controller 30 is issued from the communication network 21 to the duplex programmable controller via the external communication unit 32.

  FIG. 2 is a time chart showing an operation when the program 50 is executed in the duplex programmable controller of the present embodiment. In FIG. 2, time progresses from top to bottom. In the following, the program 50 of the control system process 40 is divided in order from the front, the process A of the program 50 is step S100, the process B of the program 50 is step S102, and the process C of the program 50 is step S105. I'm calling. Further, the synchronization information transmission command in steps S101 and S104 corresponds to an interrupt processing program of the control system process 40. Such a way of calling is the same in the standby system 41. Step S120, step S121, and step S124 correspond to the interrupt processing program of the standby system processing 41.

  Further, a communication system process 42 is performed between the first transmission / reception buffer 13a and the second transmission / reception buffer 13b via a communication path. In this communication processing 42, steps S110 and S112 mean information transfer processing from the control system to the standby system, and steps S111 and S113 mean information transfer from the standby system to the control system. The information transferred here includes synchronization information and a response signal.

  Referring to FIG. 2 in more detail, steps S100 to S106 show operations performed by the first controller 10a as the control system process 40. Steps S120 to S125 show operations performed by the second controller 10b as the standby processing 41. Further, a process in which the tracking cable 20 transfers data between the first CPU unit 11a of the first controller 10a and the second CPU unit 11b of the second controller 10b is set as a communication system process 42 in step S110. To step 113.

  3, 4, and 5 show data (synchronization information) that is necessary when the first CPU unit 11 b of the control system executes a synchronization instruction that needs to be synchronized in the duplex programmable controller of the present embodiment. ) Is stored in the transmission / reception buffer 13a.

  The operation flow of the duplex programmable controller in the present embodiment will be described with reference to FIGS.

In step S100 in FIG. 2, the first CPU unit 11a of the control system executes the program 50. In step S100, if the content of the program 50 includes an access command (synchronization target command 51 in FIG. 3) for accessing the external device to read data to the external controller 30, the first CPU unit 11a determines that the external controller 30 To read data R ₁ via the communication network 21. Thereafter, as shown in FIG. 3, the first transmission and reception buffer 13a, as synchronization information and program counter value X ₁ and executing the synchronization target instruction 51 and the data amount D ₁ of the read data R ₁ and read data R ₁ Store.

Further, in step S100 of FIG. 2, when the interrupt command 52 is received from the external controller 30 as shown in FIG. 4, the first CPU unit 11a of the control system receives the interrupt command 52 from the outside and receives an interrupt event ( a program counter value _{X 2} when executing the interrupt processing _{Z 1),} and a branch count _{Y 2,} read from the first program counter 16a and the first branch counter 15a, the first transmission and reception buffer 13a Store. The contents of the interrupt processing Z ₂ is also stored into the first reception buffer 13a as shown in FIG. In other words, from the external controller 30 when an interrupt instruction 52 is generated, the value of the first program counter 16a, the value of the first branch counter 15a, as synchronization information and contents of the interrupt processing Z ₂ first Store in the transmission / reception buffer 13a.

  After executing the interrupt event from the external controller 30, the interrupted program is resumed by reflecting the result of executing the interrupt instruction 52.

In step S100, when the synchronous interrupt timer set time 43 has elapsed and there is a synchronous timer interrupt 53, the first CPU unit unit 11a of the control system interrupts the program 50 by the synchronous timer interrupt 53 and is shown in FIG. first transceiver buffer and the contents of the program counter branch number 16a is the value of the program counter value X ₃ is a value branch counter 15a Y ₃ and synchronous interrupt process Z ₃ by a timer interrupt 53 as synchronization information as Store in 13a.

  Next, in step S101 of FIG. 2, by executing a synchronization information transmission command, the first CPU unit 11a transmits data stored in the first transmission / reception buffer 13a to the tracking cable 20 as synchronization information. Execute the send command. After execution of the synchronization information transmission command, execution of the program 50 is resumed without waiting for reception of a response from the second CPU unit 11b (step S103), and the process proceeds to step S102.

  In step S102, the first CPU unit 11a continues to execute the program 50 as in step S100.

  In step S103, the first CPU unit 11a receives the synchronization response signal transmitted from the standby second CPU unit 11b. Here, the reception of the response signal performed in step S103 specifically means that the synchronization response signal transmitted from the second CPU unit 11b is stored in the first transmission / reception buffer 13a. Since the communication system processing 42 of the tracking cable 20 that is the communication path mainly transfers the response signal, the response signal is stored in the first transmission / reception buffer 13a even when the first CPU unit 11a is executing the program 50. can do. That is, the synchronization response signal in step S103 can be received in parallel with step S102.

  When the synchronous interrupt timer set time 43 elapses in step S102, the first CPU unit 11a in the control system interrupts the program 50 by the synchronous timer interrupt 53, and in step S104, the second CPU unit 11b in the standby system in step S103. Recognize synchronization response signal from. Therefore, it is confirmed that the process of the second CPU unit 11b in the standby system follows the process of the first CPU unit 11a, and a transmission command for transmitting the synchronization information is executed in the same manner as in step S101.

  If the synchronization response signal is not received in step S103, the first CPU unit 11a waits for the synchronization response reception with the program 50 stopped. That is, if step S103 does not occur until the synchronization timer interrupt 53 is generated in step S102 and the process proceeds to step S104, the first CPU unit 11a does not proceed to step S104 but waits until step S103 occurs.

  However, if the synchronous interrupt timer setting time 43 is set to a time longer than the sum of the time required for step S110 described later and the time required for step S111, step S103 is performed in parallel with step S102. There is no time to wait.

  As described above, the first CPU unit 11a continues the step of the control system process 40.

  Next, standby processing 41 performed by the standby second CPU unit 11b and communication processing 42 that performs data transfer between the first CPU unit 11a and the second CPU unit 11b will be described. The second CPU unit 11b in the standby system executes the synchronization program based on the synchronization information transmitted from the first CPU unit 11a.

  The synchronization information transmitted by the first CPU unit 11a executing the transmission command in step S101 of FIG. 2 is transferred from the first transmission / reception buffer 13a to the second transmission / reception buffer 13b via the tracking cable 20. . Step S110, which is the transfer process, is performed mainly by the communication system using the tracking cable 20.

  In step S120, the second CPU unit 11b in the standby system receives the synchronization information from the first CPU unit 11a in the control system. Here, the reception of the synchronization information in step S120 means that the data stored in the first transmission / reception buffer 13a is transferred via the trekking cable 20 and the storage in the second transmission / reception buffer 13b is completed. .

  The time required for the communication processing 42 performed mainly by the communication system becomes longer as the capacity of the controller is increased due to the improved CPU unit processing capability. In the present embodiment, the first CPU unit 11a can process the program 50 in parallel with the communication processing 42, so that the communication processing is performed during the program execution time from the start of the program 50 to the end. The communication time for S110 and step S112 is not added. Therefore, the program execution time can be shortened.

  Next, in step S121, the second CPU unit 11b executes a transmission command for transmitting a response signal for synchronization. Here, the response signal may be any content that confirms the synchronization information. For example, the reception of the synchronization information is completed, and the second CPU unit 11B interrupts the second program 50. The value of the program counter may be used.

  When a response transmission command is issued in step S121, a response signal is transferred from the second transmission / reception buffer 13b to the first transmission / reception buffer 13a via the tracking cable 20 in step S111 in the communication processing 42. Step S111, which is the transfer process, is performed mainly by the communication system using the tracking cable 20.

  Next, the second CPU unit 11b proceeds to step S122 and executes the program 50. Here, the program 50 executed by the first CPU unit 11a and the program 50 executed by the second CPU unit 11b are the same.

In step S122, the standby second CPU unit 11b executes the program 50, and reads data from the external controller 30 to the contents of the program 50, which is the same as the synchronization target instruction 51 of the first CPU unit 11a of FIG. If there is an external device command to be executed, the second CPU unit 11b itself recognizes that it is a standby system, and unlike the first CPU unit 11a of the control system, it does not access the external controller 30, and the second The read data R ₁ stored in the transmission / reception buffer 13b is read, and the read data R ₁ acquired when the first CPU unit 11a of the control system executes the synchronization target instruction 51 in step S100 is acquired.

In the first CPU unit 11a and the second CPU units 11b, different progress of the program 50, there may be a delay when executing a program counter value _{X 1} of the leading data of the external controller 30 differs. If the data of the external controller 30 varies with time, different data may be read if the time for accessing the external controller 30 is different.

In this embodiment, the read data _{R 1} in which the first CPU unit 11a is read in the program counter value _{X 1} transfers as the synchronization information to the second transmission and reception buffer 13b of the second CPU unit 11b, the second when the CPU unit 11b executes a program counter value _{X 1,} since reads the read data _{R 1} of the second transmission and reception buffer 13b, a first CPU unit 11a and the second CPU units 11b both the same lead of the external controller 30 Data R ₁ can be reflected in the program 50.

  In step S122, the standby second CPU unit 11b determines that the standby CPU unit 11b is the second CPU unit 11b even if the synchronization target instruction 51 is an external write instruction to the external controller 30. It recognizes that it is a standby system and does not access the external controller 30 unlike the first CPU unit 11a of the control system. This is because the control system has already executed the synchronization target instruction 51 which is an external write instruction in step S100.

Further, in step S122, during execution of the program 50, the interrupt instruction 52 from the outside is transferred to the first CPU unit 11a in FIG. 5 and transferred from the first transmission / reception buffer 13a and stored in the second transmission / reception buffer 13b. There a program counter value X ₂ when generated and number of branches Y ₂ is, whether to match each value of the second CPU unit 11b built in the second program counter 16b and the value of the second branch counter 15b The second comparison unit 17b always compares.

FIG. 6 shows a block diagram for explaining the standby processing 41 performed by the second CPU unit 11b in step S122 based on the synchronization information. The second CPU unit 11b executes the program 50, if there is synchronization target instruction 51 is an external read command to the content of the program 50 in the program counter value _{X 1,} the second CPU unit 11b itself, as described above It recognizes that it is a standby system, without accessing the external controller 30 reads the read data R ₁ of the program counter value X ₁ stored in the second reception buffer 13b. That is, the first CPU unit 11a is read by the program counter value X _1, reads out the read data R ₁ which has been transmitted as synchronization information.

Thereafter, the second CPU unit 11b continues the program 50, but in the value of the second program counter 16b and the value of the second branch number counter 15b and the synchronization information stored in the second transmission / reception buffer 13b. It is constantly compared in comparison unit and a program counter value X _n and the branch count Y _n.

For example, in Figure 6, by the second comparison unit 17b, that the value of the second program counter 16b matches the program counter value X _2, the value of the second branch counter 15b coincides with the number of branches Y ₂ check, second CPU unit 11b interrupts the program 50 executes the interrupt processing _{Z 2.} The interrupt instruction 52 shown in FIG. 6 is the same as the content of the interrupt event performed when the first CPU unit 11a generates the interrupt instruction 52 in FIG. That is, the first CPU unit 11a is an interrupt process _{Z 2} went when an interrupt instruction 52 is generated, with the first CPU unit 11a same program counter value _{X 2} and number of branches was performed _{Y 2,} the second The CPU unit 11b follows.

  In the present embodiment, when an interrupt instruction is generated from the outside, the value of the program counter for executing the interrupt event by the first CPU unit 11a, the number of branches, and the interrupt processing contents are synchronized with the second CPU unit 11b. The information is transmitted as information, and the second CPU unit 11b executes an interrupt event corresponding to the interrupt instruction from the program 50 and the outside based on the synchronization information. Therefore, when an interrupt instruction is generated from the outside, it is confirmed that the first CPU unit 11a and the second CPU unit 11b have advanced to the same program counter value, and each accesses the outside individually to externally There is no need to execute the interrupt instruction.

  Accordingly, each time an external interrupt instruction is generated, one of the programs is interrupted until the first CPU unit 11a and the second CPU unit 11b proceed to the same program counter value, and the other proceeds to the same program counter value. Since no communication time is required to confirm that the values are the same, the program interruption time can be shortened and the program execution time can be shortened.

Next, in FIG. 6, the value and the second branch counter and the program counter value X ₃ and branch number Y ₃ which alignment timer interrupt 53 occurs in the first CPU unit 11a in FIG. 5 the second program counter 16b When the second comparison unit 17 confirms that the values of 15b match, a synchronization timer interrupt 53 is executed on the second CPU unit 11b. That is, in FIG. 2, the second CPU unit 11b proceeds to step S124.

  In the above steps, the second CPU unit 11b executes the same control program contents as those executed by the first CPU unit 11a in step S100 in step S122. That is, the second CPU unit 11b executes the synchronization program based on the synchronization information transmitted from the first CPU unit 11a.

  In FIG. 6, the synchronization programs executed by the second CPU unit 11 b are a program 50, a synchronization target instruction 51, an interrupt instruction 52, and a synchronization timer interrupt 53. That is, when the second CPU unit 11b executes the synchronization program, the same result as that obtained when the first CPU unit 11a executes the control program can be obtained. Therefore, the first CPU unit 11a of the control system immediately after step S100 and the second CPU unit 11b of the standby system immediately after step S122 are in the same state. In the present embodiment, the first CPU unit 11a and the second CPU unit 11b are synchronized in this way.

  As shown in FIG. 6, the second comparison unit 17 includes the value of the program counter and the number of branches of the synchronization information stored in the second transmission / reception buffer 13 b, the value of the second program counter 16 b and the number of second branches. The value is compared with the value of the counter 15b, and each time they match, the second CPU unit 11b interrupts the program, executes the interrupt processing stored in the second transmission / reception buffer 13b, and executes the program after the end of the interrupt processing. Restart 50.

  The processing content executed by the first CPU unit 11a in step 102 is that the synchronization information transmission command is executed in step S104, and the communication system processing 42 transfers the synchronization information via the tracking cable 20 in step S112. Executed. In FIG. 2, step S123 indicates when the synchronization information is completely stored in the second transmission / reception buffer.

  If step S123 is completed at the end of step S122, the second CPU unit 11b proceeds to step S124. If step S123 is not completed at the end of step S122, the second CPU unit 11b waits until step S123 is completed.

  When the second CPU unit 11b proceeds to step S124, it transmits a response signal for synchronization processing informing that the synchronization information has been received, as in step S121.

  Then, it progresses to step S125 and continues execution of a synchronization program based on the synchronization information which transmitted the content which the 1st CPU unit 11a performed by step S102 similarly to step S122.

  As described above, the second CPU unit 11b in the standby system continues the standby system process 41, and follows the control system process 40 to execute the synchronization program.

  The first CPU unit 11a of the control system reflects the calculation result of the executed program 50 in the control of the monitoring system after the program 50 ends (sends to the external device via the communication unit 12a and the communication network 21). The end of the program 50 is transmitted to the second CPU unit 11b of the standby system. Thereafter, the standby second CPU unit 11b also terminates the synchronization program, but the second CPU unit 11b does not transmit the execution result of the synchronization program.

  The first CPU unit 11a of the control system receives the input data from the external device via the communication unit 12a and the communication network 21 after finishing the program 50, and inputs the input data to the second CPU unit 11b of the standby system. Transmits and executes predetermined processing such as updating its own memory.

  The second CPU unit 11b in the standby system receives input data from the first CPU unit 11a in the control system, and executes a predetermined process such as updating its own memory. As a result, even when a separate program is executed in the next cycle, the second CPU unit 11b in the standby system can start the program while maintaining the same state as the first CPU unit 11a in the control system. Become.

  Next, a system switching method when the first CPU unit 11a of the control system of the duplex programmable controller according to the first embodiment of the present invention fails will be described.

  FIG. 7 is a time chart for explaining a system switching method due to a failure in the duplex programmable controller according to the first embodiment. In FIG. 7, the duplex programmable controller performs the same sequence as in FIG. 2 until a failure of the control system occurs. Steps S100, S101, S102, and S107 correspond to the operation of the control system, and steps S130 to S135 correspond to the operation of the standby system.

  Assume that the first CPU unit 11a of the control system fails during execution of the program 50 in step S102. When detecting the failure of its own hardware, the first CPU unit 11a stops the program 50 being executed in step S107. The first CPU unit 11a of the control system transmits a failure notification indicating that the control system has failed to the standby system via the tracking cable 20, and at the same time notifies a system switching command for switching the standby system to the control system.

  In steps S130, S131, and S132, the standby second CPU unit 11b performs the same processing as steps S120, 121, and S122 of FIG. In step S132, in parallel with the execution of the synchronization program, a failure notification is received from the first CPU unit 11a of the control system in step S133.

  After executing the synchronization program having the same contents as step S100 executed by the first CPU unit 11a in step S132, the standby second CPU unit 11b has received a failure notification from step S133 in step S134. As a condition, a process of switching from the standby system to the control system is executed, and the process proceeds to step S135.

  In step S135, the second CPU unit 11b, which is a standby system, executes the program 50 as a control system. At this time, the duplex programmable controller is in a mode in which only the second CPU unit 11b operates as the control system, and does not execute the program in both the control system and the standby system, but only in the control system (old standby system). Can continue to run. Since the second CPU unit 11b has the same configuration as the first CPU unit 11a, the program 50 can be executed as a control system.

  With the above operation, when the first CPU unit 11a that was the control system fails, the second CPU unit 11b that was the standby system switches to the control system and performs operations such as actual control. The system can be operated continuously without stopping, improving reliability.

  According to the present embodiment, the first CPU unit 11a of the control system interrupts the control program at every set time of the synchronous interrupt timer, and the second CPU unit 11b such as the interrupt event content follows and executes it. Necessary information is transmitted as synchronization information to the second CPU unit 11b, and a response signal from the second CPU unit 11b is received after the control program is restarted. That is, every time an external interrupt instruction is generated, it is necessary to interrupt the program being executed in order to confirm that the same result of the interrupt event is obtained in the first CPU unit 11a and the second CPU unit 11b. Thus, the time required for synchronization can be shortened, and the program execution time can be shortened.

  In the present embodiment, the first CPU unit 11a resumes the program 50 while the communication processing 41 is transferring data via a communication path such as the tracking cable 20. That is, since the first CPU unit 11a resumes the program 50 in parallel with the data transfer, it is not necessary to wait for the communication time for data transfer, and the program execution time can be shortened.

  Although the processing time of the program can be greatly shortened as the capacity of the controller is increased due to the improved processing capacity of the CPU unit, the time required for communication for synchronization when an external interrupt command is generated increases. There was a problem that the program execution time accounted for a large proportion of the program execution time from the start to the end and the program execution time became long. However, by using this embodiment, the program execution time can be shortened as described above. Become.

  In particular, there is a problem that the data transfer communication time is longer than the program processing time. In the conventional method, since data such as whether or not the control system and the standby system are the same program counter are exchanged and checked, the program needs to be stopped during the data transfer. However, if this embodiment is used, the program can be executed even during the data transfer, so that the program execution time can be greatly reduced.

  In the present embodiment, the second CPU unit 11b executes the synchronization program based on the synchronization information transmitted from the first CPU unit 11a, so that the second CPU unit 11b and the first CPU unit 11b Synchronization, which is a guarantee that the CPU unit 11a performs the same program, is performed. Therefore, each of the first CPU unit 11a and the second CPU unit 11b does not access the outside, and each of the first CPU unit 11a and the second CPU unit 11b accesses the outside. The operation of checking whether the access results are the same can also be omitted.

  As described above, by using this embodiment, the time required for synchronization can be omitted, and the effect of shortening the program execution time can be obtained.

Embodiment 2. FIG.
FIG. 8 shows a time chart for explaining a system switching method by executing a system switching instruction in the duplex programmable controller according to the second embodiment of the present invention. In the present embodiment, even if a failure does not occur in the first CPU unit 11a in the control system, the second CPU unit 11b in the standby system can be switched to the control system by executing the system switching command. Features. The rest is the same as in the first embodiment. According to the present embodiment, when the life of the first CPU unit 11a is approaching, the system can be freely switched by executing the switching command even if no failure occurs.

  In FIG. 8, the duplex programmable controller performs the same sequence as in FIG. 2 until a system switching command for the control system is generated. Steps S140 to S144 correspond to the operation of the first CPU unit 11a as the control system process 40, and steps S150 to S155 correspond to the operation of the standby system. The rest is the same as in the first embodiment.

  In step S140 of FIG. 8, when a system switching command is generated in the first CPU unit 11a of the control system, the first CPU unit 11a stops the program 50 being executed, and the execution contents of the program 50 before the stop are determined. The fact that certain data and a system switching command are generated is stored in the first transmission / reception buffer 13a. Further, the first CPU unit 11a executes a transmission command for transmitting the synchronization information and the system switching command stored in the first transmission / reception buffer 13a. The first CPU unit 11a switches itself to a standby system.

  In accordance with the transmission command in step S140, the communication processing 42 transfers the synchronization information and the system switching command to the second transmission / reception buffer 13b via the tracking cable 20.

  In step S150, the second CPU unit 11b that has been the standby system receives the system switching information simultaneously with the synchronization information.

  In step S151, the second CPU unit 11b notifies the first CPU unit 11a that has become the new standby system that the system switching information and the synchronization information have been received, and the process proceeds to step S152.

  In step S152, the second CPU unit 11b operates as a standby system in the same manner as in S120, executes the synchronization program until execution of the same content as the program executed by the first CPU unit 11a, and then proceeds to step S153. To do.

  In step S153, the second CPU unit 11b, which was the standby system, switches the system to the control system, and proceeds to step S154. At this time, in the duplex programmable controller, the system switching between the two systems is completed, the second CPU unit 11b becomes a new control system, and the first CPU unit 11a becomes a new standby system to resume program execution.

  With the above operation, after the system switching instruction is executed, the control system and the standby system can continuously execute the program 50. If the system switching instruction is executed, no failure occurs in any of the CPU units. Can also switch between the control system and standby system.

  This embodiment can also be used for debugging and the like, and can measure the time required for system switching.

  In the second embodiment of the present invention, portions different from the first embodiment of the present invention are described, and descriptions of the same or corresponding portions are omitted.

  10a 1st controller, 10b 2nd controller, 11a 1st CPU unit, 11b 2nd CPU unit, 12a 1st communication unit, 12b 2nd communication unit, 13a 1st transmission / reception buffer, 13b 2nd Transmission / reception buffer, 14a first connector, 14b second connector, 15a first branch number counter, 15b second branch number counter, 16a first program counter, 16b second program counter, 17a first Comparison unit, 17b Second comparison unit, 20 Tracking cable, 21 Communication network, 30 External controller, 31 External CPU unit, 32 External communication unit, 40 Control system process, 41 Standby system process, 42 Communication system process, 43 Synchronous interrupt Timer setting time, 50 programs , 51 Synchronization target instruction, 52 Interrupt instruction, 53 Synchronization timer interrupt.

Claims (10)

A first program counter, a first CPU, when executing the control program corresponding to the event, and the previous contents of SL events associated with the value and the value of the first branch counter of the first program counter A first CPU unit provided with a first transmission / reception buffer for storing synchronization information;
A second program counter; a second CPU; a second transmission / reception buffer for storing the synchronization information transmitted from the first transmission / reception buffer; a value of the second program counter; A second CPU unit provided with a comparison unit that constantly compares the synchronization information stored in the transmission / reception buffer;
A communication channel and for transmitting the synchronization information to the second reception buffer from said first transmission and reception buffer,
The event is execution of at least one of a synchronization target instruction and an interrupt instruction by the first CPU, or acceptance of an interrupt,
The second CPU units, the comparison result by the previous SL ratio較部is if they match, corresponding to the matched first program counter and the first branch counter the synchronization information associated with the value of redundant programmable controller characterized that you run the control program. The first CPU unit, child stored in the first reception buffer and the value of the first program counter to execute the interrupt processing and the contents of the interrupt processing for the interrupt command from the outside as synchronization information redundant programmable controller according to claim 1, wherein the door. When the second CPU unit stores the synchronization information in the second transmission / reception buffer, the second CPU unit transmits a response signal to the first CPU unit via the communication path, and the first CPU unit redundant programmable controller according to claim 1 or 2, characterized that you store the response signal to said first transmission and reception buffer. The first CPU unit is a control system, the second CPU unit is a standby system, and the second CPU unit is notified when a failure notification is given from the first CPU unit to the second CPU unit. redundant programmable controller according to any one of claims 1 to 3 but wherein the Rukoto switch to the control system. When the first CPU unit is a control system, the second CPU unit is a standby system, the first CPU unit issues a switching notification, and the second CPU unit receives the switching notification, redundant programmable controller according to any one of claims 1 to 4 wherein the second CPU unit is characterized Rukoto switch to the control system. It said communication path, redundant programmable controller according to any one of claims 1 to 5, wherein the tracking cables der Rukoto. Said communication path, redundant programmable controller according to any one of claims 1 to 5, characterized in Oh Rukoto bus. A step in which the first CPU unit interrupts the program being executed at every synchronous interrupt timer set time;
After the program is interrupted, the first CPU unit associates the execution contents within the set time of the synchronous interrupt timer with the value of the first program counter and the value of the first branch number counter as synchronization information on the communication path. Executing a first transmission instruction to transmit;
The first CPU unit restarting the program after the step of executing the first transmission command;
A second CPU unit receiving the synchronization information transmitted to the communication path;
Executing a second transmission command for transmitting a response signal to the communication path in response to the second CPU unit receiving the synchronization information ;
Receiving the response signal after the first CPU unit resumes the program; and
When the second CPU unit always compares the transmitted synchronization information with the second program counter and the second branch number counter of the second CPU unit, and the compared result of comparison is coincident Executing the program according to the synchronization information associated with the matched first program counter value and the first branch number counter value;
Method for synchronizing a dual programmable controller with The first CPU unit is a control system and the second CPU unit is a standby system.
When there is a failure notification from the first CPU unit to the second CPU unit,
The method for synchronizing a duplex programmable controller according to claim 8, further comprising a step of switching the two CPU units to a control system. When the first CPU unit is a control system, the second CPU unit is a standby system, the first CPU unit issues a switching notification, and the second CPU unit receives the switching notification, The synchronization method of the duplex programmable controller according to claim 8, further comprising a step of switching the second CPU unit to a control system .

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