JPS62214465A - Control method for dual controller - Google Patents

Abstract

PURPOSE:To allow stored contents of both controllers to coincide with each other by performing the control operation at a preliminarily determined operation period each time when process data transmitted from the current controller at every control period is received by the stand-by controller. CONSTITUTION:Process data is inputted to a current controller A having the control right out of two controllers A and B from a process input/output device (PI/O) 11 at every preliminarily determined control period through a PI/O bus 10, a switching circuit 8A, and a process input/output interface (PI/OIF) 7A, and the control operation is performed. Inputted process data is transmitted to the stand-by controller B through a transmission controller 4A and a transmission interface 3A at every control period. Since the stand-by controller B performs the control operation at a preliminarily determined operation period each time when receiving process data, control operation results of both controllers coincide with each other with a phase delay.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention always makes the memory contents on the standby side of the duplex controller equal to those on the control side, thereby minimizing the influence on the process when switching the control right. The present invention relates to a control method for a duplex controller suitable for.

[Conventional technology]

An example of a redundant controller that shares only the process input/output device (hereinafter abbreviated as PI10).

For example, it is known from Japanese Patent Application Laid-Open No. 57-86972.

In Japanese Patent Application Laid-open No. 57-86972, a redundant control unit captures a destination address written in a plant database in its own controller by a controller having control authority (hereinafter referred to as the control side), and Data stored at an address is read from the control side and written to the corresponding address of a controller that does not have control authority (hereinafter abbreviated as standby side). In this method, only the control side performs control calculations, and all data t that has changed on the control side
By inputting V, the memory contents of both controllers are matched.

Furthermore, a method is known in which, in a dual-system controller, both the control side and the standby side perform calculations in synchronization according to the same input.

[Problem that the invention seeks to solve]

In the above-mentioned prior art, in Japanese Patent Application Laid-Open No. 57-86972,
Since the standby side controller is not operated, all memory contents that have changed on the control side must be sent to the standby side.The redundant control unit requires high speed, and to achieve this, a dedicated controller is required. Requires hardware. In addition, when performing control calculations while synchronizing both the control side and the standby side, a control section is required to produce synchronized sound on the control side and standby side, and a failure of the synchronization control section will cause damage to both systems of the redundant controller. Leads to down. In addition, in the latter method, the connection between both controllers is loose without having a synchronization control unit, and only the data fetched from PIlo is sent to the standby side, and the standby side performs calculations based on the above data. Because the control calculation on the standby side does not have a It becomes impossible to calculate based on 1
This may cause a mismatch between the memory contents of both controllers, and may cause disturbance to the process when the control authority is switched.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for controlling a redundant controller that can minimize the influence on processes when switching control rights between controllers.

[Failure to solve the problem]

The control side controller performs PIlo every predetermined control period.
Input process data from P and perform control calculations.
Send the process data input from Ilo to the standby controller [7, The standby controller executes control calculations at a predetermined calculation cycle every time it receives process data.

[Effect]

The controller on the control side performs control calculations for each control cycle, and the controller on the standby side performs control calculations for one control cycle at the timing of receiving process data from the controller on the control side. As a result, the control calculation results of both controllers become equal with a certain phase lag. Therefore, the contents of the plant database can be made to follow the control side controller without copying the entire plant database of one controller.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of this embodiment. controller A,
B is a redundant controller that shares the PIlo (process input/output device) 11 through the PI10 bus 10.

There is a data way 12 between both controllers. They are connected by a switching logic bus 9, and the former is connected to the controller A.
, B, and the latter is a transmission line that is also used for exchanging data with man-machine systems and other controllers.

This is a bus for communicating the diagnostic results of the diagnostic circuits 6A and 6B of both controllers. Furthermore, the data way 12 is duplicated in this embodiment, making the transmission between both controllers more reliable. IA and IB are central processing units (hereinafter abbreviated as CPU), each with 2A of memory.
, an input/output device to PIloll according to the program in 2B.

It controls data transmission/reception processing and control calculation processing through the data way 12. SARAKCPUIA.

The CPUIB has a periodic timer, and runs programs for PI 10 data input processing, PI 10 output processing, control calculation processing, data transmission processing and reception processing for transmitting and receiving virtual data through the data way 12, and each program. The work data area and plant database entity required for program execution are stored. memory 2
The memory maps of A and 2B are the same. 3A, 3B are transmission interfaces (hereinafter abbreviated as transmission I/F)>4A, 4
B is a transmission controller, which transmits and receives data between the data way 12 and the transmitting and receiving buffers in the memo IJ2A and 2B. 6A and 6B are diagnostic circuits, each of which is a CPUIA in its own controller.

1i3. Memory 2A, 2B, transmission controller 4A.

4B's self-diagnosis and through the switching logic bus 9, the other controller is notified of the diagnosis results of its own controller, and all the diagnosis results of the other controller are recognized.

7A and 7B are process input/output interfaces 7 ace (hereinafter referred to as P
I10Ili'), respectively CPUIA, 1
B performs input/output control when performing input/output processing to PIloll. 8A and 8B are switching circuits, which are turned on when the respective diagnostic circuits 6A and 6B determine that the control authority is granted to the own controller, allowing access to PIlol 1.

If it is determined that the own controller does not have control rights, it is turned off and access to PIlo is limited. Furthermore, these CPUs, memory, diagnostic circuits, PI/1) IP, and two controllers are interconnected via system bus 5A, and controller B is interconnected via system bus 5B, making it possible to send and receive data and control signals. . In particular, the transmission controllers 4A and 4B use the data way 12 as a control signal.
When data is received from , an interrupt is generated to CPUIA and IB respectively.

Figure g2 is a conceptual diagram showing the flow of data in the first embodiment. Since the following operations and configurations are the same for both controllers A and B, controller 8 will be explained. Processing 21a.

21b and 21c are PI 10 data input processing, control calculation, and PI 10 output processing, respectively, which are processed by the CPUIA in this order every time they are activated.

Processes 25 and 26 are PI10 import data reception process, P
This is I10 captured data transmission processing. These processes are stored in the memo 1J2A as a program. Also,
23 is PI10 output data Rakuno area, 24 is PI10
Imported data storage area.

27 and 28d are a transmitting buffer and a receiving buffer, respectively, and areas for these are secured in two memory areas with a difference of λ. Reference numeral 29 is a control right flag, which is a register that reflects whether or not the own controller has control 4M, and is present in the 1 diagnostic circuit 6A.

It can be referenced from the CPUIA via the system bus 5A.

First, the operation will be explained assuming that the own controller has control authority.

The CPUIA performs the periodic timer processing shown in FIG. 3 every time the periodic timer counts up. That is, the control cycle counter is updated in step 831 every time the cycle timer is activated. If it matches the nine control periods specified in step 832, the control period counter is reset in step 833. Thereafter, in step 834, it is determined by referring to the control right flag 29 whether or not the own controller has the control right. When there is control authority, the process of step 835 is performed and a series of processes 21a to 21c are activated. That is, the processes 21a to 21c are
If there is control authority, it is activated every control cycle. Among these activated processes, process 21a performs PI10 data input processing.

The detailed flow of PI10 data manual processing is shown in FIG.

In step 1941, the presence or absence of the control right is determined based on the control right flag 29. If the control right is present, in step 842, the PI
PI cabas 10 from roll. Switching circuit 8A, PI10
Processing process data via IF7Ae PI1 at 24
0 to the captured data storage area, and to controller B in S43.

Requests to send PI10 captured data.

Specifically, the PI10 captured data transmission process that receives the PI10 captured request transfers the PI10 captured data to the transmission buffer 27 to the PI10 captured data storage area in process 24. The above data is transferred from the transmission buffer 27 to the transmission I/F 3A by four transmission controllers.

It is transmitted to controller B via data way 12. In this embodiment, the control cycle and the data way 12 are used to transfer the PI 10 captured data to the transmission buffer 27.
This is because the transmission to is asynchronous. Next, processing 21b,
In control calculation processing.

Input correction calculation using the data in the P I 10 captured data storage area 24 as input, l) ]) C (pirectl)
Performs digital control) calculations and sequence control calculations. The calculation result of the process 21b is set to the PI 10 output data storage area 23. After the process 21b is completed, a process 21C, a PI 10 output process, is performed.

The flow of this process is as shown in No. 51. That is, referring to the control right 7 lag 29, if there is a control right, P
From the I10 output data storage area 23, the calculation result of the control calculation process is output to PIloll as a control output.

Next, the operation when the own controller does not have control authority will be explained. own controller) If the controller does not have the control right, the P received from controller B via the data way 12
Four transmission controllers transmit the I10 captured data.
After storing the data in the receive buffer 728 in the memory 2 through F3Af, the CPUIA is notified of the interrupt via the system path 5A (hereinafter referred to as "F3Af").

This interrupt is called a reception interrupt). CP notified of reception interrupt
The UIA executes the reception interrupt process shown in FIG. In this reception interrupt process, in step 861, the control right flag 2 is
See 9. If the control authority exists, the received data is read as invalid data.

If there is no control right, process 25. PI10 import data reception performance 4. P I receive data from the receive buffer 72B.
10 Transfer to the captured data storage area 24 and step 86
2, processes 21a to 21c are activated. Here, the processes 21a to 21C are activated by the periodic timer process shown in FIG. 3 when the own controller has control authority. If the own controller does not have control authority, the activation process of step 835 is passed in the determination process of step 834, so that processes 21a to 21C are not activated in any control period. In other words.

If there is no control right, the activation factor for the processes 213 to 21C is only "imprinting" received from the other controller.

Since the processing 21a determines in step 841 that there is no control right, step S42. Pass step 843f. Therefore, I'I10 captured data received via the data way 12 is set in the PI10 captured data storage area 24.

In the control calculation process of process 21b, the same calculation is performed regardless of the presence or absence of control authority. This process is performed by PIlo
24 without directly inputting data from the PI10 input data storage area, performs calculations, and only sets the calculation results in the PI10 output data storage area in process 23 without outputting the calculation results to PIlo. Calculations can be performed without being aware of the presence or absence of control rights. In process 21c, as shown in FIG. 5, the 1'I10 output of the calculation result is passed without control authority.

The following operation is shown in a time chart as shown in FIG. In Fig. 7, 1 time "" + tm*1 is the 3rd time
This is the time determined to be the control cycle in the cycle timer process shown in the figure. Here, the controllers on the control side and the standby side are at one time tyu, t2, etc. due to the time difference between the timers. There is a time lag of Δt.

In the time chart on the standby side, the hatched portion is in accordance with the present invention. In the present invention, P from the control side
At timing 71 when the I10 captured data is received,
Since the series of processes 218 to 21C are performed based on the received data, the process 21b on the standby side is performed using the same input data as that on the control side, and the memory contents on the standby side are updated with the time delay shown in 72. matches the controlling side.

Here, if the standby controller also starts the PI10 data input process to PI10 output process (time chart without hatching for processes 21a' to 210') at time t1 in the same way as the control phase, then process 21b' At the start point, since the PI10 captured data that the control side captured by the PI 1011 at time t has not arrived, the control arithmetic processing 21b on the control side ends and the control arithmetic processing 21 on the standby side.
The memory contents at the end of b' do not match. The result of the control calculation process started at time t may also be referred to as the previous value in the process started at time jm'+1, and mismatches in memory contents are accumulated. This discrepancy is
When switching the control right, there is a risk of disturbance to the process to be controlled, and it becomes difficult to equalize the memory contents of the two controllers only by transmitting PIIO input data. As described above, by applying the method of the present invention, only the PI 10 captured data is transmitted from the control side to the standby side.

Since it is possible to match the memory contents of both controllers, it is possible to configure a duplex controller that minimizes the influence of duplex system switching on processes without using special hardware.

〔Effect of the invention〕

According to the present invention, by transmitting only the manual data from the P-worker 10 from the control-side controller to the standby-side controller, it is possible to track the memory contents related to control calculation processing other than the above-mentioned data on the standby side, and to specify Conquer without any hardware! It is possible to configure a 23 & conversion controller in which the transfer of III rights has less impact on the plant.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram showing an embodiment of the present invention. Figure 2 shows the flow of data 7' (conceptual diagram, Figure 3 is a periodic timer processing flow diagram, Figure 4 is a PI 10 data input process 70-factor, Figure 5 is a PI 10 output processing flow diagram,
FIG. 6 is a reception interrupt processing flowchart, and FIG. 7 is a time chart showing the operation of the present invention. IA, 1B...Central processing unit (CPU), 2A. 2B...Memory, 3A, 3B...Transmission interface (transmission I/F), 4A, 4B...Transmission controller, 5A, 5B...System bus, 6A, 6B...
Diagnostic circuit, 7A, 7B... Process input/output device interface (PIloIF), 8A, 8B... Switching circuit, 9... Switching logic bus, 10... Process input/output device hash (PI10 bus), 11...Process person agent Patent attorney Katsuo Ogawa -゛2□ $ 2 Mouth zlC Kaya 3 Hard timer lma yo Sosuri LvJ Kaya 4-Kaya S solid, good Otsu eyes

Claims (1)

[Claims] 1. In a redundant controller in which two controllers that share a process input/output device are connected by a transmission line, and both controllers perform control calculations based on the contents of their respective memories, the control authority of both controllers is The control-side controller that has the control side takes in process data from the process input/output device every predetermined control cycle and performs control calculation processing, and also transfers the process data input from the process input/output device to the standby-side controller that does not have control authority. The dual control method is characterized in that the data is transmitted every control cycle, and each time the standby controller receives process data from the control controller, control calculations are performed for one control cycle based on the received data. How to control the controller.