JP2009251622A - Duplex control system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a duplex control system capable of reducing an execution period of time required for processing peculiar to duplex control. <P>SOLUTION: In this duplex control system equipped with two arithmetic units for executing arithmetic operations using the same input data, a first arithmetic unit is provided with: a transfer means for performing the burst transfer of input data inputted to the first arithmetic unit by a mirrored write function from a first equalizing operation region preliminarily arranged in a storage region for the first arithmetic unit to a second equalizing operation region preliminarily arranged in the storage region for the second arithmetic unit; and an invalidating means for invalidating the input data applied to the second arithmetic unit until the transfer of the input data by the transfer means ends. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a duplex control system including two arithmetic units that execute arithmetic operations using the same input data.

When duplicating the control operation of the field controller, the field controller is composed of two CPU cards on the control side and the standby side, and the two CPU cards are operated while being synchronized. Since such a duplex operation is established on the assumption that the same output result can be obtained for the same input, both CPU cards receive external input data (for example, input / output modules and Vnet). It is necessary to execute processing using the same data as communication data).
JP 2007-280313 A

  However, since the input data from the outside has a difference in value depending on the timing to acquire it, in the conventional system, after one CPU card (card on the input side) acquires the input data, the other CPU The process of passing this input data to the card is executed. By such processing, the input data given to both CPU cards is equalized (identified).

A general procedure as a conventional process is shown below.
(1) At the synchronization point, the control side and the standby side perform synchronization.
(2) The control side acquires input data from the IO space. Here, the control side cache-writes the input data to its own memory. At this time, the standby side is waiting at the next synchronization point.
(3) The control side and the standby side perform synchronization at the next synchronization point.
(4) The standby side reads the memory on the control side and writes it to the memory on its own side (standby side). Here, the standby side performs non-cache access to the control side space and performs cache write to its own memory. At this time, the control side is waiting at the next synchronization point.
(5) The control side and the standby side perform synchronization at the next synchronization point.

  As described above, in the conventional processing, the control side acquires data (input processing) while timing is synchronized, and the standby side acquires data from the control side (equalization processing) sequentially. is doing.

  However, the amount of input data acquired from the outside increases as the capacity of the field controller increases and the processing speed increases due to the improved processing capability of the CPU card. For this reason, unless the data input processing and equalization processing capabilities are improved, the ratio of the time required for the duplex processing increases and the execution time for the control processing is limited, as is the case with the improvement in the processing capability of the CPU card. End up.

  An object of the present invention is to provide a duplex control system capable of reducing the execution time required for processing unique to duplex control.

The duplex control system of the present invention is a duplex control system comprising a first computation unit and a second computation unit that respectively execute computations using the same input data, wherein the first computation unit is the first computation unit. Input data input to the arithmetic unit is provided in advance in the storage area for the second arithmetic unit from the first equalization work area provided in advance in the storage area for the first arithmetic unit. The second equalization work area is burst-transferred by the mirrored write function, thereby transferring the input data to the second arithmetic unit, and the transfer of the input data by the transfer means is completed. And invalidating means for invalidating input data given to the second arithmetic unit.
According to this duplex control system, since the input data input to the first arithmetic unit is burst-transferred from the first equalization work area to the second equalization work area by the mirrored write function, The time required for the equalization process can be shortened.

  The transfer means burst-transfers a frame generated during a write-back from the cache of the first arithmetic unit to the first equalization work area toward the second equalization work area by a mirrored write function. May be.

  The invalidation means may invalidate the input data in the second equalization work area on the cache of the second arithmetic unit by using a cache invalid instruction.

  According to the duplex control system of the present invention, the input data input to the first arithmetic unit is burst-transferred from the first equalization work area to the second equalization work area by the mirrored write function. Therefore, the time required for the equalization process can be shortened.

  Hereinafter, an embodiment of a duplex control system according to the present invention will be described with reference to FIGS.

  FIG. 1 is a block diagram showing the configuration of the duplex control system of this embodiment.

  The duplex control system of this embodiment includes a CPU 11 and a CPU 21 that are given the same input data and execute the same calculation. A cache 12 is provided for the CPU 11, and a cache 22 is provided for the CPU 21. FIG. 1 shows a state in which the CPU 11 functions as a standby side and the CPU 21 functions as a control side. Note that the duplex control system of this embodiment can be applied to both the hot standby system and the cold standby system.

  As shown in FIG. 1, in the duplex control system of this embodiment, the transmission side equalization work area 31 </ b> A and the reception side equalization work area 31 </ b> B corresponding to the CPU 11 correspond to the CPU 21 as dedicated areas of the RAM 31. An equalization work area 32B on the reception side and an equalization work area 32A on the transmission side are prepared as dedicated areas of the RAM 32, respectively. These areas are areas for performing mirrored write and must be specified by hardware registers. However, if this designated operation is performed every time input processing is performed, a processing time is required. Therefore, in this embodiment, a dedicated area is set in advance. In addition, since there is bidirectional equalization of equalization from the control side to the standby side and equalization from the standby side to the control side, the areas on the reception side / transmission side are set for each of the CPU 11 and CPU 21. It has a structure to have.

  The mirrored write function corresponds to the transfer means in the present invention, and when the CPU executes writing to the equalization work area (transmission side), it also applies to the equalization work area (reception side) of the other CPU. This is a function for writing through the backboard bus. In the duplex control system of this embodiment, the input process and the equalization process are simultaneously executed by such a mirrored write function. Also, the duplex control system of the present embodiment uses a burst transfer to transfer a block write frame (8 words) to the backboard bus when the write to the equalization work area (transmission side) is a block write. ) Is passed through as it is. In this way, data of 8 words can be transferred at a time by using the burst transfer of the backboard.

  FIG. 2 is a flowchart showing operations related to data input and data equalization in the duplex control system of the present embodiment. 2, step S1 and steps S11 to S14 correspond to the operation of the control side CPU 21, and step S1 and steps S21 to S24 correspond to the operation of the standby side CPU 11, respectively.

  In step S1, it is determined whether or not its own CPU is a CPU that receives data input. If the determination is positive, the process proceeds to step S11, and if the determination is negative, the process proceeds to step S21.

  In step S11 and step S21, synchronization is performed between the control CPU 21 and the standby CPU 11 at the synchronization point.

  Next, in step S12, the control-side CPU 21 acquires input data from the IO space and cache-writes it to the transmission-side equalization work area 32A. Data written to the cache 22 due to the occurrence of a cache miss hit is also reflected in the equalization work area 32A on the transmission side. The equalization work area 32A on the transmission side is reflected in the equalization work area 31B on the reception side on the standby side by mirrored light, and the data of both is the same.

  During the execution of step S12, in step S22, the standby side makes all the data in the equalization work area 31B on the receiving side that was on the cache 22 invalid by the cache invalid instruction. With this processing, when the standby side next refers to the data in the equalization work area 31B, the data becomes newly equalized data, that is, data updated by the mirrored write function. The process of step S22 corresponds to the function of the invalidating means in the present invention.

  Next, in step S13, the control side writes back the data in the equalization work area 32A on the transmission side that has been in the cache 22 by flash. By this processing, the input data in the equalization work area 32A of the cache 22 is cache flushed and reflected in the data in the equalization work area 32A. Further, this input data is also reflected in the equalization work area 31B on the reception side on the standby side by the mirrored write function.

  In step S14 and step S24, synchronization is performed between the control side CPU and the standby side CPU at the synchronization point, and the process ends.

  As described above, in the duplex control system of the present embodiment, the equalization work area is provided, and the input process and the equalization process are simultaneously performed by using the mirrored write function. In addition, data transfer between CPU cards (between equalization work areas) is burst transfer of the backboard, so that data that can be transferred at a time is 8 words at a time. Since the time required for equalization substantially occupies the backboard transfer time, by using burst transfer, the time required for equalization can be reduced to about 1/8 compared to the transfer of each word. .

  Due to these effects, the time required for the duplexing process, which is the duplexing overhead, is greatly shortened and the performance is improved, so that the execution time of the control process during the duplexing operation can be increased.

  As described above, according to the duplex control system of the present invention, the input data input to the first arithmetic unit is mirrored from the first equalization work area to the second equalization work area. Since burst transfer is performed by the write function, the time required for the equalization processing can be shortened.

  The scope of application of the present invention is not limited to the above embodiment. The duplex control system of the present invention can be widely applied to field control systems, safety instrumented systems, and other control systems.

The block diagram which shows the structure of the duplication control system of one Embodiment. The flowchart which shows the operation | movement regarding data input and data equalization.

Explanation of symbols

11, 21 CPU (first arithmetic unit, second arithmetic unit)
12, 22 Cache 31A, 31B, 32A, 32B Equalization work area

Claims (3)

In a duplex control system including a first arithmetic unit and a second arithmetic unit that respectively execute arithmetic operations using the same input data,
The first arithmetic unit receives input data input to the first arithmetic unit from a first equalization work area provided in advance in a storage area for the first arithmetic unit. Transfer means for giving the input data to the second arithmetic unit by performing burst transfer by a mirrored write function toward a second equalization work area provided in advance in a storage area for the arithmetic unit;
Invalidating means for invalidating input data given to the second arithmetic unit until the transfer of the input data by the transferring means is completed;
A duplex control system comprising: The transfer means burst-transfers a frame generated during a write-back from the cache of the first arithmetic unit to the first equalization work area toward the second equalization work area by a mirrored write function. The duplex control system according to claim 1, wherein: 2. The invalidation means invalidates the input data in the second equalization work area on the cache of the second arithmetic unit by using a cache invalid instruction. Or the duplex control system according to 2;

Images