JPH04114203A - On-vehicle electronic control system - Google Patents

Abstract

PURPOSE:To integrate the control system and to reduce the number of wirings to respective controllers by converting data for control to a serial data and executing concentrated management to the control data of the plural controllers loaded on a vehicle. CONSTITUTION:A slave controller M2 converts the driving state parameter of the vehicle detected by a parameter detecting means M1 or various internally processed data to the serial data and transmitted through a communication line to a main controller M4. Based on the various data from the respective slave controllers M2, the main controller M4 operates the data for control, converts this data for control to the serial data and communicates it through the communication line to the respective slave controllers M2. When the data from the main controller M4 is received, each slave controller M2 controls plural equipments M3 loaded on the vehicle based on this data. Thus, the control system is integrated, controllability is improved, and the number of wirings to respective controllers can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vehicle electronic control system in which a plurality of control devices are connected via a serial communication line.

[Prior Art] In recent years, microcomputers have been installed in vehicles such as automobiles, and these microcomputers are used for engine control, transmission control, brake control, etc., and have brought about a dramatic improvement in control functions. .

Next, we moved from a system in which multiple microcomputers perform individual control independently to a system in which multiple microcomputers are connected via serial channels to form an elliptical network and the required data is exchanged with each other through serial transmission. For example, JP-A-62-
Publication No. 237895 describes a method of connecting multiple control devices with a serial data link, and exchanging data via a single communication line even when data from sensors required by each control device overlaps with each other. A technique has been disclosed for reducing the number of wires inside a vehicle.

[Problems to be Solved by the Invention] However, in an independent distributed processing system in which multiple microcomputers are simply connected through a communication network, although it is possible to share data and reduce the number of wires, mutual task coordination is difficult. This is difficult and increases the overhead of each microcomputer during communication.

Furthermore, in systems where computers with different capabilities coexist, there is a risk that the throughput of the entire system will decrease, making it difficult to integrate the entire control system.

[Object of the Invention] The present invention has been made in view of the above circumstances, and aims to integrate control systems by centrally managing control data of a plurality of control devices mounted on a vehicle. The object of the present invention is to provide a vehicle electronic control system that can reduce the number of wires for a vehicle.

[Means for Solving the Problems] As shown in FIG. 1, the electronic control system for a vehicle according to the present invention includes a plurality of parameter detection means M1 for detecting driving state parameters of a vehicle, and the parameter detection means M1.
The operating state parameters detected by the controller or various data processed internally are converted into serial data and sent to the system m'A11M4 via the communication line. A plurality of subordinate control devices M that control a plurality of devices M3
2, is connected to the plurality of slave control devices M2 via the communication line, and calculates control data based on various data input from each of the slave control devices M2,
The control device M4 converts this control data into serial data and transmits it to each subordinate control device 1M2 via the communication line.

[Function] In the vehicle electronic control system having the above configuration, the slave control device 71M2 converts the vehicle operating state parameters detected by the parameter detection means M1 or various internally processed data into serial data, and transmits the data via the fll serial line. and transmits it to the main controller M4.

In the main control device ff1M4, each of the slave control devices M2
The controller calculates control data based on various data from the controller, converts the control data into serial data, and transmits the serial data to each slave control device M2 via the communication line.

When each slave control device 1M2 receives data from the main control device M4, it controls a plurality of devices M3 mounted on the vehicle based on this data.

[Embodiment J of the invention Hereinafter, the present invention will be described in detail with reference to the drawings.

Figure 2 and the following diagrams show an embodiment of the present invention. Figure 2 is a configuration diagram of a vehicle electronic control system according to the present invention, Figure 3 is a circuit block diagram of a communication LSI, and Figure 4 shows a communication format. FIG. 5 is a flow chart showing the communication procedure of the mask ECU, and FIG. 6 is a flow chart showing the communication procedure of the slave E CtJ.

(System Configuration) In FIG. 2, reference numeral 1 indicates a computer group installed in a vehicle such as an automobile, and these computer group 1 includes a main control unit TL (mask ECU) 1a, an engine control device, a transmission, etc. Multiple slave control devices (slave E) consisting of control devices, brake control devices, etc.
CU) lb, 1c, and ld are connected through a serial channel to form a communication network.

The mask ECU 1a has, for example, 16 bits or 3 bits.
2-bit master CPU10a, ROM11a, RAM
12a and communication LS 113 are connected to each other, and the slave ECUs 1b, lc,
ld is, for example, an 8-bit slave CPU1.
0b, 10c.

10d, ROMI lb, 11c, 11d, RAM12
b, 12c, 12d, I10 interface 14a,
14b, 14c, and the communication LSI 13 are connected in the same manner.

In the slave ECU 1b, sensors as parameter detection means such as a crank angle sensor 15 and an intake air sensor 16 are connected to the input port of the I10 interface 14a, and an injector 17, an ignition coil 18, etc. are connected to the output ports 1 to 1. Actuators as equipment are connected.

Further, sensors and switches such as a vehicle speed sensor 19, an accelerator switch 20, and a neutral switch 21 are connected to the input port of the I10 interface 14b of the slave ECU 1c, and an A/T actuator 22 and the like are connected to the output port. Actuators are connected.

Furthermore, the input port of the I10 interface 14c of the slave ECU 1d includes a wheel speed sensor 23,
Sensors and switches such as the brake switch 24 are connected, and actuators such as the ABS brake A actuator 25 are connected to the output boat.

Master CPU 10 a of the above mask ECU 1 a
<: The connected ROM 11a stores various calculation programs such as calculation of fuel injection amount and ignition timing, while the slave ECUs 1b to 1
RO connected to each slave CPU 10b to 10d of
M11b to lid respectively store control programs such as calculation of operating state parameters and engine control, transmission control, brake control, etc. based on the calculation results by the mask ECU 1a.

The mask ECU 1a and the slave F, CU 1b
~1d are connected by a serial communication channel via the same communication LS113, and the above communication LS1
13 is used in the mask operation mode when incorporated into the above mask ECLJ1a, and is used as slave ECU1b to 1
When installed in d, it is used in slave operation mode.

That is, the mask CPL 110a is used for each slave C
Various parameters required for calculation, such as engine rotation speed N and intake air amount Q, are requested to the PUs 10b to 10d via the communication LS 113 operating in the mask operation mode, and various parameters received from the slave ECUs 1b to 1d are requested. Based on the parameters, various calculations such as fuel injection pulse width Ti and ignition timing θ are executed, and the calculation data is sent to each slave CPU 10b to 10d to the communication LS1.
13.

On the other hand, each slave CPtJ10b to 10d has a mask E.
In response to a request from the CU 1a, via the communication LS 113 that operates in slave operation mode, the operating state parameters based on the output signals from each of the plow sensors (parameter detection means) are transmitted to the master CPU 10a;
Receives various data calculated by the master CPU 10a, and outputs control signals to various actuators (devices) at predetermined timings based on the received data, for example, control data such as fuel injection amount Ti, ignition timing θ, etc. do.

At this time, the serial communication channel is connected to the master E.
Started by CLJ1a, the above mask ECU 1
For communication of a, from S I 13 to each slave ECU 1
The timing is determined by the clock signal CL supplied to signals b to 1d. As a result, data is exchanged through bidirectional clock-synchronous communication using the transmission signal TX and reception signal RX.

(Circuit configuration of communication LSI) As shown in FIG. 3, the communication LS 113 includes a master/slave selection circuit 13a, a communication control circuit 13b, a reception circuit 13C, a transmission circuit 13d, a comparison circuit 13e, and an interrupt generation circuit 13f. an address decoder 30,
In addition, this is an LSI for in-vehicle networks in which hardware such as gates, flip-flops, and counters (not shown) are integrated on the same chip.By incorporating this chip into each ECU in the vehicle, a communication network between in-vehicle computers can be established. This can be achieved extremely easily.

The communication LS 113 is connected to the CPU of each ECU 1a to 1d.
10a to 10d, data bus 31 and address bus 32
and each connected CPU 10a~
From the 10d side, the system clock φ2, read/write signal R/14, address latch signal, master/slave selection signal) (SEL, etc.) are input, and the mask CP
It controls communication of reception data RX and transmission data TX through the serial communication channel activated by U10a, and outputs an interrupt signal INT after a predetermined communication operation.

Note that the tarlock φ1 is a communication clock received from the mask in the slave mode.

The master/slave selection circuit 13a is a circuit that selects between a mask operation mode and a slave operation mode, and sends a master/slave selection signal to an AND gate 33'' and a frequency divider 34).
ISEL is input, and the divided output from the frequency divider 34 and the clock input are input to the OR gate 35, which outputs the communication clock C to the inside of the LS113 and the outside of the LS113.

The system clock φ2 is inputted to the frequency divider 34, and when in the mask operation mode, the boss selection signal H3EL, The frequency of the system clock φ2 is divided by the address decode signal D and the read/write signal R/W to output the communication clock CLK.

Furthermore, when the frequency divider 34 is in the slave operation mode,
The system clock φ2 is frequency-divided and outputted as a clock φ1 inputted from the outside, that is, a monitoring clock 5CLK for detecting an abnormality in the communication clock C[K.

The communication control circuit 13b includes counters 36, 37 and a comparator 3.
8, and consists of 39 AND gates.

The output from the OR gate 35 of the master/slave selection circuit 13a is counted by a counter 36 and output to a comparator 38, as well as to a receiving circuit 13c and a transmitting circuit 13d.

The comparator 38 compares the count number of the counter 36 with a predetermined number of bits, determines whether or not data transmission or reception of a predetermined number of beeps has been completed, and sends the interrupt generation circuit 13f to the interrupt generation circuit 13f. Output a signal.

Furthermore, in the slave operation mode, the counter 37 receives a clock φ inputted from the outside as a communication clock CLK.
1 is monitored by the monitoring clock 5CLK from the frequency divider 34 to detect the presence or absence of an abnormality, and if an abnormality is detected, a reset signal is output to each part.

The receiving circuit 13c is composed of a receiving buffer consisting of a register 40, a serial-to-parallel converter (S-P converter) 41, etc., and converts received data RX received through serial communication into parallel data by the above-mentioned S-P converter 41. and stores it in the register 40.

The transmitting circuit 13d is composed of a register 42, a transmitting buffer consisting of a register 43, and a parallel/serial converter (p, s converter) 44 such as a multiplexer. The transmission data TX is output to the p-s converter 44 via the register 43 which is a transmission buffer, and is converted into serial data and transmitted.

The comparison circuit 13e includes comparators 45, 46 and an AND gate 4.
7, and the comparator 45 includes the receiving circuit 13.
The first received data received at 0 is set and compared with the data in the register 43 (transmission buffer) of the transmission circuit 113d. A part of identification information data, which will be described later, is set and compared with the first data in the register 40 of the receiving circuit 13c.

If the comparison result of the comparator 45 matches the data contents, its output changes from high level to low level, and the register 40 of the receiving circuit &813c and the transmitting circuit 13
It is output to the P-8 converter 44 of d and is also input to the AND gate 47.

Further, if the data contents match as a result of the comparison by the comparator 46, the output similarly changes from high level to low level and is input to the above-mentioned game 1 47.

The output of the AND gate 47 is input to the interrupt generation circuit 13f as an interrupt factor signal via the AND gate 1.33 of the master/slave selection circuit i3a.

The interrupt generation circuit 13f is composed of an OR gate 48 and a flip-flop 49, and receives the communication end signal from the communication control circuit 13b and the master/slave selection circuit 1.
The output from the OR gate 3a is input to the OR gate 1-48, and the output of the OR gate 48 triggers the flip-flop 49 to output an interrupt signal INT.

The flip-flop 49 is reset by each CPU that receives the 18 interrupt signals writing data to a predetermined address, so that each CPU can handle either edge trigger or level trigger interrupt signals. It has become.

Next, the operation of the embodiment with the above configuration will be explained.

(Operation of the mask ECU) In the mask ECU 1a, the communication L S
By inputting the master/slave selection signal HSEL of 0" to the master/slave selection circuit 13a of I13, the communication LS113 is set to the master operation mode, and the CP
According to the memory space of U10a, for example, the upper 4 bits of the address bus 32 are decoded, and the lower 4 bits are used to access various functions related to communication.

For example, received data RX (4 pies!-) is stored in each address whose lower 4 bits are addresses OOH to 03H, and when the CPL 110a reads this address, the data is stored in the register 40 (receiving buffer) of the receiving circuit 13c. The data is taken in via the data bus 31, and
The above C is added to each address from 04H to 08H of the lower 4 bits.
When the PIJ10a writes data, the data bus 31
Transmission data TX (5 bytes) is sent to the transmission circuit 13 via
The write length is stored in the register 42 of d.

Furthermore, the address OA is set by the master CPU 10a.
The data written in H determines the communication speed, and the frequency divider 34 of the master/slave selection circuit 13a divides the system clock φ2 to output the communication clock CLK, thereby setting the communication speed.

In the mask operation mode, the clock φ1 is not used and is always "0", and the communication clock CL output from the frequency divider 34 is directly outputted to the outside via the ORG-1-35, and is sent to the slave ECUs 1b to 1d. L for each communication
It is supplied to S113.

At the same time, the master/slave selection signal Fl[ is applied to the AND gate 33 of the master/slave selection circuit 13a.
Regardless of the signal from the comparator circuit 13e that is input to the AND gate 33 with its output always set to "O", an interrupt is generated by a transmission end signal from the comparator 38 of the communication control circuit 13b, which will be described later. At the same time, it is input to the counter 37 of the communication control circuit 13b, and the counter 37 is stopped and its output is kept at a high level.

Then, the transmission data TX by the master CPU 10a is
Immediately after the writing of T is completed, communication is started, and the counter 36 of the communication control circuit 13b controls the communication clock C.
[In other words, the number of bits of the transmission data TX is counted and the S, P converter 41 of the receiving circuit 13C is counted.
A synchronizing signal is output to the p-s converter 44 of the transmitting circuit 13d, and the signal is transmitted from the mask ECU 1a to each slave ECU.
Serial data is transmitted to 1b to 1d in a predetermined format), and necessary data is received.

As shown in Figure 4, the transmitted data is HD^■^1~HD
It consists of 5 bytes of ^1^5, the first byte data HDATA1 and 2 bytes), [1 data HDATA
TA2 is identification information data. That is, first, in the first byte of data HDATA1, the ECU number of the slave EC'tJ requesting data transmission (for example, identification information data indicating the slave ECU 1b, which is an engine control device; bits 6 to 4). ) and the type of requested data (for example, identification information data indicating that it is engine rotation speed and intake air amount data; bits 3 to LSB).

Next, in the second byte of data HD^TA2, the destination slave EC sends the data from the mask ECU.
The ECU number of U (bits 6 to 4) and the type of data to be transmitted (bits 3 to LSB) are sent, and the remaining 3 bytes are used to send data calculated by the master CPU 10a, for example,
Data such as fuel injection pulse width T is transmitted.

Then, when the count number of the communication clock CLK reaches 40 bits in the counter 36 of the communication control circuit 13b, the output of the counter 36 and the comparison data of the comparator 38 (
40 pixl~) match, and the output of the comparator 38 changes from high level to low level as a communication end signal. As a result, the output of the AND gate 39 is inverted from high level to low level, resetting the counter 36, and the output of the comparator 38 is input to the OR gate 48 of the interrupt generating circuit 13f, becoming an interrupt factor. The transmission of the byte data is finished.

In the interrupt generation circuit 13f, one input to the OR gate 48 is the output from the AND gate 33 of the master/slave selection circuit 13a, which is always 0'', so the comparator 38 of the communication control circuit 13b When the output of is reversed from high level to low level, flip-flop 49
The input to the 4 flip-flops is inverted from high level to low level, and the four flip-flops are triggered at the falling edge, and an interrupt signal INT is generated. This causes an interruption to the master CPUIQa, and receives the received data RX.

In other words, 5 bytes (40 bits) of transmission data is sent from the mask to each slave in one communication, and after the communication is finished,
There is an interval of two or more clocks until the next communication starts.

(Operation of slave ECU) On the other hand, in each slave ECU 1b to 1d, communication LS1
13 master/slave selection circuit 13
The slave selection signal ISEL is set to 1'' and the communication LS 113 is used in slave operation mode.

That is, when the master/slave selection signal +13[[ is set to "1'", the frequency of the system clock φ2 is divided by the frequency divider 34 and outputted as the monitoring clock SCL.

This monitoring clock SCL includes "1 master ECU 1a"
A tally clock having a cycle longer than 1/2 of the cycle of the communication clock C[, which is input as a tally clock φ1 from the OR gate 35, and is inputted to the communication control circuit 13b.

It should be noted that the communication clock C output from the OR gate 35
The signal is also output to the outside of the communication LS 113 and can be used by other slave ECUs.

Each slave CPU 10b to 10d writes the transmission data TX to the register 42 of the transmission circuit 13d in advance to prepare for communication, but in this case, the address 040 to 08H
The transmission data TX written in is 4 bytes (04H is not used on the slave side), and as shown in Figure 4, the first data 5DATA1 is the ECU number (bits 6 to 6) of the slave ECU that transmits the data. 4), and
This is identification information data indicating the type of data to be transmitted (bits 3 to LSB).

Then, when communication is activated by the mask ECU 1a, data from the mask ECU 1a is received,
No data is sent from the slave ECUs 1b to 1d in the first byte, and the comparator 45 of the comparison circuit 13e compares the first byte received data HDATAI from the master ECU 1a with the sending buffer. A certain register 43
1 byte "1 data SD to ■1" is compared.

For example, if the content of the first byte of data T^1 from the mask ECU 1a is a data request to the slave ECU 1b, and the type of data requested is engine rotation speed data, the slave ECU ],
When the 1-byte L1 data 5DAT^1 prepared in advance in b matches the above content, the output of the comparator 45 changes from high level to low level, and a transmission instruction is output to the p-s converter 44 of the transmission circuit 13d. The data is immediately started to be transmitted from the transmitting circuit 13d to the master ECU 1a, and is also input to the register 40 of the receiving circuit 13c.

Then, as a result of the output from the comparator 45, the MSB (bit 7) of the data HDATA2 from the mask ECU 1a stored in the register 40 is cleared to "O". To ^2
By reading the MSB of , it can be determined whether or not data has been transmitted to the mask ECU 1 a when an interrupt occurs.

The output of the comparator 45 is input to the AND gate 33 of the master/slave selection circuit 13a via the AND gate 47, and one input of the AND gate 1/33 receives the master/slave selection signal "1 pass". Therefore, the output changes from high level to low level and is input to the OR gate 48 of the interrupt generating circuit 13f.

In this case, in the other slave ECUIC, 1 (1), the first byte received data T^1 from the mask ECU 1a does not match the prepared first byte data 5DATA1, so it does not send the above data. Slave ECU
In 1b, the above data SO^TA1 (= HDATA
I) followed by 3 bytes of data SD^TA2~5DAT
^4 are sequentially transmitted in synchronization with the communication clock CLK from the mask ECU 1a.

When the count of the communication clock CLK in the counter 36 of the communication control circuit 13b reaches 40 bits), a low-level communication end signal is output from the comparator 38, and the OR gate of the interrupt generation time 1i'813f is output. 48.

When data is transmitted to the mask ECU 1a, or as a result of comparing the second byte received data HO^TA2 from the mask ECU 1a with the comparator 46 of the comparison circuit 13e, it is determined that the ECU number of the received data HDATA2 is the same. When the ECtJ number matches the ECtJ number of the above-mentioned comparison circuit 13e, that is, when a low-level signal that causes an immediate 1-input is output from one or both of the comparators 45 and 46 of the above-mentioned comparison circuit 13e, one of the OR gates 48 of the above-mentioned interrupt generation circuit 13f input becomes low level.

Therefore, the four flip-flops are triggered by the fall of the output signal of the comparison circuit 13e or the communication end signal from the communication control circuit 13b, and an interrupt signal is output from the interrupt generation circuit 13f, so that the necessary data is transferred to each slave. It is incorporated into the CPUs 10b to 10d, and
The new transmission data is sent to the register 42 of the transmission circuit 13d.
will be written to.

On the other hand, when there is no data transmission to the mask ECU 1a and no data transmission from the master ECU 1a to itself, the output of the comparison circuit 13e remains at a high level, and therefore the interrupt generation circuit Since one input of the OR gate 13f remains at a high level, no interrupt is generated even if the communication end signal is input from the communication control circuit 13b to the interrupt generation circuit 13f.

That is, since no signal is output from the comparator circuit 13e that causes an interrupt, no operation is performed and the next communication is waited for.

Furthermore, the mask ECU1a and each slave ECU1b
In communication with ~1d, the communication clock CLK is monitored by the counter 37 of the communication control circuit 13b, and noise and the like get mixed into the communication clock C and cause the slave ECU to
1 If an erroneous count of the communication clock C[ occurs on the b to ld sides, the communication will end once and the interval between the communication clock C[ and the above communication clock C[ will be 2 or more clocks before the next communication starts. At this point, three or more clocks of the monitoring clock 5CLK are detected. Then, a low level reset signal is output from the counter 37, and each part is reset.)
・This prevents incorrect data from being initialized.

Incidentally, the interrupt signal IN■ from the interrupt generating circuit 13f is as follows.
It is reset by writing the appointee's data to address 09H.

(Data communication procedure) Next, mask ECUla and slave ECU 1b~1
The data communication procedure with d will be explained according to the flowcharts of FIGS. 5 and 6.

(Mask ECU communication procedure) The flowchart in FIG. 5 shows the communication procedure of the mask ECU 1a. First, in step 5101, the communication LS
113, and in step 5102, the master CPU 10a sets 5 bytes of data, ie, the destination ECUNO, and the type of data (control data, transmission request data) in the communication LS 113.

Next, when the 5-byte data set from the master CPU 10a is completed, steps 5102 to 5 are performed.
The process proceeds to step 103, where the communication channel is activated by the communication LS 113, and communication is immediately started.

Next, in step 5104, 40 communication clocks CL
K and the 5-byte data set in step 5102 above are transmitted to each slave ECU 1b to 1d, and when the communication is completed, in step 5105, the communication LS 11
3 sets the interrupt terminal of the master CPU 10a to a low level to start interrupt processing of the master CPU 10a.

Then, when the process advances to step 8106, the master CPU
10a writes arbitrary data to a predetermined address in the communication LS 113, returns the interrupt terminal of the master CPU 10a to high level, and proceeds to step 5107.

When the process proceeds to step 5107, the master CPU 10a reads the received data of 4 bytes) from the communication LS 113, and then returns to step 5102 to prepare for the next communication. Note that control data such as the fuel injection pulse width T1 is calculated based on the received data while the communication LS 113 is communicating.

(Communication element R of slave EC1J) On the other hand, FIG. 6 shows the communication procedure of each slave ECU i b to 1d.
Communication LS1 from 0b to 10d via data bus 31
The data for the monitoring clock SCL is set in 1B, and in step 5202, the communication clock CLK and data are received from the master ECLlla.

Next, the process advances to step 5203, where the communication clock C
[] and the monitoring clock SCL set in step 5201 above, and if the rising edge of the monitoring clock 5CLK is detected three or more times within the time when the communication clock C is at a low level, the communication clock SCL is Clock C [
It is determined that there is an abnormality due to the contamination of noise, etc., and the process proceeds to step 5204, where the communication LSI 13 is reset, and the process returns to step 5201.

On the other hand, in step 5203, if the rising edge of the monitoring clock 5CLH is not detected three or more times within the time period in which the communication clock C[K is at a low level, the communication clock C[K is determined to be normal and the step 5205
Then, based on the first item information data from the mask ECU 1a, that is, the 1st byte data HDATAI, it is determined whether or not a data transmission request has been designated from the master ECLJ 1a.

When there is a transmission request from the mask ECU 1a,
The process proceeds from step 5205 to step 3206, and the data 5DAT^1 to 5DATA4 prepared in advance are transmitted to the mask ECU 1a.

If there is no transmission request designation from the mask ECU 1a, the process proceeds from step 5205 to step 5207, where it is determined whether the count number of the communication clock CL has reached 40 pulses.

If the communication clock CLK has not reached 40 pulses in step 5207, the process returns from step 5207 to step 5202 to receive the next data from the mask ECULa, while the communication clock CL has reached 40 pulses. If so, the process proceeds from step 5207 to step 8208, where the counter for the communication clock 01 is reset, and the process proceeds to step 5209.

In step 5209, it is determined whether data has been transmitted to the master ECTJ 1a, and if data has been transmitted to the mask ECUla, step 521
0 and the data H received from the mask ECU 1a.
Clear the MSB (bit 7) of D^■^2 and proceed to step 5212.

On the other hand, in step 5209, the mask ECU1a
If no data is being sent to the mask EC, the process proceeds from step 5209 to step 5211, and the mask EC
Based on the identification information data set ■^2 from U1a, it is determined whether data for itself has been received or not, and if data for itself has been received, the process proceeds from step 5211 to step 5212.

Next, step 5210 or step 5211
When the process advances to step 5212, the communication LSI13
sets the interrupt terminals of each of the slave CPUs 10b to 10d to low level to start interrupt processing, and proceeds to step 5213.

In step 5213, each slave CPL 110b to 1
Each slave CPU 10 writes arbitrary data to a predetermined address from 0d to the communication LS 113.
The interrupt terminals b to 10d are returned to high level and the process advances to step 5214.

Then, in step 5214, the mask ECU 1a
When the slave ECtJ 1 b receives the physical quantity data HDATA3 to HDATA5 together with the identification information data HDATA2 from the slave ECtJ 1 b, for example, when the slave ECtJ 1 b receives the fuel injection pulse width Ti, the data HDATA2 of those 4 pie 1 to
~Load HAO^■^5.

In addition, data HDAT from the mask ECU 1 a
When the MSB of ^2 is "0'°, that is, when data is transmitted to the mask ECU 1a, new transmission data is set from the slave CPU to the communication LS 113, and the process returns to step 5202.

On the other hand, in step 5211, if data for itself has not been received, the process returns to step 5202 and waits for the next data input from the mask ECU 1a.

For example, the slave ECU 1b calculates parameters such as the engine rotation speed N and intake air ff1Q from input signals from sensors (parameter detection means), and
This data is transmitted at the time of request communication from U1a, and a drive signal having a fuel injection pulse width Ti as control data received from mask ECU1a is outputted to the injector 17 as a device at a predetermined timing.

As a result, the mask ECU 1a performs arithmetic processing of control data that was conventionally processed independently by multiple control devices, and the common data between each slave ECU 1b to ld is centrally managed. and each slave EC
The load on U1b to 1d is significantly reduced.

In addition, since each slave ECU 1b to 1d can receive control data based on operating state parameters from sensors that are not input to itself from the mask ECU 1a,
There is no need to redundantly connect each sensor to each slave ECU 1b to 1d, and the number of wires in the system can be significantly reduced.

In this embodiment, the communication between the computers has been described as being of the tarlock synchronous type, but the present invention is not limited thereto, and can also be applied to start-stop synchronous type of communication.

[Effects of the Invention] As explained above, according to the present invention, a plurality of parameter detection means for detecting driving state parameters of a vehicle, and driving state parameters detected by the parameter detection means or various internally processed data are serially transmitted. A plurality of slave control devices that convert the data into data and transmit it to the main control device via a communication line, and control a plurality of devices installed in the vehicle based on the data received from the main control device, and It connects to the plurality of slave control devices mentioned above through a line, calculates control data based on each company's data input from each slave control device, converts this control data into serial data, and connects the communication line to the above communication line. Since the main control device is equipped with the main control device that transmits data to each of the subordinate control devices via the main control device, all data in the system can be centrally managed by the main control device, realizing control system integration and improving controllability. In addition to this, excellent effects such as being able to reduce the number of wires for each control device are achieved.

[Brief explanation of drawings]

Figure 1 is a claim correspondence diagram showing the basic configuration of the present invention, Figure 2 is a claim correspondence diagram showing the basic configuration of the present invention.
The figures below show one embodiment of the present invention, Fig. 2 is a configuration diagram of a vehicle electronic control system according to the present invention, Fig. 3 is a circuit block diagram of a communication LSI, and Fig. 4 does not show the communication format. The explanatory diagram, FIG. 5 is a flowchart showing the communication procedure of the mask ECU, and FIG. 6 is a flowchart showing the communication procedure of the slave ECU. Ml...Parameter detection means M2...Slave control device M3...Device M4...Main controller No. 5 Fig. 6

Claims (1)

[Scope of Claims] A plurality of parameter detection means for detecting driving state parameters of the vehicle, and converting the driving state parameters detected by the parameter detection means or various internally processed data into serial data and transmitting the serial data via a communication line. A plurality of slave control devices that transmit data to the main control device and control a plurality of devices mounted on the vehicle based on data received from the main control device, and a plurality of slave control devices that communicate with each other via the communication line. and calculates control data based on various data input from each of the slave control devices, converts this control data into serial data, and transmits the serial data to each of the slave control devices via the communication line. A vehicle electronic control system characterized by comprising a main control device.