JPH0585048B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a microprogram branch control method when jumping or branching to an address on a microprogram specified by a microinstruction in a control device employing a microprogram control method. It is related to.

[Conventional technology]

As conventional microprogram branch control systems of this type, there are generally known branching systems using horizontal microprograms and branching systems using vertical microprograms.

The former horizontal branching method has the advantage of high effective speed because calculations, shift functions, etc. and branching functions can be written in one microinstruction, but on the other hand, the bit width of one microinstruction is long, and the microprogram memory is The disadvantage is that the capacity becomes large.

In addition, the latter vertical branching method creates separate types of microinstructions for calculations, shift functions, and branching functions, and by limiting the functions that can be described with one instruction, memory usage efficiency is improved and microinstructions are Although it has the advantage of saving program memory capacity, it has the disadvantage of slow effective speed because calculations, shift functions, and branch functions cannot be written in one microinstruction.

Various improved methods have been proposed to take advantage of these advantages and compensate for their drawbacks. FIG. 3 is an explanatory diagram of a conventional microprogram branch control system disclosed in, for example, Japanese Patent Laid-Open No. 58-201147. In the figure, 1 is a high-speed readable microprogram storage memory in which a microprogram is stored, and 2 is a high-speed readable branch information storage memory.

In addition, M in the figure is an information field that specifies the type of operation, shift operation, target register number, etc., and BSEL is a 1-bit width that indicates whether the branch control function of this microinstruction is enabled or disabled. The branch instruction field BNO is a branch number field that indicates the type of branch control.

Next, the operation will be explained. For microinstructions that do not require branch control, write the BSEL field as "invalid". When executing such an instruction,
The next microprogram address is automatically +1
be done.

For microinstructions that require branch control, the BSEL field is written as "enabled," and the branch shape type BOP, branch condition BCC, and branch destination address BAD are stored in the branch information storage memory 2. This storage address is written in the BON field of the microprogram storage memory 1.

When the microinstruction is executed, when the BSEL field is "valid", the H/W (hardware) determines whether the branch condition is met or not based on the contents of the branch information storage memory 2, and when the condition is met,
The microprogram address written in the BAD field becomes the address of the next instruction.

Therefore, according to this method, instead of a field related to branch information in a microinstruction, only a logical number (address of branch information storage memory 2) corresponding to the type of branch information and a branch indication field (7 bits) are used. All you have to do is store it.

Assuming that there are n types of branch information, the width of the branch function description field is n1+1 bits (n=2 ⁿ¹ ).
If the address space of the microprogram storage memory 1 is ^2l , generally n1+1≪l, and the capacity of the microprogram storage memory 1 can be reduced.

[Problem that the invention seeks to solve]

Since the conventional microprogram branch control system is configured as described above, all combinations of branch formats, branch conditions, and branch destination addresses used in the microprogram are stored in the branch information storage memory 2. Therefore, even if the capacity of the microprogram storage memory 1 decreases, the capacity of the branch information storage memory 2 increases.

Furthermore, there is a problem that managing the correspondence between all branch instructions and branch information storage addresses becomes complicated.

This invention was made to solve the above-mentioned problems, and aims to provide a microprogram branch control method that can further improve memory usage efficiency without sacrificing the advantages of the horizontal branch method. purpose.

[Means for solving problems]

The microprogram branch control method according to the present invention includes a microprogram storage memory that stores a sequence of microinstructions, a branch address memory that stores an absolute address of a branch destination, and an addition/subtraction operation that calculates a branch destination address from a relative address and an actual row address. and a branch address selection circuit that selects either the output value of the branch address memory or the output value of the adder/subtractor as a branch destination address for performing branch control.

[Effect]

In the present invention, an adder/subtractor calculates a branch destination address from a relative address indicated in a branch number field included in a microinstruction string stored in a microprogram storage memory and an actual row address;
The branch address selection circuit selects the branch destination address calculated by the adder/subtractor and the output value of the branch address memory, and operates to perform branch control using the selected value as the branch destination address.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, it is a microprogram storage memory that stores one microprogram and can be read at high speed.

An example of the structure of a microinstruction string stored in the microprogram storage memory 1 is shown in FIG. In this figure 2, M is a field that specifies the operation type, shift operation, target register number, etc., and BOP is a branch format type setting field that specifies the type of branch format, and if branching is not necessary, indicate so. Write the code that shows.

Also, BCC is the branch condition specification field, BTYP
is a branch type field, and is a 1-bit field that indicates whether the branch performed by the micro instruction is a short-distance branch or a long-distance branch. For example, it is "0" for a short-distance branch, and "1" for a long-distance branch. given that,
If "0" is specified, the next branch number field BN0 is the relative address (positive or negative) of the branch destination.
If "1" is specified, it is interpreted as the address of a branch address memory, which will be described later, that stores the absolute address of the branch destination.

The above-mentioned short-distance branch here refers to a branch to a relatively close address that is commonly used, and long-distance branch refers to a branch to a distant address that occurs less frequently. .

The explanation returns to FIG. 1 again. In Figure 1, 2
A is the branch address memory mentioned above, which stores the absolute address of the branch destination and can be read out at high speed.

Further, 3 is a pipeline register to which the output of microprogram storage memory 1 is set and outputs the control signal specified by the microinstruction, and 4 is the branch destination relative address specified by the above BN0 field and the current execution address. This is an adder/subtractor for calculating an absolute address from .

5 is a branch address selection circuit that selects either the output of the branch address memory 2A or the output of the adder/subtractor 4 according to the specification of the BTYP field, and 6 is a program counter that indicates the address of the microinstruction to be executed.

7 is a decoder, which is the pipeline register 3 above.
A comparator 8 compares the output of the data 7 with the output of the branch condition selection circuit 9 to determine whether the branch condition is met or not.

This branch condition selection circuit 9 is configured to receive signals C ₁ -Cn indicating the execution state of the control device.

Next, the operation will be explained. In this invention, in the short-distance branch, branch control is performed by specifying a relative address, and in the long-distance branch, branch control is performed by referring to a branch address memory.

However, the term "short distance" or "long distance" as used herein differs depending on the system to which this invention is applied, and the most efficient short distance branching range is determined for each system, and the area outside that range is defined as long distance.

Now, set the bit width of the BN0 field in Figure 2 to W.
Then, 2 ^w types of branch destination absolute addresses can be written in the branch address memory 2A, and a branch to an address range of ±2 ^w-1 from a branch instruction is a short distance branch, and other branches are long distance branches. It becomes a distance branch.

For example, if the BTYP field is "0" at address a1 of microprogram storage memory 1,
When a short-distance branch instruction m1 in which the BN0 field is r is stored, this microinstruction is executed as follows.

In other words, address a is written to program counter 6.
When set to 1, the microinstruction m1 in the microprogram storage memory 1 is taken out to the pipeline 3, a control signal according to its contents is output to each part, and the program counter 6 is set to +1.
It is counted up.

In this case, since the content of the BN0 field of the microinstruction m1 is r, the adder/subtractor 4 writes (a1
−1)+r−1 operation is performed, and as a result, a1
The address +r appears at the output of the adder/subtractor 4.

Also, since the value of the BTYP field of microinstruction m1 is "0", branch address selection circuit 5
selects the output of adder/subtractor 4.

On the other hand, the branch condition selection circuit 9 is provided with a signal indicating the execution state of the control device, such as carrying a calculation result.
C ₁ to Cn are input, and a predetermined state signal designated by the contents of the branch condition designation field BCC is selected from among these signals and output to the comparator 8 .

Further, the content of the branch format type indication field BOP is decoded by the decoder 7, and the signal is compared with the output of the previous branch condition selection circuit 9 by the comparator 8 to determine whether the branch condition is satisfied or not. be exposed.

When the branch condition is satisfied, the comparator 8 outputs, for example, "1" as a load signal for the program counter 6, and the output of the branch address selection circuit 5, that is, the value of a1+r, is loaded into the program counter 6. Therefore, the microinstruction stored at address a1+r of microprogram storage memory 1 is executed next.

On the other hand, if the comparator 8 determines that the branch condition is not satisfied, the output of the comparator 8 is "0", so the branch address a1+r is not loaded into the program counter 6, and the current value of the program counter 6, that is, Address a1+1 is executed next.

A long-distance branch instruction m2 in which the BTYP field is "1" and the BN0 field is b1 is sent to address a2 of microprogram storage memory 1.
If the far branch instruction m2 is stored in the microinstruction m2, the execution of the far branch instruction m2, that is, the microinstruction m2 is as follows.

The process until microinstruction m2 is set in the pipeline register 3 is the same as the execution of microinstruction m1, but in the case of microinstruction m2,
Since the value of the BTYP field is "1", the branch address selection circuit 5 selects the branch address memory 2.
Select the output of A.

Here, address b of branch address memory 2A
Assuming that data x is pre-stored in 1,
Similarly to the case of the microinstruction m1, when the branch condition is satisfied and the output of the comparator 8 becomes "1", the address x is loaded into the program counter 6. Therefore, the microinstruction stored at address x in microprogram storage memory 1 is executed next.

Note that in the above embodiment, a branch instruction, that is,
The branch relative address and the address of the branch address memory 2A are written in the microinstructions m1 and m2, respectively, but after the microinstruction is set in the pipeline register 3, the next execution address is written to the output terminal of the program counter 6. In order to shorten the time it takes to appear, branch instructions, that is, instructions that are executed immediately before microinstructions m1 and m2, are used.
A structure may also be used in which the values of the BTYP field and BN0.yield are written and the branch destination address is latched in the branch address selection circuit 5.

However, the branch destination relative address at this time must be a relative address to the instruction executed immediately before the branch instruction.

〔Effect of the invention〕

As described above, according to the present invention, a branch destination address is calculated by an adder/subtractor from the relative address indicated in the branch number field and the actual row address, and the calculated branch destination address and the output value of the branch address memory are is selected by the branch address selection circuit, and the selected value is used as the branch destination address. Therefore, branches to nearby addresses, which are relatively frequently used, are performed by specifying relative addresses, and branches to distant addresses are performed. Branches can be performed by referring to the address memory. Therefore, the microprogram storage memory stores a small bit-width relative address and the address of the branch address memory, and furthermore, only a small number of branch destination addresses can be branched. It is sufficient to store it in the address memory.

This has the effect of further increasing memory usage efficiency without sacrificing the advantages of the branching method using horizontal microprograms.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microprogram branch control system according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the structure of a microinstruction applied to the same embodiment, and FIG. 3 is a conventional microprogram branch control system. FIG. 1 is a microprogram storage memory, 2A is a branch address memory, 4 is an adder/subtractor, and 5 is a branch address selection circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A microprogram storage memory that stores a microinstruction string including a branch type field that indicates whether a branch number field that specifies a branch destination indicates a branch destination relative address or a separately recorded branch destination absolute address; a branch address memory that is accessed using the contents of the branch number field as an address and stores the absolute address of the branch destination; an adder/subtractor that calculates the branch destination address from the relative address indicated in the branch number field and the actual row address; A microprogram branch control system comprising: a branch address selection circuit that selects either the output value of the branch address memory or the output value of the adder/subtractor as a branch destination address for branch control according to a value of a type field.