JPH01106140A - Branching control system for microprogram - Google Patents

Abstract

PURPOSE:To improve the memory availability by calculating a branch destination address from the address under execution and the relative address shown in a branch number field and selecting the output of a branch address memory via a branch address selecting circuit. CONSTITUTION:In case a short-distance branching instruction is stored in an address a1 of a microprogram memory 1, a program counter 6 is set at the a1 and said branch instruction is delivered to a pipeline 3. Under such conditions, an adder/subtractor 4 calculates an absolute address from the address under execution and the relative address of the branch destination designated by a branch number field BNO. While a branch address selecting circuit 5 selects the output of the adder/subtractor 4. At the same time, the branching conditions are delivered to a branch condition selecting circuit 9 and compared with the contents of a branch form type instruction field BOP by a comparator 8 to be loaded when the branching conditions are satisfied. In the case of a long-distance branching instruction, the circuit 5 selects the output of a branch address memory 2A.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a control device a that employs a microprogram control method.
The present invention relates to a microprogram branch control system when jumping or branching to an address on a microprogram specified by a microinstruction.

[Conventional technology]

As conventional microprogram branch control systems of this type, there are generally known branching systems using horizontal microprograms and branching systems using vertical microprograms.

The former horizontal branching method has the advantage of high effective speed because calculations, shift functions, etc. and branching functions can be written in one microinstruction, but on the other hand, the bit width of one microinstruction is long and the microprogram The disadvantage is that the memory capacity increases.

In addition, the latter vertical branching method creates separate types of microinstructions for calculations, shift functions, and branching functions, and by limiting the functions that can be described with one instruction, memory usage efficiency is improved and microinstructions are Although it has the advantage of saving program memory capacity, it has the disadvantage of slow effective speed because calculations, shift functions, and branch functions cannot be written in one microinstruction.

Various improved methods have been proposed to take advantage of these advantages and compensate for their drawbacks. Figure 3 shows, for example, JP-A-56
FIG. 2 is an explanatory diagram of a conventional microprogram branch control method disclosed in Japanese Patent No. 201147. In the figure, 1 is a high-speed readable microprogram storage memory in which a microprogram is stored, and 2 is a high-speed readable branch information storage memory.

Furthermore, M in the figure is a field for information that specifies the type of operation, shift operation, register number to be matched, etc., and BSEL is a 1-bit indicating whether the branch control function of this microinstruction is enabled or disabled. Width branch support field, BNO
is a branch number field indicating the type of branch control.

Next, the operation will be explained. For microinstructions that do not require branch control, the BSEL field is written as "invalid". When such an instruction is executed, the next microprogram address is automatically incremented by 1.

For microinstructions that require branch control, the BESE field is written as "valid," and the branch format type BOP, branch condition BCC, and branch destination address BAD are stored in the branch information storage memory 2, and further, Set this storage address to microprogram storage memory 10BNO.
Write in the field.

When the microinstruction is executed, when the BSEL field is "valid", the H
/W (hardware) determines whether the branch condition is met or not, and when the condition is met, the microprogram address written in the BAD field becomes the address of the next instruction.

Therefore, according to this method, instead of a field related to branch information in a microinstruction, a logical number (address of branch information storage memory 2) corresponding to the type of branch information,
Only the branch support field (7 bits) needs to be stored.

Assuming that there are n types of branch information, the width of the branch function description field is n 1 + 1 bits (n = 2),
The address space of microprogram storage memory 1 is set to 2'
In this case, generally n+l(t), and the capacity of the microprogram storage memory 1 can be reduced.

[Problem that the invention seeks to solve]

Since the conventional microprogram branch control system is configured as described above, all combinations of branch formats, branch conditions, and branch destination addresses used in the microprogram are stored in the branch information storage memory 2. Therefore, even if the capacity of the microprogram storage memory 1 is reduced, the capacity of the branch information storage memory 2 increases.

Furthermore, there is a problem that managing the correspondence between all branch instructions and branch information storage addresses becomes complicated.

This invention was made to solve the above-mentioned problems, and aims to provide a microprogram branch control method that can further improve memory usage efficiency without sacrificing the advantages of the horizontal branch method. purpose.

[Means for solving problems]

The microprogram branch control method according to the present invention includes a microprogram storage memory that stores a sequence of microinstructions, a branch address memory that stores an absolute address of a branch destination, and an addition/subtraction operation that calculates a branch destination address from a relative address and an actual row address. and a branch address selection circuit that selects either the output value of the branch address memory or the output value of the adder/subtractor as a branch destination address for performing branch control.

[Effect]

In this invention, an adder/subtractor calculates a branch destination address from the relative address indicated in the branch number field included in the microinstruction string stored in the microprogram storage memory and the actual row address, and the branch address selection circuit calculates the branch destination address using the adder/subtractor. The calculated branch destination address and the output value of the branch address memory are selected, and branch control is performed using the selected value as the branch destination address.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, reference numeral 1 denotes a microprogram storage memory that stores microprograms and can be read at high speed.

An example of the structure of a microinstruction string stored in the microprogram storage memory 1 is shown in FIG. In this Figure 2, M is a field for specifying the operation type, shift operation, target register number, etc., BOP is a branch format type specification field for specifying the type of branch format, and if branching is unnecessary, Write code to indicate this.

Also, BCC is a branch condition specification field, and BTYP is a branch type field, which is a 1-bit field that indicates whether a branch performed by a microinstruction is a short-distance branch or a long-distance branch. '', if "1" is specified for a long-distance branch, if "0" is specified, the next branch number field BNO will be the relative address of the branch destination (
positive or negative), and in case "1" is specified,
This is interpreted as the address of a branch address memory, which will be described later, that stores the absolute address of the branch destination.

The above-mentioned short-distance branch here refers to a branch to a relatively close address that is commonly used, and long-distance branch refers to a branch to a distant address that occurs less frequently. .

The explanation returns to FIG. 1 again. In FIG. 1, C is the branch address memory mentioned above, which stores the absolute address of the branch destination and can be read out at high speed.

Further, 3 is a pipeline register to which the output of microprogram storage memory 1 is set and outputs a control signal specified by the microinstruction, and 4 is a branch target relative address specified by the BNO field and the current execution address. This is an adder/subtractor for calculating an absolute address from .

5 is a branch address selection circuit that selects either the output of the two branch address memories or the output of the adder/subtractor 4 according to the specification of the BTYP field, and 6 is a program counter that indicates the address of the microinstruction to be executed. .

T is a decoder that decodes the control signal output from the pipeline register 3, and 8 is a comparator that compares the output of the decoder 7 and the output of the branch condition selection circuit 9, and determines whether the branch condition is satisfied or not. This is to determine whether the condition holds true.

This branch condition selection circuit 9 is configured to receive signals C1 to Cn indicating the execution state of the control device.

Next, the operation will be explained. In the present invention, the short-distance branch is controlled by specifying a relative address, and the long-distance branch is controlled by referring to the branch address memory.

However, the term "short distance" or "long distance" as used herein differs depending on the system to which this invention is applied, and the most efficient short distance branching range is determined for each system, and the area outside that range is defined as long distance.

Now, if the bit width of the BNO field in Figure 2 is W, then 2 VI types of branch destination absolute addresses can be written in the two branch address memories, and a branch to an address range of ±2 from the branch command is possible. Short-distance branches and other branches are long-distance branches.

For example, address a of microprogram storage memory 1
1 stores a short-distance branch instruction m1 in which the BTYP field is "0" and the BNQ field is r, the execution of this microinstruction is performed as follows.

That is, when the address a1 is set in the program counter 6, the microinstruction m1 of the microprogram storage memory 10 is taken out to the pipeline 3, and control signals according to the contents are output to each part, and the program counter 6 is +1 count up 0 In this case, since the content of the BNO field of microinstruction m1 is r, the adder/subtractor 4 calculates (a1 + 1) + r-
1 is performed, and as a result, the address a1+r appears at the output end of the adder/subtractor 4.

Also, the value of the BTYP field of microinstruction m1 is "0".
”, the branch address selection circuit 5 selects the output of the adder/subtractor 4.

On the other hand, the branch condition selection circuit 9 receives signals C~Cn indicating the execution state of the control device, such as carry of calculation results, and is specified from among these signals by the contents of the branch condition specification field BCC. A predetermined state signal is selected and outputted to the comparator 8.

Further, the content of the branch format type indication field BOP is decoded by the decoder 7, and the signal is compared with the output of the previous branch condition selection circuit 9 by the comparator 8 to determine whether the branch condition is met or not. .

When the branch condition is met, the comparator 8 outputs, for example, rlJ as a load signal for the program counter 6, and the output of the branch address selection circuit 5, that is, the value of a1+r, is loaded into the program counter 6. Therefore, the microinstruction stored at address a 1 +r of microprogram storage memory 1 is executed next.

On the other hand, if the comparator 8 determines that the branch condition is not satisfied, the output of the comparator 8 is "0", so the branch address a 1 + r is not loaded into the program counter 6, and the current program color / 6 , i.e., the address of jL1+1 is executed next.

If a long distance branch instruction m2 in which the BTYP field is "1" and the BNO field is bl is stored at address a2 of the microprogram storage memory 1, this long distance branch instruction m2, that is, the micro The execution of instruction m2 is as follows.

The process until the microinstruction m2 is set in the pipeline register 3 is the same as the execution of the microinstruction m1, but in the case of the microinstruction m2, since the value of the BTYP field is "1", the branch address selection circuit 5 selects the output of two branch address memories.

Here, suppose that data X is stored in advance at address b1 of two branch address memories, and microinstruction m
1, if the branch condition is satisfied and the output of the comparator 8 becomes "1", the program counter 6
is loaded with address X. Therefore, the microinstruction stored at address X in microprogram storage memory 1 is executed next.

Note that in the above embodiment, the branch instruction, that is, the microinstruction m1. m2 indicates the branch relative address and the address of the two branch address memories, and 9 indicates,
In order to shorten the time from when a microinstruction is set in the pipeline register 3 until the next execution address appears at the output end of the program register 6, a branch instruction, that is, immediately before the microinstruction m 1 * m 2 The structure may be such that the values of the BTYP field and the BNO field are written in the instruction to be executed, and the branch destination address is latched in the branch address selection circuit 5.

However, the branch destination relative address at this time must be a relative address to the instruction executed immediately before the branch instruction.

〔Effect of the invention〕

As described above, according to the present invention, the branch destination address is calculated by the adder/subtractor from the relative address indicated in the branch number field and the actual row address, and the calculated branch destination address and the output value of the branch address memory are is selected by the branch address selection circuit, and the selected value is used as the branch destination address. Therefore, branching to the nearest nine addresses, which is relatively frequently used, is performed by specifying a relative address, and branching to a distant address is performed. Branching to can be performed by referring to the branch address memory. Therefore, the microprogram storage memory stores a relative address with a small bit width and the address of the branch address memory, and furthermore, only a decimal branch destination address is stored. It is sufficient to store it in the branch address memory.

This has the effect of further increasing memory usage efficiency without sacrificing the advantages of the branching method using horizontal microprograms.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram of a microprogram branch control system according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the structure of a microinstruction applied to the embodiment, and FIG. FIG. 2 is a block diagram of a conventional microprogram branch control method. 1 is a microprogram storage memory, 2 is a branch address memory, 4 is an adder/subtractor, and 5 is a branch address selection circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation (2 others) Procedural amendment (voluntary)

Claims (1)

[Claims] a microprogram storage memory that stores a microinstruction sequence including a branch type field that indicates whether a branch number field that specifies a branch destination indicates a branch destination relative address or a separately recorded branch destination absolute address; a branch address memory that is accessed using the content of the number field as an address and stores the absolute address of the branch destination; an adder/subtractor that calculates the branch destination address from the relative address indicated in the branch number field and the actual row address; and the branch type A microprogram branch control system comprising a branch address selection circuit that selects either the output value of the branch address memory or the output value of the adder/subtractor as a branch destination address for branch control according to a field value.