JPH0628033B2 - Processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor such as a one-chip signal processor capable of reading and writing a built-in memory with one instruction, and particularly to write control to the memory.

(Prior Art) Conventionally, a one-chip signal processor has a single-chip built-in arithmetic unit that performs arithmetic and logical operations, a control unit that controls the operation of the processor, a storage unit that stores instructions and data, and the like. It is a thing. Here, the arithmetic unit is an arithmetic logic unit (hereinafter referred to as ALU), a multiplier, etc., the control unit is an instruction register, an instruction decoder, etc., and the storage unit is a readable / writable memory (hereinafter referred to as RAM), a read-only memory. (Hereinafter, referred to as ROM) and the like, respectively.

In this type of processor, the internal RAM is read
One instruction is required for each of the operation and the write operation. Therefore, when an arithmetic unit performs an arithmetic operation via the built-in RAM, a read instruction and a write instruction for the built-in RAM are required. Normally, in the one-chip signal processor, the read instruction and the write instruction of the built-in RAM operate in one clock.

(Problems to be Solved by the Invention) However, the processor having the above configuration has the following problems.

Recently, with the progress of digital signal processing technology and the expansion of the application area of the signal processing processor, there is an increasing demand for higher performance and higher functionality of the signal processing processor. One of the demands is a demand to read and write the internal RAM with one instruction (that is, one clock).

There are two methods for adding RAM read / write instructions in terms of instruction system. The first method is a method of adding a read / write command in addition to a read command and a write command of RAM. This method has a problem that the types of instructions are increased and the hardware is increased.

The second method is a method of deleting a RAM read instruction and a write instruction and unifying them into a RAM read / write instruction. In this case, the functions of the RAM read and write instructions are replaced by the RAM read / write instructions. However, when the RAM read function is replaced by the second method, the R
It is necessary to prohibit the writing of AM. In order to realize this, it is necessary to provide a field indicating the write prohibition to the RAM in the read / write instruction of the RAM, but this causes a problem that the hardware becomes large.

The present invention has a problem that the above-mentioned prior art has one instruction (that is, one clock) without increasing the size of hardware.
It is intended to provide a processor which solves the problem that it is difficult to read and write the memory.

(Means for Solving Problems) In order to solve the above problems, the present invention provides an instruction format field that defines an instruction format, a read offset for generating a read address of a memory, and a write address of the memory. Out of one instruction having a write offset that generates a write address, a write address generation circuit that generates a write address signal by operating the instruction format field and write offset, and index data, and an address is specified by the write address signal. And a memory in which data is written to the address, and the following means are provided in the processor that executes the reading and writing of the memory in one clock by the one instruction.

That is, in the present invention, a write prohibition means for decoding the instruction format field and the write offset and generating a write prohibition signal for prohibiting the writing of data to the memory when the write offset shows a specific value. To
It is provided in the write address generation circuit.

(Operation) According to the present invention, since the processor is configured as described above, the write inhibit means generates the write inhibit signal when detecting the specific value of the write offset. This write inhibit signal inhibits writing to the memory, thereby suppressing the increase in size of hardware. Therefore, the above problems can be eliminated.

(Embodiment) FIG. 1 is a main part configuration diagram of a one-chip signal processor according to an embodiment of the present invention, that is, a configuration block diagram of a write address generation circuit.

This write address generation circuit is composed of an instruction register 1 for temporarily storing an instruction read from a ROM (not shown), an AND gate 2 for type identification, a NAND gate 3 as a write prohibiting means for prohibiting writing to an internal RAM, and a write address. Index register 4 for write, and 2 for write address generation
An input 6-bit addition circuit 5 is provided. The AND gate 2 inputs the output signals A30 and A31 of the instruction register 1 and outputs a logical product of them. The NAND gate 3 takes a logical product of the output signals A0 to A29 of the instruction register 1 and the output of the AND gate 2. It is a circuit that outputs a write-inhibit signal S that is its inverted signal. The index register 4 is a circuit for temporarily storing index data, and the adder circuit 5 is a circuit for adding the output signals A0 to A5 of the instruction register 1 and the output of the index register 4 to output write address signals AD1 to AD6. .

Note that, in FIG. 1, main parts such as an arithmetic unit and a storage unit included in a general one-chip signal processor are omitted for convenience of description, but these omitted arithmetic units are the processors of this embodiment. Naturally it is also provided. Here, as in the conventional case, the arithmetic unit is an ALU, a multiplier, etc., the storage unit is a ROM for storing a program instruction given to the instruction register 1, and the RAM is for storing data at an address designated by the write address signals AD1 to AD6. And so on.

FIG. 2 is a diagram showing an instruction configuration example capable of reading and writing the built-in RAM with one instruction (that is, one clock). In Fig. 2, "TYP" is a field that defines the format of the command, "Rad
“D” and “Wadd” are offsets for generating the read address and the write address of the internal RAM, respectively. The read address and write address of the built-in RAM are created by calculating the respective offsets. The write address is created by the write address generation circuit shown in FIG. The read address is created by the read address generation circuit,
This read address generation circuit is composed of, for example, a circuit in which the NAND gate 3 is deleted in the circuit of FIG.

Next, the write operation to the internal RAM will be described.

First, the write address signals AD1 to AD6 of the internal RAM are the memory write offset "Wadd" (= the signal A5 to
It is generated by adding the contents of A0) and the index register 4 in the adder circuit 5. This index register 4 is updated by another means not shown.

Now, when the field "TYP" is 1,1 and the output signals A5, A4, ..., A0 of the instruction register 1 indicate 1, 1, ..., 1,
The write inhibit signal S becomes 0, and writing to the internal RAM is prohibited. Also, the output signals A5, A4,
When A0 is not 1, 1, ..., 1, the write inhibit signal S becomes 1, and writing to the internal RAM is permitted. With such a configuration, it is possible to easily implement write prohibition to the RAM.

The problem here is that the output signal A5 of the instruction register 1
Only when A4, ..., A0 is 1, 1, ..., 1 and it is desired to write data to the RAM. In such cases, the output signal
If A5, A4, A3, A2, A1, A0 are set to 1,1,1,1,1,0 and 1 is added to the contents of the index register 4, the data is written at the same address as the memory address. be able to. However, if the output signals A5 to A0 are all 1 and it is desired to write to the RAM, if the length of the offset "Radd" is sufficiently long, it hardly occurs. In this example, the offset "Radd" has a length of 6 bits and an appearance probability of about 2
Since it is a little less than%, the troublesome operation of adding 1 to the content of the index register 4 is not required so much.

In the recent signal processor, the signals S and AD1 to A
About 10 bits are required for D6. In such a case, the memory address signal is generated by extending the bit width of the index register 4 and the adder 5. The offset "Radd" is sufficient to be 6 bits up to 10 bits for the memory address signal. Therefore, in general, the index register 4 and the adder 5 are necessary regardless of the present embodiment, and the hardware particularly increased in this embodiment is only the NAND gate 3.

The advantages of this embodiment can be summarized as follows.

When reading / writing the internal RAM with one instruction (that is, one clock), write inhibition can be easily controlled by a program instruction. Further, the amount of hardware to be realized is negligible compared to the amount of hardware of the entire one-chip signal processor.

The present invention is not limited to the circuit shown in FIG.
It is also possible to modify the ND gate 3 to another gate circuit, or to modify the number of bits in FIGS. 1 and 2 to increase or decrease. Further, the application area of the present invention is not limited to the one-chip signal processor, and the reading of the memory,
It can be applied to all processors that can execute writing with one instruction.

(Effect of the Invention) As described in detail above, according to the present invention, the write prohibition means for prohibiting the write to the memory when the write offset shows a specific value is provided. The prohibition can be easily controlled by a program command, and the write prohibition means can be realized with a minimum amount of hardware.

[Brief description of drawings]

FIG. 1 is a block diagram of the essential parts of a processor showing an embodiment of the present invention, and FIG. 2 is a command block diagram of FIG. 1 ... Instruction register, 2 ... AND gate, 3 ... NAND gate, 4 ... Index register, 5 ... Adder circuit,
A0 to A31 …… Instruction register output signal, AD1 to AD6 …… Write address signal, S …… Write inhibit signal.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Masao Iida 1-7-12 Toranomon, Minato-ku, Tokyo Inside Oki Electric Industry Co., Ltd. (56) Reference JP-A-53-44131 (JP, A) JP-A-SHO 61-26152 (JP, A)

Claims (1)

[Claims] 1. An instruction format field out of one instruction having an instruction format field defining an instruction format, a read offset for generating a read address of a memory, and a write offset for generating a write address of the memory. A write address generation circuit that calculates a write offset and index data to generate a write address signal; and an address is specified by the write address signal,
A processor for writing data to the address, the processor executing the reading and writing of the memory in one clock by the one instruction, decoding the instruction format field and the writing offset, and writing the offset A processor characterized in that the write address generation circuit is provided with a write inhibit means for generating a write inhibit signal for inhibiting the writing of data to the memory when a specific value is indicated.