JPH0580154B2 - - Google Patents

Info

Publication number
JPH0580154B2
JPH0580154B2 JP62310151A JP31015187A JPH0580154B2 JP H0580154 B2 JPH0580154 B2 JP H0580154B2 JP 62310151 A JP62310151 A JP 62310151A JP 31015187 A JP31015187 A JP 31015187A JP H0580154 B2 JPH0580154 B2 JP H0580154B2
Authority
JP
Japan
Prior art keywords
type
region
forming
transistor formation
mos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62310151A
Other languages
English (en)
Japanese (ja)
Other versions
JPH01150349A (ja
Inventor
Satoshi Shida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP62310151A priority Critical patent/JPH01150349A/ja
Publication of JPH01150349A publication Critical patent/JPH01150349A/ja
Publication of JPH0580154B2 publication Critical patent/JPH0580154B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs

Landscapes

  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP62310151A 1987-12-07 1987-12-07 半導体集積回路装置の製造方法 Granted JPH01150349A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62310151A JPH01150349A (ja) 1987-12-07 1987-12-07 半導体集積回路装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62310151A JPH01150349A (ja) 1987-12-07 1987-12-07 半導体集積回路装置の製造方法

Publications (2)

Publication Number Publication Date
JPH01150349A JPH01150349A (ja) 1989-06-13
JPH0580154B2 true JPH0580154B2 (https=) 1993-11-08

Family

ID=18001776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62310151A Granted JPH01150349A (ja) 1987-12-07 1987-12-07 半導体集積回路装置の製造方法

Country Status (1)

Country Link
JP (1) JPH01150349A (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422508A (en) * 1992-09-21 1995-06-06 Siliconix Incorporated BiCDMOS structure
US5422290A (en) * 1994-02-28 1995-06-06 National Semiconductor Corporation Method of fabricating BiCMOS structures
KR100358571B1 (ko) * 1999-12-31 2002-10-25 주식회사 하이닉스반도체 반도체소자의 제조방법

Also Published As

Publication number Publication date
JPH01150349A (ja) 1989-06-13

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