JPH0579182B2 - - Google Patents

Info

Publication number
JPH0579182B2
JPH0579182B2 JP62176229A JP17622987A JPH0579182B2 JP H0579182 B2 JPH0579182 B2 JP H0579182B2 JP 62176229 A JP62176229 A JP 62176229A JP 17622987 A JP17622987 A JP 17622987A JP H0579182 B2 JPH0579182 B2 JP H0579182B2
Authority
JP
Japan
Prior art keywords
substrate
diffusion layer
mos capacitor
conductivity type
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62176229A
Other languages
Japanese (ja)
Other versions
JPS6420648A (en
Inventor
Tomohisa Mizuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP62176229A priority Critical patent/JPS6420648A/en
Publication of JPS6420648A publication Critical patent/JPS6420648A/en
Publication of JPH0579182B2 publication Critical patent/JPH0579182B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto
    • H10B12/038Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0383Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は、半導体装置およびその製造方法に係
り、特にMOS(絶縁ゲート型)キヤパシタおよび
その形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a MOS (insulated gate type) capacitor and a method for forming the same.

(従来の技術) 一般に、ダイナミツク型半導体メモリに用いら
れるトレンチ構造(溝堀り型)のMOSキヤパシ
タは、従来、第3図に示すように構成されてい
た。即ち、たとえばp型シリコン基板31の表面
に形成されたトレンチ開口部32において、基板
表面にはMOSキヤパシタの電荷蓄積層(以下、
D層と記す)としてn+層33が形成されており、
基板表面上にはMOSキヤパシタの誘電膜となる
ゲート酸化膜34が形成されており、このゲート
酸化膜34上にはMOSキヤパシタの電極(ゲー
ト電極)となるn型不純物が高濃度にドープされ
た多結晶シリコン35が形成されている。
(Prior Art) In general, a trench-structured MOS capacitor used in a dynamic semiconductor memory has conventionally been constructed as shown in FIG. That is, for example, in a trench opening 32 formed on the surface of a p-type silicon substrate 31, a charge storage layer (hereinafter referred to as
An n + layer 33 is formed as a layer D),
A gate oxide film 34 is formed on the substrate surface to serve as a dielectric film of the MOS capacitor, and this gate oxide film 34 is doped with a high concentration of n-type impurity to serve as the electrode (gate electrode) of the MOS capacitor. Polycrystalline silicon 35 is formed.

上記構造のMOSキヤパシタにあつては、微細
化に伴つて、隣りのトレンチキヤパシタ(図示せ
ず)とのパンチスルーを防ぐために、n+層33
をxj(接合深さ)を小さくする必要がある。この
ようにn+層33のxjを小さくしていくにつれて、
n+層33のコーナーエツジ部Aの電界はますま
す大きくなり、かつ平坦部Bの電界よりなり大き
くなる。特に、上記n+層33の形成を、たとえ
ばシリコン基板に対して斜めからAsイオンの注
入により行う場合には、トレンチ底面部での濃度
がトレンチ側面に比べて高くなるので、コーナー
エツジ部Aの電界が大きくなる。従つて、上記
n+層33での接合リーク電流の増大、接合耐圧
の劣化などの問題が生じる。
In the MOS capacitor having the above structure, as miniaturization progresses, in order to prevent punch-through with the adjacent trench capacitor (not shown), the n + layer 3
It is necessary to reduce xj (junction depth). As we reduce xj of the n + layer 33 in this way,
The electric field at the corner edge portion A of the n + layer 33 becomes increasingly large, and becomes much larger than the electric field at the flat portion B. In particular, when the n + layer 33 is formed, for example, by obliquely implanting As ions into the silicon substrate, the concentration at the bottom of the trench is higher than at the side surfaces of the trench, so The electric field increases. Therefore, the above
Problems such as an increase in junction leakage current in the n + layer 33 and deterioration of junction breakdown voltage occur.

なお、上記したようなトレンチ構造のMOSキ
ヤパシタに限らず、平面構造のMOSキヤパシタ
であつても、シリコン基板の表面に1層の拡散層
のみからなるD層を有する場合にも、D層のxjを
小さくしようとするとD層での接合リーク電流の
増大、接合耐圧の劣化が生じるという問題があ
る。
Note that xj of the D layer is not limited to the trench-structured MOS capacitor as described above, but also to a planar-structured MOS capacitor that has a D layer consisting of only one diffusion layer on the surface of the silicon substrate. If an attempt is made to reduce the junction leakage current in the D layer, there is a problem that the junction leakage current increases and the junction breakdown voltage deteriorates.

(発明が解決しようとする問題点) 本発明は、上記したようにMOSキヤパシタの
微細化に伴つて電荷蓄積層の接合深さを小さくす
るにつれて接合リーク電流の増大、接合耐圧の劣
化などが生じるという問題点を解決すべくなされ
たもので、MOSキヤパシタの電荷蓄積層の接合
深さを浅くしても、この層にかかる電界が緩和さ
れ、その接合リーク電流の低減および接合耐圧の
向上を図り得る半導体装置を提供することを目的
とする。
(Problems to be Solved by the Invention) As described above, as the junction depth of the charge storage layer is reduced with the miniaturization of MOS capacitors, junction leakage current increases, junction breakdown voltage deteriorates, etc. This was developed to solve this problem. Even if the junction depth of the charge storage layer of a MOS capacitor is made shallow, the electric field applied to this layer is relaxed, reducing junction leakage current and improving junction breakdown voltage. The purpose of the present invention is to provide a semiconductor device that can be obtained.

また、本発明は、上記MOSキヤパシタを半導
体基板の表面の凹部に形成する際、簡単なプロセ
スで形成することが可能になる半導体装置の製造
方法を提供することを目的とする。
Another object of the present invention is to provide a method for manufacturing a semiconductor device that allows the MOS capacitor to be formed in a concave portion on the surface of a semiconductor substrate through a simple process.

〔発明の構成〕[Structure of the invention]

(問題点を解決するための手段) 本発明の半導体装置は、半導体基板とMOSキ
ヤパシタ誘電膜との界面から半導体基板側に向つ
て半導体基板とは逆導電型で不純物濃度の濃い第
1の拡散層およびこれと同じ導電型であつてそれ
よりも不純物濃度の薄い第2の拡散層と、前記
MOSキヤパシタ誘電膜上に形成された電極層と
が順次形成されてなるMOSキヤパシタが、半導
体基板表面の凹部に形成されてなることを特徴と
する。
(Means for Solving the Problems) The semiconductor device of the present invention has a first diffusion having a conductivity type opposite to that of the semiconductor substrate and having a high impurity concentration from the interface between the semiconductor substrate and the MOS capacitor dielectric film toward the semiconductor substrate side. a second diffusion layer having the same conductivity type and a lower impurity concentration than the second diffusion layer;
MOS capacitor The MOS capacitor is formed by sequentially forming an electrode layer on a dielectric film, and is formed in a recess on the surface of a semiconductor substrate.

また、本発明の半導体装置の製造方法は、半導
体基板内に凹部を形成し、この凹部より基板内
に、この基板と逆導電型の不純物を、前記基板に
対する垂線に対して所定の角度を有する斜め方向
から導入し、前記凹部より基板内に、この基板と
逆導電型の不純物を、前記基板に対する垂線に対
して所定の角度を有する斜め方向から、前記導入
とは異なる条件で導入し、アニール処理し、凹部
表面から順次、基板と逆導電型の第1の拡散層、
基板と逆導電型で第1の拡散層より不純物濃度の
薄い第2の拡散層を形成し、前記第1の拡散層上
にMOSキヤパシタ誘電膜を形成し、前記MOSキ
ヤパシタ誘電膜上に電極層を形成することを特徴
とする。
Further, in the method for manufacturing a semiconductor device of the present invention, a recess is formed in a semiconductor substrate, and an impurity having a conductivity type opposite to that of the substrate is introduced from the recess into the substrate at a predetermined angle with respect to a perpendicular to the substrate. An impurity having a conductivity type opposite to that of the substrate is introduced into the substrate through the recess from an oblique direction at a predetermined angle with respect to the perpendicular to the substrate, and is annealed. a first diffusion layer having a conductivity type opposite to that of the substrate;
forming a second diffusion layer having a conductivity type opposite to that of the substrate and having a lower impurity concentration than the first diffusion layer; forming a MOS capacitor dielectric film on the first diffusion layer; and forming an electrode layer on the MOS capacitor dielectric film. It is characterized by the formation of

(作用) 半導体基板とMOSキヤパシタ誘電膜との界面
から、半導体基板側に向つて順次、基板と逆導電
型の第1の拡散層、基板と逆導電型で、この第1
の拡散層よりも不純物濃度が薄い第2の拡散層を
有することによつて、凹部のコーナーエツジ部で
の電界を緩和できる。従つて、接合リーク電流の
低減、接合耐圧の向上が可能になり、MOSキヤ
パシタの微細化を図ることが可能になる。
(Function) From the interface between the semiconductor substrate and the MOS capacitor dielectric film, a first diffusion layer of a conductivity type opposite to the substrate, a first diffusion layer of a conductivity type opposite to the substrate, and a first diffusion layer of a conductivity type opposite to the substrate,
By providing the second diffusion layer having a lower impurity concentration than the diffusion layer, the electric field at the corner edge portion of the recess can be alleviated. Therefore, it becomes possible to reduce the junction leakage current and improve the junction breakdown voltage, and it becomes possible to miniaturize the MOS capacitor.

また、上記MOSキヤパシタを半導体基板表面
の凹部に形成する際、斜め方向からのイオン注入
により凹部の底面および少なくとも一側面に対し
て同時に前記電荷蓄積層を形成することが可能に
なり、プロセスが簡単である。
Furthermore, when forming the MOS capacitor in a recess on the surface of a semiconductor substrate, the charge storage layer can be simultaneously formed on the bottom and at least one side of the recess by ion implantation from an oblique direction, which simplifies the process. It is.

(実施例) 以下、図面を参照して本発明の一実施例を詳細
に説明する。第1図a乃至cは、半導体集積回
路、たとえばダイナミツク型メモリにおけるメモ
リセルの情報記憶用のトレンチ構造のMOSキヤ
パシタの形成工程におけるウエハ断面構造の一部
を示している。即ち、先ず、第1図aに示すよう
に、p型シリコン基板1上にCVD法(気相成長
法)により所定厚さのSiO2膜を堆積形成する。
次に、このSiO2膜を写真蝕刻法等によりパター
ニングした後、残存したSiO2膜2をマスクとし
てたとえばRIE法(反応性イオンエツチング法)
により異方性エツチングを行つてシリコン基板1
に3μmの深さのトレンチ開口部3を形成する。
その後、第1図bに示すように、シリコン基板1
に対する垂線に対して所定角度+θ、−θ(θはた
とえば7度)を有する斜め上方からたとえばヒ素
イオン(As+)を200KeV(加速電圧)、1×1015
cm-2(ドーズ量)の条件で注入する。このとき、
トレンチ開口部3の底面および側面にイオン注入
が同時に行われる。次に、上記と同様に入射角±
θでたとえばリンイオン(P+)を100KeV(加速
電圧)、1×1013cm-2(ドーズ量)の条件で注入す
る、その後、上記と同様に入射角±θでボロンイ
オン(B+)を150KeV(加速電圧)、1×1013cm-2
の条件で注入する。従つて、イオン注入後のアニ
ール処理によつて、トレンチ開口部3内で基板表
面から基板内部に向つて、基板とは逆導電型で不
純物(As)濃度の濃いn+拡散層4、このn+拡散
層と同じ導電型でこれよりも不純物(P)濃度の濃い
n-拡散層5、基板と同じ導電型で基板よりも不
純物(B)濃度の濃いp-拡散層6の順で三層形成さ
れる。次に、前記CVD法によるSiO2膜2をエツ
チング除去した後、第1図cに示すように、
MOSキヤパシタ用誘電膜となるたとえば100Åの
厚さのSiO2膜7を熱酸化法により形成し、さら
に、その上にMOSキヤパシタ用ゲート電極とな
る不純物がドープされた多結晶シリコン膜8を形
成する。
(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIGS. 1a to 1c show a part of a wafer cross-sectional structure in the process of forming a trench-structured MOS capacitor for storing information in a memory cell in a semiconductor integrated circuit, for example, a dynamic memory. That is, first, as shown in FIG. 1a, a SiO 2 film of a predetermined thickness is deposited on a p-type silicon substrate 1 by CVD (vapor phase growth).
Next, after patterning this SiO 2 film by photolithography or the like, the remaining SiO 2 film 2 is used as a mask to perform etching using, for example, RIE method (reactive ion etching method).
The silicon substrate 1 is etched by anisotropic etching.
A trench opening 3 with a depth of 3 μm is formed.
After that, as shown in FIG. 1b, the silicon substrate 1
For example, arsenic ions (As + ) are irradiated at 200 KeV (acceleration voltage) and 1×10 15 from diagonally above at predetermined angles +θ, -θ (θ is 7 degrees) with respect to the perpendicular to
Inject under the condition of cm -2 (dose amount). At this time,
Ion implantation is performed simultaneously on the bottom and side surfaces of trench opening 3. Next, the incident angle ±
For example, phosphorus ions (P + ) are implanted at θ under the conditions of 100 KeV (acceleration voltage) and 1×10 13 cm -2 (dose amount), and then boron ions (B + ) are implanted at an incident angle of ±θ in the same manner as above. 150KeV (acceleration voltage), 1×10 13 cm -2
Inject under the following conditions. Therefore, by annealing after ion implantation, an n + diffusion layer 4, which has a conductivity type opposite to that of the substrate and has a high concentration of impurity (As), is formed in the trench opening 3 from the substrate surface to the inside of the substrate. + Same conductivity type as the diffusion layer, but higher concentration of impurity (P)
Three layers are formed in this order: an n -diffusion layer 5 and a p -diffusion layer 6, which has the same conductivity type as the substrate and has a higher impurity (B) concentration than the substrate. Next, after etching and removing the SiO 2 film 2 by the CVD method, as shown in FIG.
A SiO 2 film 7 having a thickness of, for example, 100 Å, which will serve as a dielectric film for the MOS capacitor, is formed by thermal oxidation, and a polycrystalline silicon film 8 doped with impurities, which will serve as the gate electrode for the MOS capacitor, is further formed thereon. .

上記したように形成された第1図cに示すトレ
ンチ構造のMOSキヤパシタにおいて、n+拡散層
4はAsイオンの注入により形成され、n-拡散層
5はPイオンの注入により形成されているので、
これらの基板深さ方向に対する不純物濃度のプロ
フアイルはそれぞれ第2図中に示すようになる。
即ち、n+拡散層4の濃度分布は急峻、n-拡散層
5の濃度分布は緩慢であり、D層(電荷蓄積層)
の接合深さxjはn+拡散層4の接合深さに等しく
(浅い)、D層にかかる電界(D層と基板との間の
電界)はn-拡散層5の存在により緩和される。
In the trench-structured MOS capacitor shown in FIG. 1c formed as described above, the n + diffusion layer 4 is formed by implanting As ions, and the n - diffusion layer 5 is formed by implanting P ions. ,
The profiles of impurity concentrations in the substrate depth direction are shown in FIG. 2, respectively.
That is, the concentration distribution of the n + diffusion layer 4 is steep, the concentration distribution of the n - diffusion layer 5 is slow, and the concentration distribution of the D layer (charge storage layer) is
The junction depth xj is equal to (shallow) the junction depth of the n + diffusion layer 4 , and the electric field applied to the D layer (the electric field between the D layer and the substrate) is relaxed by the presence of the n diffusion layer 5 .

従つて、上記構造のMOSキヤパシタによれば、
微細化に伴つて隣りのトレンチ構造のMOSキヤ
パシタ(図示せず)とのパンチスルーを防ぐため
に前記接合深さxjを小さくしても、D層にかかる
電界は小さいので、D層での接合リーク電流が低
減され、接合耐圧が向上する。しかも、D層に隣
接して基板側にp-層6を有するので、隣り合う
トレンチ構造のMOSキヤパシタのD層相互間で
のパンチスルーが防止される。
Therefore, according to the MOS capacitor with the above structure,
Even if the junction depth xj is reduced in order to prevent punch-through with an adjacent trench-structured MOS capacitor (not shown) due to miniaturization, the electric field applied to the D layer is small, so junction leakage in the D layer will occur. Current is reduced and junction breakdown voltage is improved. Furthermore, since the p - layer 6 is provided on the substrate side adjacent to the D layer, punch-through between the D layers of adjacent trench-structured MOS capacitors is prevented.

また、前記したようなトレンチ構造のMOSキ
ヤパシタの形成工程においては、D層形成のため
のイオン注入を行う際、トレンチ開口部3に対し
て斜め上方から異なる条件で連続的にイオン注入
を行うことで、不純物濃度が異なる二層4,5を
トレンチ開口部3の底面および少なくとも一側面
に形成することができる。従つて、簡単なプロセ
スで前記MOSキヤパシタを形成することができ
る。
In addition, in the process of forming the trench-structured MOS capacitor as described above, when performing ion implantation to form the D layer, ion implantation is continuously performed diagonally from above into the trench opening 3 under different conditions. Then, two layers 4 and 5 having different impurity concentrations can be formed on the bottom surface and at least one side surface of the trench opening 3. Therefore, the MOS capacitor can be formed through a simple process.

なお、上記実施例では、各イオンの注入に対し
て、入射角度±θの斜め上方からイオン注入を行
つてトレンチ開口部の各側面に底面と同様の三層
の不純物層を形成したが、入射角度+θまたは−
θのいずれか一方の斜め上方からイオン注入を行
つてトレンチの側面の少なくとも一側面に底面と
同様のn+層、n-層を形成した場合でも上記実施
例と同様の効果が得られる。要は、トレンチ開口
部の少なくとも底面に前記したような2層のD層
を形成しておくことによつて、前述と同様な効果
が得られる。
In the above example, each ion was implanted obliquely from above at an incident angle of ±θ to form a three-layer impurity layer on each side of the trench opening, similar to the bottom surface. Angle +θ or -
Even when ion implantation is performed obliquely above either side of θ to form an n + layer and an n - layer similar to the bottom surface on at least one side surface of the trench, the same effect as in the above embodiment can be obtained. In short, the same effect as described above can be obtained by forming the two D layers described above at least on the bottom surface of the trench opening.

また、前記実施例は、トレンチ構造のMOSキ
ヤパシタについて説明したが、平面構造(プレー
ナ型)のMOSキヤパシタも、そのD層を前記し
たように2層化することによつて前述と同様な効
果が得られる。換言すれば、半導体基板表面の平
坦部または凹部に形成されるMOSキヤパシタを
有する半導体装置に本発明を適用して有効であ
る。
Furthermore, although the above embodiments have been described with respect to a trench-structured MOS capacitor, a planar-structured MOS capacitor can also have the same effect as described above by forming the D layer into two layers as described above. can get. In other words, the present invention is effective when applied to a semiconductor device having a MOS capacitor formed in a flat portion or a concave portion of the surface of a semiconductor substrate.

〔発明の効果〕〔Effect of the invention〕

上述したように本発明は、MOSキヤパシタの
電荷蓄積層の接合深さが浅く、この層にかかる電
界が緩和され、その接合リーク電流の低減および
接合耐圧の向上を図ることができ、MOSキヤパ
シタの微細化に適した半導体装置を提供できると
共に、上記MOSキヤパシタを半導体基板表面の
凹部に簡単なプロセスで形成することが可能な製
造方法を提供できる。
As described above, in the present invention, the junction depth of the charge storage layer of the MOS capacitor is shallow, the electric field applied to this layer is relaxed, and the junction leakage current can be reduced and the junction breakdown voltage can be improved. It is possible to provide a semiconductor device suitable for miniaturization, and also to provide a manufacturing method that allows the MOS capacitor to be formed in a recess on the surface of a semiconductor substrate by a simple process.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a乃至cは本発明の半導体装置の製造方
法の一実施例に係る各工程におけるウエハ断面の
一部を示す図、第2図は第1図c中のn+拡散層、
n-拡散層の基板深さ方向における不純物濃度の
プロフアイルの一例を示す図、第3図は従来のト
レンチ構造のMOSキヤパシタを示す断面図であ
る。 1……p型シリコン基板、3……トレンチ開口
部、4……n+層、5……n-層、6……p-層、7
……キヤパシタ誘電膜、8……キヤパシタ電極。
FIGS. 1a to 1c are views showing a part of a wafer cross section in each step of an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 2 is a diagram showing the n + diffusion layer in FIG. 1c,
FIG . 3 is a cross-sectional view showing a conventional trench-structured MOS capacitor. DESCRIPTION OF SYMBOLS 1...p-type silicon substrate, 3...trench opening, 4...n + layer, 5...n - layer, 6...p - layer, 7
...Capacitor dielectric film, 8...Capacitor electrode.

Claims (1)

【特許請求の範囲】 1 半導体基板とMOSキヤパシタ誘電膜との界
面から半導体基板側に向つて前記半導体基板とは
逆電導型で不純物濃度の濃い第1の拡散層および
これと同じ導電型であつてそれよりも不純物濃度
の薄い第2の拡散層と、前記MOSキヤパシタ誘
電膜上に形成された電極層とが順次形成されてな
るMOSキヤパシタが、半導体基板表面の凹部に
形成されてなることを特徴とする半導体装置。 2 前記第2の拡散層と前記基板との間に、前記
基板と同一導電型で、前記基板よりも不純物濃度
の薄い第3の拡散層が、さらに形成されているこ
とを特徴とする特許請求の範囲第1項記載の半導
体装置。 3 前記MOSキヤパシタは、ダイナミツク型半
導体メモリにおけるメモリセルの情報記憶用のも
のであることを特徴とする特許請求の範囲第1項
および第2項いずれか1項記載の半導体装置。 4 半導体基板内に凹部を形成する工程と、前記
凹部より前記基板内に、この基板と逆導電型の不
純物を、前記基板に対する垂線に対して所定の角
度を有する斜め方向から導入する第1の工程と、 前記凹部より前記基板内に、この基板と逆導電
型の不純物を、前記基板に対する垂線に対して所
定の角度を有する斜め方向から、前記第1の工程
とは異なる条件で導入する第2の工程と、 アニール処理し、凹部表面から順次、前記基板
と逆導電型の第1の拡散層、前記基板と逆導電型
で前記第1の拡散層より不純物濃度の薄い第2の
拡散層を形成する工程と、 前記第1の拡散層上にMOSキヤパシタ誘電膜
を形成する工程と、 前記MOSキヤパシタ誘電膜上に電極層を形成
する工程と、 を具備することを特徴とする半導体装置の製造方
法。 5 前記凹部より前記基板内に、この基板と同一
導電型の不純物を、前記基板に対する垂線に対し
て所定の角度を有する斜め方向から導入する第3
の工程を、さらに具備することを特徴とする特許
請求の範囲第4項記載の半導体装置の製造方法。
[Scope of Claims] 1. A first diffusion layer having a high impurity concentration and having a conductivity type opposite to that of the semiconductor substrate from the interface between the semiconductor substrate and the MOS capacitor dielectric film and a first diffusion layer having a high impurity concentration and having the same conductivity type as the semiconductor substrate. A MOS capacitor, in which a second diffusion layer having a lower impurity concentration and an electrode layer formed on the MOS capacitor dielectric film are formed in sequence, is formed in a recess on the surface of a semiconductor substrate. Characteristic semiconductor devices. 2. A patent claim characterized in that a third diffusion layer is further formed between the second diffusion layer and the substrate, the third diffusion layer having the same conductivity type as the substrate and having a lower impurity concentration than the substrate. The semiconductor device according to item 1. 3. The semiconductor device according to claim 1 or 2, wherein the MOS capacitor is for storing information in a memory cell in a dynamic semiconductor memory. 4. A step of forming a recess in a semiconductor substrate, and a first step of introducing an impurity of a conductivity type opposite to that of the substrate into the substrate from the recess from an oblique direction having a predetermined angle with respect to a perpendicular to the substrate. a step of introducing an impurity of a conductivity type opposite to that of the substrate into the substrate through the recess from an oblique direction having a predetermined angle with respect to a perpendicular to the substrate under conditions different from those in the first step; Step 2: Annealing and sequentially forming a first diffusion layer having a conductivity type opposite to that of the substrate from the surface of the recess, and a second diffusion layer having a conductivity type opposite to the substrate and having an impurity concentration lower than that of the first diffusion layer. a step of forming a MOS capacitor dielectric film on the first diffusion layer; and a step of forming an electrode layer on the MOS capacitor dielectric film. Production method. 5. A third step of introducing an impurity of the same conductivity type as the substrate into the substrate from the recess from an oblique direction having a predetermined angle with respect to a perpendicular to the substrate.
5. The method of manufacturing a semiconductor device according to claim 4, further comprising the step of:
JP62176229A 1987-07-15 1987-07-15 Semiconductor device and manufacture thereof Granted JPS6420648A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62176229A JPS6420648A (en) 1987-07-15 1987-07-15 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62176229A JPS6420648A (en) 1987-07-15 1987-07-15 Semiconductor device and manufacture thereof

Publications (2)

Publication Number Publication Date
JPS6420648A JPS6420648A (en) 1989-01-24
JPH0579182B2 true JPH0579182B2 (en) 1993-11-01

Family

ID=16009890

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62176229A Granted JPS6420648A (en) 1987-07-15 1987-07-15 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6420648A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53145577A (en) * 1977-05-25 1978-12-18 Hitachi Ltd Production of semiconductor rectifier
JPS5524411A (en) * 1978-08-09 1980-02-21 Hitachi Ltd Process of manufacturing semiconductor rectifying device
JPS61119075A (en) * 1984-11-15 1986-06-06 Nec Corp Manufacture of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53145577A (en) * 1977-05-25 1978-12-18 Hitachi Ltd Production of semiconductor rectifier
JPS5524411A (en) * 1978-08-09 1980-02-21 Hitachi Ltd Process of manufacturing semiconductor rectifying device
JPS61119075A (en) * 1984-11-15 1986-06-06 Nec Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS6420648A (en) 1989-01-24

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