JPH056805A - Chip-type varistor - Google Patents

Abstract

PURPOSE:To provide a chip-type varistor which can have a glass film of the uniform thickness formed on the surface of a ceramic body that prevents the glass film from being diffused into an internal electrode for avoiding the deterioration in electric characteristic. CONSTITUTION:The plurality of internal electrodes 3 are buried in a ceramic body 2 and one end face 3a of each internal electrode 3 is connected to an internal electrode 4 which is formed on left and right end faces 2a, 2b of the ceramic body 2. Then, the outer surface of the ceramic body 2 is coated with a glass film 6. Thus, a chip-type varistor 1 is fabricated. Between the surface of the ceramic body 2 and the internal electrode 3, a free electrode 7 not connected to the external electrode 4 is installed. An area of the free electrode 7 is made larger than that of a characteristic part A of the internal electrode 3 so that the free electrode 7 may cover the characteristic part A. For the free electrode 7, a silver-palladium alloy or platinum is employed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type varistor functioning as a voltage non-linear resistor, and particularly when a glass film is coated on the surface of a sintered body, the film thickness of the glass film can be made uniform. At the same time, it relates to a structure capable of suppressing the diffusion to the internal electrodes and preventing the deterioration of the electrical characteristics.

[0002]

2. Description of the Related Art In recent years, miniaturization and integration have rapidly progressed in the field of electronic equipment adopted for communication devices and the like. Also,
There is a demand for a reduction in withstand voltage due to higher density of ICs, and along with this, protection elements and circuit designs are required to prevent destruction and malfunction of IC circuits due to intrusion of high-voltage noise. . As such a protection element, a varistor having a voltage non-linear characteristic is adopted. In order to apply this varistor to an IC circuit, conditions such as low suppression voltage, small electrostatic capacitance, and small size are required. However, the above varistor has a problem that the varistor voltage must be lowered in order to reduce the suppression voltage, so that the capacitance becomes large. Further, the capacitance can be reduced by reducing the electrode area, but this causes a problem that the surge resistance is reduced. Conventionally, a multilayer chip varistor has been proposed as a device that can be made compact while reducing the suppression voltage and the electrostatic capacitance (for example, Japanese Patent Publication No. S58).
-23921). In this laminated varistor, semiconductor ceramic layers and internal electrodes are alternately laminated and integrally sintered, one end surface of the internal electrode is exposed at both end surfaces of the sintered body, and the internal electrode of the internal electrode is exposed at both end surfaces. An external electrode connected to one end face is formed. By the way, although the chip varistor is useful as a noise absorbing element,
When the size of the varistor element is reduced, there is a problem that a leak current due to a surface current or a surface discharge is likely to occur. Further, since Ag is used for the external electrodes, there is a problem that solder erosion is likely to occur during surface mounting by soldering. In order to avoid such leakage current and solder erosion, it is effective to coat the outer surface of the sintered body excluding the external electrodes with a glass film to insulate it. As a method of coating the glass film, a method of baking the glass at a temperature of 400 to 900 ° C. and diffusing the glass on the surface portion of the sintered body has been conventionally used. By forming this glass film, the leakage current can be suppressed, and the surface of the external electrode can be coated with a plating film by electrolytic plating to prevent solder leaching. Here, when the external electrodes are coated with a plating film, since the sintered body is a semiconductor, if the surface of the sintered body is not reliably insulated, the plating will grow over the entire surface and short-circuit will occur. Or the effect of suppressing leakage current may be reduced. Therefore, the glass film needs to have a certain thickness, and it is necessary to make the thickness uniform.
Therefore, the baking temperature of the glass is set high to increase the surface diffusion.

[0003]

However, in the above-mentioned conventional chip varistor, when the baking temperature of the glass is increased, the grain boundary diffusion of the glass may be activated and the glass may reach the internal electrode, resulting in the varistor voltage. However, there is a problem that the suppression voltage increases, which adversely affects the varistor characteristics. Here, it is possible to delicately control the amount of glass and the baking temperature in order to avoid the diffusion to the internal electrodes while making the thickness of the glass film uniform. However, this control is very difficult and is difficult at present. The present invention has been made in view of the above conventional circumstances, when forming a glass film on the surface of the sintered body, it is possible to make the film thickness uniform while eliminating the need for delicate control of the baking temperature, and to the internal electrode It is an object of the present invention to provide a chip-type varistor capable of suppressing the diffusion of varistor and preventing an adverse effect on varistor characteristics.

[0004]

Therefore, the invention of claim 1 is to embed a plurality of internal electrodes inside a sintered body, and connect the internal electrodes to external electrodes formed on both end surfaces of the sintered body. In addition, in a chip type varistor formed by coating a glass film on the outer surface of the sintered body, a free electrode that is not connected to the external electrode is provided between the surface portion of the sintered body and the internal electrode. It is characterized by that. Further, the invention of claim 2 is characterized in that the free electrode is larger than the area of the characteristic portion of the internal electrode and covers the characteristic portion. Further, in the invention of claim 3, the free electrode is Ag-P.
It is characterized by being made of d alloy or Pt.

[0005]

According to the chip type varistor of the first aspect of the invention, since the free electrode is provided between the surface portion of the sintered body and the internal electrode, the free electrode suppresses the diffusion of the glass into the interior. Therefore, even if the baking temperature is set high, the diffusion to the internal electrodes can be reduced and the deterioration of the varistor characteristics can be avoided. As a result, it is possible to form a glass film having a large film thickness and a uniform thickness without requiring a fine control of the baking temperature, and it is possible to improve the insulating property. Further, in the invention of claim 2, since the area of the free electrode is larger than the area of the characteristic portion of the internal electrode, the diffusion of the glass into the internal electrode can be more reliably suppressed. Further, in the invention of claim 3, since the silver / palladium alloy and platinum are used for the free electrode, the effect of suppressing the diffusion of glass can be improved.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 4 are views for explaining a chip type varistor according to an embodiment of the present invention. In the figure, reference numeral 1 is a chip-type varistor of the present embodiment, which is a pair of internal electrodes 3 and 3 made of an Ag-Pd alloy inside a rectangular parallelepiped sintered body 2 made of semiconductor ceramics containing ZnO as a main component. And the left and right end faces 2 of the sintered body 2
The external electrodes 4 made of Ag are formed on a and 2b. One end surface 3a of each internal electrode 3 has the sintered body 2
Are alternately exposed on the left and right end faces 2a and 2b of the above and are connected to the external electrode 4, and the other end faces are enclosed in the sintered body 2. The outer surface of the external electrode 4 is covered with a Ni plating film 8 by electrolytic plating.

The portion of the ceramic layer 5a sandwiched between the internal electrodes 3 of the sintered body 2 is a characteristic portion A which exhibits a voltage non-linear characteristic, and the characteristic portion A is a characteristic portion A of the internal electrodes 3. It is the opposite surface. The portions of the sintered body 2 other than the ceramics layer 5a are dummy ceramics layers 5b and 5c.

Further, a glass film 6 is formed on the outer surface of the sintered body 2, and the glass film 6 is diffused to the surface portion of the sintered body 2 by baking lead borosilicate glass powder at a high temperature. It is formed by doing so.

A free electrode 7 made of an Ag--Pd alloy which is not connected to the external electrode 4 is provided in the ceramic layers 5b and 5c between the internal electrode 3 and the surface of the sintered body 2. The free electrode 7 is enclosed in the sintered body 2. The free electrode 7 is set larger than the area of the characteristic portion A of the internal electrode 3 and covers the characteristic portion A. The free electrode 7 suppresses diffusion into the glass layer 7.

Next, a method of manufacturing the chip varistor 1 of this embodiment will be described. First, as a ceramic raw material, ZnO, Bi ₂ O ₃ , CoCO ₃ , with a purity of 99% or more,
98 mol% and 0.5 mol of MnO ₂ and Sb ₂ O ₃ , respectively
%, 0.5 mol%, 0.5 mol%, 0.5 mol% are weighed, and pure water is added to this and mixed by a ball mill for 24 hours to form a slurry. Next, the slurry is filtered, dried, granulated, and then calcined at a temperature of 800 ° C. for 2 hours. After that, the calcined product is roughly pulverized by a pulverizer, pure water is added to the pulverized product, and the mixture is finely pulverized by a vol mill, filtered and dried, and then dispersed in a solvent together with an organic binder to form a slurry. A green sheet having a thickness of 50 μm is formed from this slurry by a doctor blade method, and the green sheet is punched out into a predetermined size to form a large number of ceramic sheets. As a result, the ceramics layer 5a that exhibits the voltage non-linear characteristic and the ceramics layers 5b and 5c as dummy are formed.

Next, a conductive paste made of Ag-Pd alloy (ratio of 7: 3) is prepared, and the paste is screen-printed on the upper surfaces of the ceramic layers 5a and 5c to form the internal electrodes 3. In this case, only one end surface 3a of the internal electrode 3 is located at the outer edge of the ceramic layers 5a and 5c, and the remaining end surfaces are located inside the ceramic layers 5a and 5c. Further, a conductive paste is similarly printed on the upper surfaces of the other ceramic layers 5b and 5c to form the free electrode 7. The free electrode 7 is formed such that all of its end faces are located inside the peripheral edges of the ceramic layers 5b and 5c and are larger than the area of the characteristic portion A of the internal electrode 3.

Next, as shown in FIG. 4, each internal electrode 3
So as to face each other with the ceramics layer 5a sandwiched therebetween, and the one end faces 3a of the respective internal electrodes 3 are alternately arranged on the left and right sides, and the ceramics layer 5b having no printing on the upper surface and the lower surface thereof. Stack 2 pieces of 5c. Further, the ceramic layers 5b and 5c on which the free electrodes 7 are formed are stacked on the upper and lower surfaces thereof, and two ceramic layers 5b and 5c on which nothing is printed are stacked. Next, a pressure of ² t / cm ² is applied in the stacking direction to perform pressure bonding, thereby forming a stack. After that, the laminated body is cut into a predetermined size, heated at a temperature of 500 ° C. for 2 hours to remove the binder, and then heated to 950 ° C. and baked for 2 hours to obtain a sintered body 2. .

The sintered body 2 thus obtained is placed in an alumina porcelain pot, and 1 wt% of the total weight of the sintered body is added with lead borosilicate glass powder. Then, while rotating the porcelain pot, 700
Heat to ~ 900 ° C. Then, the glass powder is sintered body 2
Of the glass film 6 is diffused to form the glass film 6. In this case, the glass powder is prevented from diffusing inside by the free electrode 8 and is suppressed from permeating into the internal electrode 3, and the glass film 6 having a uniform thickness is formed on the surface portion of the sintered body 2. To be done.

Next, after the Ag paste is applied to the left and right end faces 2a and 2b of the sintered body 2 where one end face 3a of the internal electrode 3 is exposed, the external electrode 4 is heated at 800 ° C. for 10 minutes. To form. Then, the sintered body 2 is electroplated to form a Ni plating film 8 on the outer surface of the external electrode 4. In this case, since the portion of the sintered body 2 other than the external electrode 4 is covered with the glass film 6, plating does not adhere. As a result, the chip type varistor 1 of this embodiment is manufactured.

As described above, according to this embodiment, the free electrode 7 is disposed between the surface of the sintered body 2 and the internal electrode 3, and the free electrode 7 covers the characteristic portion A of the internal electrode 3. So
The diffusion of the glass can be suppressed by the free electrode 7, the diffusion to the internal electrode 3 can be reduced, and the increase of the limiting voltage and the varistor voltage can be avoided. Further, since the baking temperature can be increased, the tension of the molten glass can be reduced, the wettability to the element can be improved, and the thick and uniform glass film 6 can be formed. Leakage current can be reduced without impairing the voltage suppression effect, and solder leaching during soldering can be prevented. In the above embodiment, the structure in which the pair of internal electrodes 3 are embedded in the sintered body 2 has been described as an example, but the present invention is not limited to this, and a structure in which a large number of internal electrodes are embedded is provided. Can also be applied to.

[0016]

[Table 1]

Table 1 shows the results of tests conducted to confirm the effect of the chip type varistor of this embodiment. In this test, a large number of chip type varistors were created by the manufacturing method of the above-mentioned embodiment, and the varistor voltage, nonlinear coefficient, capacitance, electrostatic loss, The limiting voltage ratio, soldering process change rate, varistor voltage after plating, and surge change rate were measured. Further, the free electrode is, as shown in FIG.
For the characteristic area t1 × t2 of the internal electrode (see FIG. 5 (c)), the area of the free electrode is t1 + Δt, t2 + Δt (0
Up to 0.4 mm) (see FIG. 5 (a)), the free electrode area is t1-Δt, t2-Δt.
It was performed when the size was reduced within the range of (0.1 to 0.2 mm) (see Fig. 5 (b)). Here, the rate of change in the soldering process was measured using a pine resin for each sample after the external electrodes were formed.
It was immersed in a 4 × 6 solder bath at 860 ° C. for 5 seconds, washed with trichloroethane for 60 seconds, and allowed to stand for 1 hour for measurement. The limiting voltage ratio is the ratio of the output voltage / varistor voltage when a triangular current wave of 8 × 20 μsec is applied, and the surge change rate is the varistor voltage / application when left for 1 hour after applying the above triangular current wave. This is the change rate of the front varistor voltage. In addition,
For comparison, the same measurement was performed for a conventional chip varistor without a free electrode. As is clear from Table 1, conventional samples without free electrodes (No. 1 to 6)
Then, if the glass baking temperature is as low as 700-800 ℃,
Although the varistor voltage and the nonlinear coefficient are satisfactory, the dielectric loss and the rate of change in soldering are low, and the plating process adheres to the entire surface of the sintered body and causes a short circuit, resulting in an uneven glass film thickness. Has become. Further, when the baking temperature is as high as 850 ° C. or higher, the glass film is uniform, but the varistor voltage and the nonlinear coefficient are deteriorated, and the glass diffuses to the internal electrodes. on the other hand,
If the area of the free electrode is smaller than the characteristic part of the internal electrode (Sample Nos. 7, 8, 13, 14), the varistor voltage and the specific linear coefficient are determined because the glass wraps around the free electrode and diffuses inside. The characteristics are slightly less effective.
On the other hand, when the area of the free electrode is larger than that of the characteristic portion (Sample Nos. 9 to 12 and 15 to 20), the characteristics of the varistor voltage, the nonlinear coefficient, the dielectric loss, and the limiting voltage ratio are impaired. Satisfactory characteristics are obtained in all of the soldering process change rate, the varistor voltage after plating, and the surge change rate.

[0018]

[Table 2]

[0019]

[Table 3]

Tables 2 and 3 show the conventional samples (Nos. 2 to 6) used in the above test, which are not provided with the free electrode, and the samples of the present embodiment (Nos. 11 and 17) which are provided with the free electrode. )
Shows the result of cross-section polishing of each sample, and the diffusion distance of the glass of this sample was investigated by an X-ray microanalyzer (energy dispersion type). For this, as shown in FIG. 2, the diffusion distance of the sintered body 2 in the laminating direction x-axis and the diffusion distance in the y-axis orthogonal to the laminating direction were measured. In each sample, the distance from the surface of the sintered body 2 to the free electrode 7 is 100 μm, and the distance from the free electrode to the internal electrode is 100 μm.
The distance from the side end face of the sintered body to the side end face of the internal electrode was 400 μm. As is clear from each table, in the conventional sample without a free electrode, the glass reaches the characteristic part of the internal electrode when the baking temperature required for insulation is 850 ° C. On the other hand, in the sample of this example, even if the baking temperature was raised to 900 ° C., the glass did not reach the internal electrode, and it can be seen that the free electrode suppressed the diffusion of the glass into the inside.

[0021]

As described above, according to the chip type varistor according to the present invention, the free electrode which is not connected to the external electrode is disposed between the surface portion of the sintered body and the internal electrode. When forming a glass film on the surface, there is an effect that the film thickness can be made uniform without the need for delicate control of the baking temperature, and diffusion to the internal electrodes can be suppressed to prevent adverse effects on varistor characteristics.

[Brief description of drawings]

1 is a cross-sectional view taken along the line I-I of FIG. 3 for explaining a chip type varistor according to an embodiment of the present invention.

FIG. 2 II-II of FIG. 3 of the chip type varistor of the above embodiment.
It is a line sectional view.

FIG. 3 is a perspective view of the chip type varistor of the above embodiment.

FIG. 4 is an exploded perspective view of the chip type varistor of the above embodiment.

FIG. 5 is a plan view of a free electrode and an internal electrode for explaining a test method performed for confirming the effect of the above-mentioned embodiment.

[Explanation of symbols]

1 chip type varistor 2 Sintered body 2a, 2b Left and right end faces of the sintered body 3 internal electrodes 3a One end surface of internal electrode 4 external electrodes 6 glass film 7 Free electrode A characteristic section

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yasunobu Yoneda             Stock number 2 26-10 Tenjin, Nagaokakyo-shi, Kyoto             Murata Manufacturing Co., Ltd.

Claims (3)

[Claims] 1. A plurality of internal electrodes are embedded inside a ceramic sintered body, one end surface of the internal electrode is connected to an external electrode formed on an end surface of the sintered body, and the other side of the sintered body is connected. A chip-type varistor having a surface coated with a glass film, wherein a free electrode which is not connected to the external electrode is arranged between the surface portion of the sintered body and the internal electrode. 2. The free electrode according to claim 1,
A chip-type varistor which is larger than the area of a characteristic portion that exhibits a linear characteristic of voltage ratio in an internal electrode and covers the characteristic portion. 3. The chip type varistor according to claim 1, wherein the free electrode is made of a silver-palladium alloy or platinum.