JPH0567645A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0567645A
JPH0567645A JP3230018A JP23001891A JPH0567645A JP H0567645 A JPH0567645 A JP H0567645A JP 3230018 A JP3230018 A JP 3230018A JP 23001891 A JP23001891 A JP 23001891A JP H0567645 A JPH0567645 A JP H0567645A
Authority
JP
Japan
Prior art keywords
layer
wiring layer
semiconductor device
bonding pad
window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3230018A
Other languages
Japanese (ja)
Inventor
Katsuhiko Oimura
克彦 老邑
Akio Kashiwakura
明男 柏倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP3230018A priority Critical patent/JPH0567645A/en
Publication of JPH0567645A publication Critical patent/JPH0567645A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a semiconductor device which can increase integration degree. CONSTITUTION:A first wiring layer 3 and a second wiring layer 5 are connected to each other through a through hole 9 provided in the region excluding the lower region of a bonding pad window 7 and the lower sectional constitution of the window 7 is formed into a constitution consisting of a semiconductor substrate 1, a first insulating later 2, the layer 3, a second insulating layer 4 and the layer 5 formed in order from the lower part. As the lower part of the window 7 has the layer 4, the layer 2 can be prevented from being broken by impact when a wire 8 is bonded. As a result, an element, such as a resistor, can be formed in the lower part of the window 7 and the integration degree of a semiconductor device can be increased.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は、集積回路などの半導
体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an integrated circuit.

【０００２】[0002]

【従来の技術】近年、集積回路では、集積度を上げるた
めに、２層配線を用いることが一般的であった。従来の
２層配線を用いた半導体装置のボンディングパッド部の
断面を図２に示す。図２において、１は半導体基板、２
は第１絶縁層、３は第１配線層、４は第２絶縁層、５は
第２配線層、６は保護膜、７はボンディングパッド窓、
８はワイヤ、１０は第１配線層３と第２配線層５を接続
するためのスルーホールである。2. Description of the Related Art In recent years, it has been common in integrated circuits to use two-layer wiring in order to increase the degree of integration. FIG. 2 shows a cross section of a bonding pad portion of a conventional semiconductor device using a two-layer wiring. In FIG. 2, 1 is a semiconductor substrate, 2
Is a first insulating layer, 3 is a first wiring layer, 4 is a second insulating layer, 5 is a second wiring layer, 6 is a protective film, 7 is a bonding pad window,
Reference numeral 8 is a wire, and 10 is a through hole for connecting the first wiring layer 3 and the second wiring layer 5.

【０００３】この従来の半導体装置では、ボンディング
パッド窓７の下部にスルーホール１０を形成し、第１配
線層３と第２配線層５を接続している。In this conventional semiconductor device, a through hole 10 is formed below the bonding pad window 7 to connect the first wiring layer 3 and the second wiring layer 5.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら上記従来
の構成では、第２配線層５にワイヤ８をボンディングす
るときの衝撃で第１絶縁層２が破壊されやすいため、集
積回路の集積度を高くすることができなかった。すなわ
ち、第１絶縁層２が破壊されると第１配線層３と半導体
基板１がショート状態になってしまうため、ボンディン
グパッド窓７の下部に抵抗などの素子を形成できないの
である。However, in the above conventional structure, the first insulating layer 2 is easily broken by the impact when the wire 8 is bonded to the second wiring layer 5, so that the degree of integration of the integrated circuit is increased. I couldn't. That is, when the first insulating layer 2 is destroyed, the first wiring layer 3 and the semiconductor substrate 1 are short-circuited, so that an element such as a resistor cannot be formed below the bonding pad window 7.

【０００５】この発明は上記課題を解決するもので、集
積度を高めることのできる半導体装置を提供することを
目的とする。The present invention solves the above problems, and an object of the present invention is to provide a semiconductor device capable of increasing the degree of integration.

【０００６】[0006]

【課題を解決するための手段】上記目的を達成するため
にこの発明の半導体装置は、第１配線層と第２配線層を
接続するためのスルーホールをボンディングパッド窓の
下部領域を除く領域に設けたことを特徴とする。In order to achieve the above object, a semiconductor device of the present invention has a through hole for connecting a first wiring layer and a second wiring layer in a region excluding a lower region of a bonding pad window. It is characterized by being provided.

【０００７】[0007]

【作用】この発明の構成によれば、スルーホールをボン
ディングパッド窓の下部領域を除く領域に設けたことに
より、ボンディングパッド窓の下部領域には第２絶縁層
を有し、ボンディングの衝撃により第１絶縁層が破壊さ
れるのを防止できる。According to the structure of the present invention, since the through hole is provided in the region excluding the lower region of the bonding pad window, the second insulating layer is provided in the lower region of the bonding pad window, and the second insulating layer is provided by the impact of bonding. (1) It is possible to prevent the insulating layer from being destroyed.

【０００８】[0008]

【実施例】以下、この発明の一実施例について、図１を
参照しながら説明する。図１はこの発明の一実施例の半
導体装置のボンディングパッド部の断面図である。な
お、図１において図２と対応する部分には同一の符号を
付してある。この半導体装置において、第１配線層３と
第２配線層５は、ボンディングパッド窓７の下部領域を
除く領域に設けたスルーホール９で接続してあるため、
ボンディングパッド窓７の下部の断面構成は、下から順
に半導体基板１，第１絶縁層２，第１配線層３，第２絶
縁層４，第２配線層５となっている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a sectional view of a bonding pad portion of a semiconductor device according to an embodiment of the present invention. Note that, in FIG. 1, portions corresponding to those in FIG. 2 are denoted by the same reference numerals. In this semiconductor device, the first wiring layer 3 and the second wiring layer 5 are connected by the through hole 9 provided in the region excluding the lower region of the bonding pad window 7,
The cross-sectional structure of the lower portion of the bonding pad window 7 is a semiconductor substrate 1, a first insulating layer 2, a first wiring layer 3, a second insulating layer 4, and a second wiring layer 5 in order from the bottom.

【０００９】このように、ディングパッド窓７の下部に
第２絶縁層４を有するため、ワイヤ８をボンディングす
るときの衝撃により第１絶縁層２が破壊されるのを防止
できる。このため、ボンディングパッド窓７の下部に抵
抗などの素子を形成することができ、集積度を高めるこ
とができる。As described above, since the second insulating layer 4 is provided under the padding window 7, it is possible to prevent the first insulating layer 2 from being destroyed by the impact when the wire 8 is bonded. Therefore, an element such as a resistor can be formed below the bonding pad window 7, and the degree of integration can be increased.

【００１０】[0010]

【発明の効果】この発明の半導体装置は、第１配線層と
第２配線層を接続するためのスルーホールをボンディン
グパッド窓の下部領域を除く領域に設けたことにより、
ボンディングパッド窓の下部領域には第２絶縁層を有
し、ボンディングの衝撃により第１絶縁層が破壊される
のを防止できるため、ボンディングパッド窓の下部に抵
抗などの素子を形成することができ、集積度を高めるこ
とができる。According to the semiconductor device of the present invention, the through hole for connecting the first wiring layer and the second wiring layer is provided in the region excluding the lower region of the bonding pad window.
Since the second insulating layer is provided in the lower region of the bonding pad window to prevent the first insulating layer from being destroyed by the impact of bonding, a device such as a resistor can be formed under the bonding pad window. , The degree of integration can be increased.

【図面の簡単な説明】[Brief description of drawings]

【図１】この発明の一実施例の半導体装置のボンディン
グパッド部の断面図である。FIG. 1 is a sectional view of a bonding pad portion of a semiconductor device according to an embodiment of the present invention.

【図２】従来の半導体装置のボンディングパッド部の断
面図である。FIG. 2 is a sectional view of a bonding pad portion of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ 半導体基板 ２ 第１絶縁層 ３ 第１配線層 ４ 第２絶縁層 ５ 第２配線層 ７ ボンディングパッド窓 ８ ワイヤ ９ スルーホール 1 Semiconductor Substrate 2 First Insulating Layer 3 First Wiring Layer 4 Second Insulating Layer 5 Second Wiring Layer 7 Bonding Pad Window 8 Wire 9 Through Hole

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体基板上に第１絶縁層，第１配線
層，第２絶縁層および第２配線層が順次形成され、前記
第２配線層にワイヤがボンディングされた半導体装置で
あって、 前記第１配線層と前記第２配線層を接続するためのスル
ーホールをボンディングパッド窓の下部領域を除く領域
に設けたことを特徴とする半導体装置。1. A semiconductor device in which a first insulating layer, a first wiring layer, a second insulating layer and a second wiring layer are sequentially formed on a semiconductor substrate, and a wire is bonded to the second wiring layer, A semiconductor device, wherein a through hole for connecting the first wiring layer and the second wiring layer is provided in a region excluding a lower region of a bonding pad window.
JP3230018A 1991-09-10 1991-09-10 Semiconductor device Pending JPH0567645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3230018A JPH0567645A (en) 1991-09-10 1991-09-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3230018A JPH0567645A (en) 1991-09-10 1991-09-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0567645A true JPH0567645A (en) 1993-03-19

Family

ID=16901286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3230018A Pending JPH0567645A (en) 1991-09-10 1991-09-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0567645A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000049190A (en) * 1998-07-14 2000-02-18 Texas Instr Inc <Ti> System and method for making bonding on active integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000049190A (en) * 1998-07-14 2000-02-18 Texas Instr Inc <Ti> System and method for making bonding on active integrated circuit

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