JPH056706B2 - - Google Patents

Info

Publication number
JPH056706B2
JPH056706B2 JP56162691A JP16269181A JPH056706B2 JP H056706 B2 JPH056706 B2 JP H056706B2 JP 56162691 A JP56162691 A JP 56162691A JP 16269181 A JP16269181 A JP 16269181A JP H056706 B2 JPH056706 B2 JP H056706B2
Authority
JP
Japan
Prior art keywords
address
data
access
bus
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56162691A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5864689A (ja
Inventor
Tadaaki Bando
Yasushi Fukunaga
Yoshinari Hiraoka
Hidekazu Matsumoto
Tetsuya Kawakami
Takeshi Kato
Toshuki Ide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Industry and Control Solutions Co Ltd
Original Assignee
Hitachi Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd
Priority to JP56162691A priority Critical patent/JPS5864689A/ja
Publication of JPS5864689A publication Critical patent/JPS5864689A/ja
Publication of JPH056706B2 publication Critical patent/JPH056706B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284Multiple user address space allocation, e.g. using different base addresses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP56162691A 1981-10-14 1981-10-14 デ−タ処理装置 Granted JPS5864689A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56162691A JPS5864689A (ja) 1981-10-14 1981-10-14 デ−タ処理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56162691A JPS5864689A (ja) 1981-10-14 1981-10-14 デ−タ処理装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP4027794A Division JPH0715667B2 (ja) 1992-02-14 1992-02-14 データ処理装置

Publications (2)

Publication Number Publication Date
JPS5864689A JPS5864689A (ja) 1983-04-18
JPH056706B2 true JPH056706B2 (en, 2012) 1993-01-27

Family

ID=15759463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56162691A Granted JPS5864689A (ja) 1981-10-14 1981-10-14 デ−タ処理装置

Country Status (1)

Country Link
JP (1) JPS5864689A (en, 2012)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59178700A (ja) * 1983-03-29 1984-10-09 Shimadzu Corp デ−タ処理装置
JPH0793220A (ja) * 1993-09-20 1995-04-07 Agency Of Ind Science & Technol 仮想記憶管理方式

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5821352B2 (ja) * 1979-09-17 1983-04-28 株式会社日立製作所 バツフア・メモリ制御方式

Also Published As

Publication number Publication date
JPS5864689A (ja) 1983-04-18

Similar Documents

Publication Publication Date Title
US4481573A (en) Shared virtual address translation unit for a multiprocessor system
KR100242484B1 (ko) 캐쉬 메모리 시스템의 성능 최적화 방법 및 장치
US4924466A (en) Direct hardware error identification method and apparatus for error recovery in pipelined processing areas of a computer system
US6625698B2 (en) Method and apparatus for controlling memory storage locks based on cache line ownership
JP4119380B2 (ja) マルチプロセッサシステム
JPH0345407B2 (en, 2012)
JPH041374B2 (en, 2012)
US6473845B1 (en) System and method for dynamically updating memory address mappings
US6892283B2 (en) High speed memory cloner with extended cache coherency protocols and responses
EP0474450A2 (en) Processor system with improved memory transfer means
JP3590075B2 (ja) 仮想記憶方式のデータ処理装置及び方法
US5161219A (en) Computer system with input/output cache
US20030014697A1 (en) System and method for dynamically moving checksums to different memory locations
JPH0567976B2 (en, 2012)
JP2829115B2 (ja) ファイル共用方法
JP3814521B2 (ja) データ処理方法および装置
JP3836836B2 (ja) メモリ複製オペレーション時の不正確なキャッシュ・ライン保護機構
JPH056706B2 (en, 2012)
JP2813182B2 (ja) マルチプロセッサコンピュータ複合装置
JPS6113261B2 (en, 2012)
JPS63253448A (ja) マルチ計算機装置
JPS6138504B2 (en, 2012)
US6915390B2 (en) High speed memory cloning facility via a coherently done mechanism
JPH0573417A (ja) データ処理装置
JPS5864690A (ja) キヤツシユメモリ制御方法