JPH0567976B2 - - Google Patents

Info

Publication number
JPH0567976B2
JPH0567976B2 JP1328623A JP32862389A JPH0567976B2 JP H0567976 B2 JPH0567976 B2 JP H0567976B2 JP 1328623 A JP1328623 A JP 1328623A JP 32862389 A JP32862389 A JP 32862389A JP H0567976 B2 JPH0567976 B2 JP H0567976B2
Authority
JP
Japan
Prior art keywords
cache
line
store
bce
sce
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1328623A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0340047A (ja
Inventor
Ryuu Riishiingu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH0340047A publication Critical patent/JPH0340047A/ja
Publication of JPH0567976B2 publication Critical patent/JPH0567976B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP1328623A 1988-12-23 1989-12-20 キヤツシユ・ライン・ストア方法 Granted JPH0340047A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US289659 1981-08-03
US07/289,659 US5016168A (en) 1988-12-23 1988-12-23 Method for storing into non-exclusive cache lines in multiprocessor systems

Publications (2)

Publication Number Publication Date
JPH0340047A JPH0340047A (ja) 1991-02-20
JPH0567976B2 true JPH0567976B2 (en, 2012) 1993-09-28

Family

ID=23112511

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1328623A Granted JPH0340047A (ja) 1988-12-23 1989-12-20 キヤツシユ・ライン・ストア方法

Country Status (4)

Country Link
US (1) US5016168A (en, 2012)
EP (1) EP0374370B1 (en, 2012)
JP (1) JPH0340047A (en, 2012)
DE (1) DE68926878T2 (en, 2012)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214766A (en) * 1989-04-28 1993-05-25 International Business Machines Corporation Data prefetching based on store information in multi-processor caches
US5230070A (en) * 1989-09-08 1993-07-20 International Business Machines Corporation Access authorization table for multi-processor caches
US5197139A (en) * 1990-04-05 1993-03-23 International Business Machines Corporation Cache management for multi-processor systems utilizing bulk cross-invalidate
US5263142A (en) * 1990-04-12 1993-11-16 Sun Microsystems, Inc. Input/output cache with mapped pages allocated for caching direct (virtual) memory access input/output data based on type of I/O devices
US5404483A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills
US5291442A (en) * 1990-10-31 1994-03-01 International Business Machines Corporation Method and apparatus for dynamic cache line sectoring in multiprocessor systems
JP2788836B2 (ja) * 1992-05-15 1998-08-20 インターナショナル・ビジネス・マシーンズ・コーポレイション ディジタルコンピュータシステム
US5699538A (en) * 1994-12-09 1997-12-16 International Business Machines Corporation Efficient firm consistency support mechanisms in an out-of-order execution superscaler multiprocessor
US5924121A (en) * 1996-12-23 1999-07-13 International Business Machines Corporation Adaptive writeback of cache line data in a computer operated with burst mode transfer cycles
US6260117B1 (en) * 1997-09-18 2001-07-10 International Business Machines Corporation Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency
JP2002287997A (ja) * 2001-03-23 2002-10-04 Kinji Mori 多重系処理方法
US8244983B2 (en) * 2006-10-30 2012-08-14 Hewlett-Packard Development Company, L.P. Memory control systems with directory caches and methods for operation thereof
US9075727B2 (en) * 2012-06-14 2015-07-07 International Business Machines Corporation Reducing penalties for cache accessing operations
US11188379B2 (en) * 2018-09-21 2021-11-30 International Business Machines Corporation Thermal capacity optimization for maximized single core performance

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4394731A (en) * 1980-11-10 1983-07-19 International Business Machines Corporation Cache storage line shareability control for a multiprocessor system
US4484267A (en) * 1981-12-30 1984-11-20 International Business Machines Corporation Cache sharing control in a multiprocessor
US4775955A (en) * 1985-10-30 1988-10-04 International Business Machines Corporation Cache coherence mechanism based on locking
US4797814A (en) * 1986-05-01 1989-01-10 International Business Machines Corporation Variable address mode cache
US4925225A (en) * 1989-06-19 1990-05-15 Dost Incorporated Vacuum lifting device for handling sheet material

Also Published As

Publication number Publication date
EP0374370B1 (en) 1996-07-24
DE68926878T2 (de) 1997-02-06
EP0374370A2 (en) 1990-06-27
EP0374370A3 (en) 1991-07-17
JPH0340047A (ja) 1991-02-20
US5016168A (en) 1991-05-14
DE68926878D1 (de) 1996-08-29

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