JPH0564807B2 - - Google Patents
Info
- Publication number
- JPH0564807B2 JPH0564807B2 JP1014963A JP1496389A JPH0564807B2 JP H0564807 B2 JPH0564807 B2 JP H0564807B2 JP 1014963 A JP1014963 A JP 1014963A JP 1496389 A JP1496389 A JP 1496389A JP H0564807 B2 JPH0564807 B2 JP H0564807B2
- Authority
- JP
- Japan
- Prior art keywords
- register
- subroutine
- instruction
- register number
- argument
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30054—Unconditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1014963A JPH02196333A (ja) | 1989-01-26 | 1989-01-26 | サブルーチン呼出し方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1014963A JPH02196333A (ja) | 1989-01-26 | 1989-01-26 | サブルーチン呼出し方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02196333A JPH02196333A (ja) | 1990-08-02 |
| JPH0564807B2 true JPH0564807B2 (cs) | 1993-09-16 |
Family
ID=11875634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1014963A Granted JPH02196333A (ja) | 1989-01-26 | 1989-01-26 | サブルーチン呼出し方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02196333A (cs) |
-
1989
- 1989-01-26 JP JP1014963A patent/JPH02196333A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02196333A (ja) | 1990-08-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4715013A (en) | Coprocessor instruction format | |
| US4729094A (en) | Method and apparatus for coordinating execution of an instruction by a coprocessor | |
| US4731736A (en) | Method and apparatus for coordinating execution of an instruction by a selected coprocessor | |
| US4750110A (en) | Method and apparatus for executing an instruction contingent upon a condition present in another data processor | |
| US5021991A (en) | Coprocessor instruction format | |
| US4821231A (en) | Method and apparatus for selectively evaluating an effective address for a coprocessor | |
| US4914578A (en) | Method and apparatus for interrupting a coprocessor | |
| US4994961A (en) | Coprocessor instruction format | |
| JPH0564807B2 (cs) | ||
| US4758978A (en) | Method and apparatus for selectively evaluating an effective address for a coprocessor | |
| JPH0377137A (ja) | 情報処理装置 | |
| US4811274A (en) | Method and apparatus for selectively evaluating an effective address for a coprocessor | |
| JPS62243032A (ja) | 情報処理装置 | |
| JP3140028B2 (ja) | サブルーチンの引数の受け渡し方式 | |
| JP2586690B2 (ja) | 命令プリフェッチ装置 | |
| JPS63178330A (ja) | 演算フラグ制御装置 | |
| JPH04167146A (ja) | 情報処理装置のアドレストレース方式 | |
| JPH03127171A (ja) | ベクトル処理装置 | |
| JPH0259829A (ja) | マイクロコンピュータ | |
| JPS6236576B2 (cs) | ||
| JPS62221062A (ja) | シングルチツプマイクロコンピユ−タ | |
| JPH03182945A (ja) | 主記憶内データ転送方式 | |
| JPH0214335A (ja) | デバッガの割込み方式 | |
| JPS58176752A (ja) | マクロ命令フエツチ方式 | |
| JPH0242559A (ja) | 情報処理装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |