JPH0563027A - Bonding method for semiconductor device and substrate - Google Patents

Bonding method for semiconductor device and substrate

Info

Publication number
JPH0563027A
JPH0563027A JP4020897A JP2089792A JPH0563027A JP H0563027 A JPH0563027 A JP H0563027A JP 4020897 A JP4020897 A JP 4020897A JP 2089792 A JP2089792 A JP 2089792A JP H0563027 A JPH0563027 A JP H0563027A
Authority
JP
Japan
Prior art keywords
semiconductor device
substrate
bumps
adhesive
insulating adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4020897A
Other languages
Japanese (ja)
Other versions
JPH06103705B2 (en
Inventor
Kazuhiro Sugiyama
和弘 杉山
Toshiyoshi Deguchi
敏良 出口
Hisashi Masaki
久士 正木
Yoshio Yarita
好男 鑓田
Yoshinori Atsumi
好則 厚見
Toshiharu Tamaki
敏晴 玉木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP4020897A priority Critical patent/JPH06103705B2/en
Publication of JPH0563027A publication Critical patent/JPH0563027A/en
Publication of JPH06103705B2 publication Critical patent/JPH06103705B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a junction method between a semiconductor device and a substrate which is capable of reducing production cost by a further extent compared with an anisotropic conductive bonding agent-based method and, what is more, applicable to substrates having lower heat resistant properties. CONSTITUTION:An ultraviolet setting type insulating bonding agent 6 is applied to one side of a semiconductor device 1 at a thick coat in such a fashion that bumps 2b may be buried therein while each connection terminal 5a of a substrate 4 is formed in smaller width compared with the bumps 2b. Each bump 2b of the semiconductor device 1 is aligned with each mating connection terminal 5a of the substrate 4 so that the semiconductor device 1 and the substrate 4 are relatively depressed. Under this condition, ultraviolet rays are emitted thereto so that the insulating bonding agent 6 may be set.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は半導体装置と基板の接
合方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for joining a semiconductor device and a substrate.

【0002】[0002]

【従来の技術】IC装置等の半導体装置を基板に取付け
る方法としては、一般に、半導体ペレットのバンプと基
板の端子部とをワイヤボンディングにより接続する方法
が採用されているが、この方法は、ワイヤボンディング
に時間がかかるだけでなく、ボンディングワイヤも高価
であるために、かなりコスト高となるから、最近では、
半導体ペレットのバンプを直接基板の端子部に接続する
方法が検討されている。
2. Description of the Related Art As a method of mounting a semiconductor device such as an IC device on a substrate, a method of connecting a bump of a semiconductor pellet and a terminal portion of the substrate by wire bonding is generally used. Not only is the bonding time consuming, but the cost of the bonding wires is also very high, so these days,
A method of directly connecting the bumps of the semiconductor pellet to the terminal portions of the substrate has been studied.

【0003】半導体装置のバンプを直接基板の端子部に
接続する半導体装置と基板の接合方法としては、従来、
半導体装置と、この半導体装置の各バンプに対応する端
子部が形成された基板とを、その接合面に異方導電性接
着剤を介在させて相対的に押圧することにより、半導体
装置と基板とを前記異方導電性接着剤によって接着接合
する方法が考えられている。
Conventionally, as a method of joining a semiconductor device and a substrate in which bumps of the semiconductor device are directly connected to terminal portions of the substrate,
The semiconductor device and the substrate are formed by relatively pressing the semiconductor device and the substrate on which the terminal portions corresponding to the bumps of the semiconductor device are formed with the anisotropic conductive adhesive interposed between the semiconductor device and the substrate. A method of adhesively bonding the above with the anisotropic conductive adhesive is considered.

【0004】なお、前記異方導電性接着剤が、絶縁性接
着剤中に導電性粒子を、導電性粒子同志が互いに接触し
合わないような割合で混入したもので、この異方導電性
接着剤からなる接着剤層は、厚さ方向には導通性を示す
が面方向(横方向)には絶縁性をもっているから、半導
体ペレットと基板との接合面に異方導電性接着剤を介在
させて半導体ペレットと基板とを相対的に押圧すると、
半導体ペレットの各バンプと基板の各端子部とが導通接
続(導電性粒子を介して導通接続)される。
The anisotropic conductive adhesive is a mixture of electrically conductive particles in an insulating adhesive in such a ratio that the conductive particles do not contact each other. Since the adhesive layer made of an agent has conductivity in the thickness direction but has an insulating property in the surface direction (lateral direction), an anisotropic conductive adhesive is interposed on the bonding surface between the semiconductor pellet and the substrate. When the semiconductor pellet and the substrate are pressed relative to each other,
Each bump of the semiconductor pellet and each terminal portion of the substrate are electrically connected (electrically connected via conductive particles).

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記の
ように異方導電性接着剤によって半導体装置と基板とを
接着接合する方法では、半導体装置の各バンプと基板の
各端子部との全てが必ず導通接続されるとは限らず、そ
のために信頼性が悪いという問題をもっていた。これ
は、前記異方導電性接着剤の導電性粒子の分布が不規則
にばらついているためであり、これに対して半導体装置
の各バンプの巾は非常に狭いから、異方導電性接着剤に
その導電性粒子の間隔が前記バンプの巾より広くなって
いる箇所があってこの箇所に半導体装置のバンプがたま
たま対応すると、この部分のバンプと基板の端子部との
間には導電性粒子が介在されずにこのバンプと端子部と
が導通接続されない状態になる。
However, in the method of adhesively bonding the semiconductor device and the substrate with the anisotropic conductive adhesive as described above, all of the bumps of the semiconductor device and the terminal portions of the substrate are all indispensable. There is a problem in that reliability is poor because it is not always connected electrically. This is because the distribution of the conductive particles of the anisotropic conductive adhesive varies irregularly, whereas the width of each bump of the semiconductor device is very narrow, so that the anisotropic conductive adhesive There is a portion where the distance between the conductive particles is wider than the width of the bump, and the bump of the semiconductor device happens to correspond to this portion, the conductive particle is present between the bump at this portion and the terminal portion of the substrate. The bump and the terminal portion are not electrically connected to each other without the interposition of.

【0006】なお、異方導電性接着剤中の導電性粒子の
混入比を多くしてやれば、導電性粒子の間隔も小さくな
るから、全てのバンプと端子部とをほぼ確実に導通接続
することができるが、このように異方導電性接着剤中の
導電性粒子の混入比を多くすると、導電性粒子の間隔が
密になっている部分で導電性粒子同志が接触し合って隣
接するバンプ同志を短絡させてしまうことになる。
If the mixing ratio of the conductive particles in the anisotropic conductive adhesive is increased, the distance between the conductive particles also becomes smaller, so that all the bumps and the terminal portions can be almost surely electrically connected. However, if the mixing ratio of the conductive particles in the anisotropic conductive adhesive is increased in this way, the conductive particles will come into contact with each other at the portion where the conductive particles are closely spaced and the adjacent bumps will be adjacent to each other. Will be short-circuited.

【0007】また、上記異方導電性接着剤によって半導
体装置と基板とを接着接合する方法は、半導体装置また
は基板の接合面に異方導電性接着剤を塗布して半導体装
置と基板とを押圧することで半導体装置のバンプと基板
の端子部とを導通接続することができるから、短時間で
半導体装置と基板とを接合することができ、従ってワイ
ヤボンディングによる方法に比べればある程度はコスト
を下げることができるが、それでも、異方導電性接着剤
が高価出あるために、大幅はコストダウンははかれなか
った。
In the method of adhesively bonding the semiconductor device and the substrate with the anisotropic conductive adhesive, the anisotropic conductive adhesive is applied to the bonding surface of the semiconductor device or the substrate, and the semiconductor device and the substrate are pressed. By doing so, the bumps of the semiconductor device and the terminal portions of the substrate can be electrically connected, so that the semiconductor device and the substrate can be joined in a short time, and thus the cost can be reduced to some extent as compared with the method by wire bonding. However, the cost was not significantly reduced because the anisotropic conductive adhesive was expensive.

【0008】また、上記の異方導電性接着剤を用いる接
合では、接着剤が硬化するまで長時間加圧状態を維持す
ることは好ましくない為、一般にホットメルト型の接着
剤を用いるが、このような接合方法は耐熱性の低い基板
に対しては適用できないという問題もある。
Further, in the above-mentioned joining using the anisotropic conductive adhesive, it is not preferable to maintain the pressure state for a long time until the adhesive is hardened. Therefore, a hot melt type adhesive is generally used. There is also a problem that such a joining method cannot be applied to a substrate having low heat resistance.

【0009】この発明は、上記の実情に鑑みてなされた
ものであって、その目的とするところは、異方導電性接
着剤によって半導体装置と基板を接着接合する方法と同
様、能率よく半導体装置と基板とを接合することができ
るものであって、異方導電性接着剤を用いる方法よりも
さらにコストを低減することができ、かつ、より耐熱性
の低い基板に対しても適用可能な半導体装置と基板の接
合方法を提供することにある。
The present invention has been made in view of the above circumstances, and its purpose is to efficiently perform a semiconductor device as in the method of adhesively bonding a semiconductor device and a substrate with an anisotropic conductive adhesive. And a substrate can be bonded together, the cost can be further reduced as compared with the method using an anisotropic conductive adhesive, and the semiconductor can be applied to a substrate having lower heat resistance. It is to provide a method of joining a device and a substrate.

【0010】[0010]

【課題を解決するための手段】この発明の半導体装置と
基板の接合方法は、半導体装置の一面にバンプが埋没す
るように紫外線硬化型の絶縁性接着剤を厚く被着すると
共に基板の各接続用端子部を前記バンプよりも巾狭に形
成し、前記半導体装置の各バンプを前記基板の各対応す
る接続用端子部に位置合わせして前記半導体装置と前記
基板とを相対的に押圧し、この状態で紫外線を照射して
前記絶縁性接着剤を硬化するものである。
According to a method of joining a semiconductor device and a substrate of the present invention, an ultraviolet curable insulating adhesive is thickly deposited so that a bump is buried on one surface of the semiconductor device, and each connection of the substrate is made. Forming a terminal portion for use narrower than the bump, aligning each bump of the semiconductor device with each corresponding connecting terminal portion of the substrate, and relatively pressing the semiconductor device and the substrate, In this state, ultraviolet rays are irradiated to cure the insulating adhesive.

【0011】[0011]

【作用】このような接合方法では、絶縁性接着剤のみに
よる接合であり高価な導電性粒子を全く使用することが
ないから材料が安価であり、しかも、絶縁性接着剤は半
導体装置の全面に被着するだけでよいから大変能率的と
なって、コストを低減することができる。また、絶縁性
接着剤は紫外線の照射によって硬化する紫外線硬化型で
あるから低温接合が可能となって、耐熱性の低い基板を
用いたり、接合の信頼性を向上することができる。さら
に、基板の接続用端子が半導体装置のバンプよりも巾狭
になっているので、位置ずれの許容差を大きくすること
ができ、より生産能率が向上する。
According to such a joining method, since the joining is performed only by the insulating adhesive and expensive conductive particles are not used at all, the material is inexpensive, and the insulating adhesive is applied to the entire surface of the semiconductor device. Since it only needs to be attached, it is very efficient and the cost can be reduced. Further, since the insulating adhesive is an ultraviolet curable type which is cured by irradiation of ultraviolet rays, low temperature bonding is possible, and a substrate having low heat resistance can be used and bonding reliability can be improved. Further, since the connection terminals of the substrate are narrower than the bumps of the semiconductor device, the tolerance of positional deviation can be increased, and the production efficiency is further improved.

【0012】[0012]

【実施例】以下、この発明の一実施例を図面を参照して
説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0013】図1において、1は半導体装置(例えばI
Cペレット)であり、この半導体装置1の主面には、そ
の外周に沿わせて多数の端子部2,2,…が配列され、
またこの半導体装置1の主面には、前記端子部2,2,
…を除いて、絶縁性の保護膜3が主面全面にわたって形
成されている。なお、この半導体装置1は、例えば一辺
の長さが4mmの方形で厚さが0.3mmのもので、各端子
部は0.1〜0.5mmのピッチで配列されている。
In FIG. 1, 1 is a semiconductor device (for example, I
C pellets), on the main surface of the semiconductor device 1, a large number of terminal portions 2, 2, ...
Further, on the main surface of the semiconductor device 1, the terminal portions 2, 2,
Except for ..., Insulating protective film 3 is formed over the entire main surface. The semiconductor device 1 is, for example, a rectangle having a side length of 4 mm and a thickness of 0.3 mm, and the terminals are arranged at a pitch of 0.1 to 0.5 mm.

【0014】また、4は絶縁材からなる配線基板であ
り、この基板4面には多数の配線5,5,…が形成され
ている。この各配線5,5,…は、基板4面の半導体装
置取付け位置から導出されており、各配線5,5,…の
半導体装置取付け位置側の端部はそれぞれ半導体装置1
の各端子部2,2,…とそれぞれ対応する半導体装置接
続用端子部5a,5a,…とされている。なお、この半
導体装置接続用端子部5a,5a,…の巾は、半導体装
置1の端子部2,2,…の巾よりわずかに狭い巾とされ
ている。
A wiring board 4 made of an insulating material has a large number of wirings 5, 5, ... Formed on the surface of the board 4. The wirings 5, 5, ... Are derived from the semiconductor device mounting position on the surface of the substrate 4, and the ends of the wirings 5, 5 ,.
, And semiconductor device connecting terminal portions 5a, 5a, ... Corresponding to the respective terminal portions 2, 2 ,. The width of the semiconductor device connecting terminal portions 5a, 5a, ... Is made slightly narrower than the width of the terminal portions 2, 2 ,.

【0015】この実施例は、半導体装置1と基板4との
一方例えば基板4の半導体装置取付け位置に、この基板
4面に形成した各端子部5a,5a,…の上から絶縁性
接着剤6を塗布し、その上に半導体装置1を重ねてこの
半導体装置1と基板4とを相対的に押圧することによ
り、半導体装置1側の各端子部2,2,…と基板4側の
各端子部5a,5a,…とを導通接続させるとともに、
前記絶縁性接着剤6を硬化させて半導体装置1と基板4
とを絶縁性接着剤6によって接着接合するものであり、
この半導体装置1と基板4との接合は具体的には次のよ
うにして行なわれる。
In this embodiment, one of the semiconductor device 1 and the substrate 4, for example, at the semiconductor device mounting position of the substrate 4, the insulating adhesive 6 is applied from above the terminal portions 5a, 5a, ... Formed on the surface of the substrate 4. Are applied, the semiconductor device 1 is overlaid thereon, and the semiconductor device 1 and the substrate 4 are pressed relatively to each other, so that each terminal portion 2, 2, ... On the semiconductor device 1 side and each terminal on the substrate 4 side are applied. While electrically connecting the parts 5a, 5a, ...
The semiconductor device 1 and the substrate 4 are obtained by curing the insulating adhesive 6.
And are bonded together with an insulating adhesive 6,
The joining of the semiconductor device 1 and the substrate 4 is specifically performed as follows.

【0016】まず、図2(a)に示すような半導体装置
接続用端子部5a,5a,…を配列形成した基板1面
に、その各端子部5a,5a,…を含む半導体装置接合
面全体にわたって各端子部5a,5a,…の上から絶縁
性接着剤6を図2(b)に示すようにほぼ均一厚さに塗
布する。
First, the entire semiconductor device bonding surface including the respective terminal portions 5a, 5a, ... On the surface of the substrate 1 on which the semiconductor device connecting terminal portions 5a, 5a ,. The insulating adhesive 6 is applied over the respective terminal portions 5a, 5a, ... To a substantially uniform thickness as shown in FIG. 2 (b).

【0017】この後、図2(c)に示すように、前記絶
縁性接着剤6の上から半導体装置1を、その各端子部
2,2,…を基板4側の各端子部5a,5a,…とそれ
ぞれ対応させて重ね、この状態で半導体装置1をその上
から加圧治具7により加圧して半導体装置1と基板とを
相対的に押圧するとともに、前記絶縁性接着剤6を硬化
させて半導体装置1と基板4とを絶縁性接着剤6によっ
て接着接合する。
Thereafter, as shown in FIG. 2C, the semiconductor device 1 is mounted on the insulating adhesive 6 so that the terminal portions 2, 2, ... Are connected to the terminal portions 5a, 5a on the substrate 4 side. , And so on, and in this state, the semiconductor device 1 is pressed from above by a pressing jig 7 to relatively press the semiconductor device 1 and the substrate, and the insulating adhesive 6 is cured. Then, the semiconductor device 1 and the substrate 4 are adhesively bonded to each other with the insulating adhesive 6.

【0018】しかして、上記のように絶縁性接着剤6の
上から半導体装置1を重ねて半導体装置1と基板4とを
相対的に押圧すると、この押圧力により、半導体装置1
と基板4との両方の端子部2,5a間の接着剤6がこの
端子部間の外側に押出され、両方の端子部2,5aが図
2(c)に示すように互いに直接接触してこの両端子部
2,5aが導通接続される。なお、半導体装置1と基板
4とを相対的に押圧する加圧力は、700g〜1Kg程
度で十分であり、この程度の加圧力で半導体装置1と基
板4とを相対的に押圧すると両端子部2,5a間の接着
剤6がほぼ完全に押出されて両端子部2,5aが十分な
導通性をもって接続される。また、この状態で前記絶縁
性接着剤6を硬化させると、この接着剤6により半導体
装置1と基板4とが互いに接着される。
When the semiconductor device 1 is overlaid on the insulating adhesive 6 and the semiconductor device 1 and the substrate 4 are relatively pressed as described above, the pressing force causes the semiconductor device 1 to move.
The adhesive 6 between the terminal portions 2 and 5a of the substrate 4 and the substrate 4 is extruded to the outside between the terminal portions, and both the terminal portions 2 and 5a come into direct contact with each other as shown in FIG. 2 (c). The two terminal portions 2, 5a are electrically connected. The pressing force for relatively pressing the semiconductor device 1 and the substrate 4 is about 700 g to 1 Kg, and when the semiconductor device 1 and the substrate 4 are relatively pressed by this pressing force, both terminal portions are pressed. The adhesive 6 between the terminals 2 and 5a is almost completely extruded and the two terminal portions 2 and 5a are connected with sufficient conductivity. Further, when the insulating adhesive 6 is cured in this state, the adhesive 6 bonds the semiconductor device 1 and the substrate 4 to each other.

【0019】なお、接着剤としては、常温硬化型、一般
にホットメルト型と呼ばれている熱可塑性接着剤や熱硬
化性接着剤なども考えられるが、本発明においては、絶
縁性接着剤6としてUVインクを用いることを特徴とす
る。この場合、基板4面に塗布したUVインク絶縁性接
着剤6の上に半導体装置1を重ねて加圧し、この状態で
紫外線を照射して絶縁性接着剤6を硬化させる。この接
合方法は直接加熱する熱圧着方法によりも低温で接合が
行なわれるため、基板4として耐熱性の低い安価な材料
のものを用いることが可能となる。このようにして半導
体装置1を基板4に接着接合した後は、必要に応じて図
3に示すように半導体装置1をエポキシ樹脂等の合成樹
脂8でモールドする。
As the adhesive, a thermoplastic adhesive or a thermosetting adhesive which is generally called a room temperature curable type or a hot melt type may be considered. In the present invention, the insulating adhesive 6 is used. It is characterized by using UV ink. In this case, the semiconductor device 1 is superposed on the UV ink insulating adhesive 6 applied to the surface of the substrate 4 and pressed, and in this state, the insulating adhesive 6 is cured by irradiating ultraviolet rays. In this bonding method, the bonding is performed at a lower temperature than the thermocompression bonding method of directly heating, so that the substrate 4 can be made of an inexpensive material having low heat resistance. After the semiconductor device 1 is adhesively bonded to the substrate 4 in this manner, the semiconductor device 1 is molded with a synthetic resin 8 such as an epoxy resin as required, as shown in FIG.

【0020】図4は上記のようにして接合された半導体
装置1と基板4の接合部の一部分を拡大して示したもの
で、半導体装置1は、その端子部2から金バンプをなく
したものとされている。すなわち、図4において、11
は半導体装置1の基材(ここではN型基材)、12はP
型拡散層、13はN型拡散層であり、これら拡散層1
2,13が形成された一面には酸化シリコン(Si
2 )からなる絶縁膜14が形成され、この上にはアル
ミニウムからなる配線15が形成されている。この配線
15は、前記絶縁膜14に設けた開口部において前記拡
散層12,13のうちの所定の拡散層と導通されてい
る。また、この配線15は、装置一面の外周縁部に導出
されており、この配線15の端部は、外部回路との接続
用パッド2aとされ、このパッド2aは、そのまま半導
体装置1の端子部2とされている。また、3は前記配線
15の上から半導体装置1の主面に形成された酸化シリ
コンからなる絶縁保護膜であり、この保護膜3は、前記
パッド2aからなる端子部2を除いて形成されている。
FIG. 4 is an enlarged view of a part of the joint portion between the semiconductor device 1 and the substrate 4 joined as described above. The semiconductor device 1 has the terminal portion 2 without the gold bump. It is said that. That is, in FIG.
Is a base material of the semiconductor device 1 (here, N-type base material), 12 is P
Type diffusion layer, 13 is an N type diffusion layer, and these diffusion layers 1
Silicon oxide (Si
An insulating film 14 made of O 2 ) is formed, and a wiring 15 made of aluminum is formed thereon. The wiring 15 is electrically connected to a predetermined diffusion layer of the diffusion layers 12 and 13 at the opening provided in the insulating film 14. Further, the wiring 15 is led out to the outer peripheral portion of the one surface of the device, and the end portion of the wiring 15 is used as a pad 2a for connection with an external circuit, and the pad 2a is directly the terminal portion of the semiconductor device 1. It is supposed to be 2. Further, 3 is an insulating protective film made of silicon oxide formed on the main surface of the semiconductor device 1 from above the wiring 15, and the protective film 3 is formed excluding the terminal portion 2 made of the pad 2a. There is.

【0021】しかして、図5は本発明の接合方法の最も
好ましい実施例を説明する為の半導体装置1および基板
4の端子部配列に沿う断面図である。ここにおいて、半
導体装置1の端子部2,2,…の各パッド2a(図4参
照)の上に金をメッキして金バンプ2b,2b,…を形
成する。また、これら金バンプ2b,2b,…が形成さ
れた半導体装置1の一面には、図5に示すように、UV
インク絶縁性接着剤6を、各金バンプ2b,2b,…が
埋没するように厚く塗布する。このようにすると、絶縁
性接着剤6の塗布面は半導体装置1の面積以上には拡が
らないため、塗布量のコントロールが容易となる。な
お、絶縁性接着剤はあらかじめシート状に成形しておく
こともできる。
FIG. 5 is a sectional view taken along the arrangement of the terminal portions of the semiconductor device 1 and the substrate 4 for explaining the most preferred embodiment of the joining method of the present invention. Here, gold is plated on each pad 2a (see FIG. 4) of the terminal portions 2, 2, ... Of the semiconductor device 1 to form gold bumps 2b, 2b ,. Further, as shown in FIG. 5, the one surface of the semiconductor device 1 on which the gold bumps 2b, 2b, ...
The ink insulating adhesive 6 is applied thickly so that the gold bumps 2b, 2b, ... Are buried. In this case, the coated surface of the insulating adhesive 6 does not extend beyond the area of the semiconductor device 1, so that the coated amount can be easily controlled. The insulating adhesive may be formed into a sheet shape in advance.

【0022】[0022]

【発明の効果】以上説明した如く、本発明の接合方法
は、絶縁性接着剤のみによる接合であって高価な導電性
粒子を全く使用することがないから材料が安価であり、
しかも、絶縁性接着剤は半導体装置の全面に被着するだ
けでよいから大変能率的となって、コストの低減が可能
であり、また、絶縁性接着剤は紫外線の照射によって硬
化する紫外線硬化型であるから低温接合が可能となっ
て、耐熱性の低い基板を用いたり、接合の信頼性を向上
することができ、さらに、基板の接続用端子が半導体装
置のバンプよりも巾狭になっているので、位置ずれの許
容差を大きくしてより生産能率の向上を図ることができ
る、等の効果を奏する。
As described above, in the joining method of the present invention, the material is inexpensive because the joining is performed only by the insulating adhesive and no expensive conductive particles are used.
Moreover, since the insulating adhesive only needs to be applied to the entire surface of the semiconductor device, it is very efficient and the cost can be reduced. Further, the insulating adhesive is an ultraviolet curable type which is cured by irradiation of ultraviolet rays. Therefore, low-temperature bonding is possible, a substrate with low heat resistance can be used, bonding reliability can be improved, and the connection terminals of the substrate are narrower than the bumps of the semiconductor device. Therefore, there is an effect that the tolerance of the positional deviation can be increased and the production efficiency can be further improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の接合方法を説明するための接合方法
の概略図。
FIG. 1 is a schematic view of a joining method for explaining the joining method of the present invention.

【図2】絶縁性接着剤の塗布状態を説明するための端子
部配列に沿う断面図。
FIG. 2 is a cross-sectional view taken along an arrangement of terminal portions for explaining a coated state of an insulating adhesive.

【図3】半導体装置をモールドした状態の断面図。FIG. 3 is a cross-sectional view of a state in which a semiconductor device is molded.

【図4】図3のA−A線に沿う拡大断面図。FIG. 4 is an enlarged cross-sectional view taken along the line AA of FIG.

【図5】この発明の接合方法の最も好ましい実施例を示
す半導体装置と基板の端子部配列線に沿う断面図。
FIG. 5 is a cross-sectional view showing a most preferred embodiment of the joining method of the present invention along a semiconductor device and a substrate terminal portion arrangement line.

【符号の説明】[Explanation of symbols]

1…半導体装置(ICペレット)、2…端子部、2a…
パッド、2b…金バンプ、4…基板、5…配線、5a…
端子部、6…絶縁性接着剤(UVインク)
1 ... Semiconductor device (IC pellet), 2 ... Terminal part, 2a ...
Pads, 2b ... Gold bumps, 4 ... Substrate, 5 ... Wiring, 5a ...
Terminal part, 6 ... Insulating adhesive (UV ink)

───────────────────────────────────────────────────── フロントページの続き (72)発明者 正木 久士 東京都羽村市栄町3丁目2番1号 カシオ 計算機株式会社羽村技術センター内(市制 実施による住居表示の変更) (72)発明者 鑓田 好男 東京都羽村市栄町3丁目2番1号 カシオ 計算機株式会社羽村技術センター内(市制 実施による住居表示の変更) (72)発明者 厚見 好則 東京都羽村市栄町3丁目2番1号 カシオ 計算機株式会社羽村技術センター内(市制 実施による住居表示の変更) (72)発明者 玉木 敏晴 東京都羽村市栄町3丁目2番1号 カシオ 計算機株式会社羽村技術センター内(市制 実施による住居表示の変更) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hisashi Masaki 3-2-1 Sakaemachi, Hamura-shi, Tokyo Casio Computer Co., Ltd. Hamura Technical Center (change of residence display due to the implementation of the municipal system) (72) Inventor Yoshiru Akita Man 3-2-1 Sakaemachi, Hamura-shi, Tokyo Casio Computer Co., Ltd. Hamura Technical Center (change of housing display due to city system implementation) (72) Inventor Yoshinori Atsumi 3-2-1 Sakaemachi, Hamura-shi, Tokyo Casio Computer Co., Ltd. Hamura Technical Center (change of housing display due to city system implementation) (72) Inventor Toshiharu Tamaki 3-2-1, Sakaemachi, Hamura City, Tokyo Casio Computer Co., Ltd. Hamura Technical Center (house based at city system implementation Display change)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】一面に複数のバンプが形成された半導体装
置を、前記バンプに対応する接続用端子部を有する基板
に接合する方法において、前記半導体装置の一面に前記
バンプが埋没するように紫外線硬化型の絶縁性接着剤を
厚く被着すると共に前記基板の各接続用端子部を前記バ
ンプよりも巾狭に形成し、前記絶縁性接着剤を介して前
記半導体装置の各バンプを前記基板の各対応する接続用
端子部に位置合わせした上、前記半導体装置と前記基板
とを相対的に押圧し、この状態で紫外線を照射して前記
絶縁性接着剤を硬化することを特徴とする半導体装置と
基板の接合方法。
1. A method of bonding a semiconductor device having a plurality of bumps formed on one surface thereof to a substrate having connection terminal portions corresponding to the bumps, wherein ultraviolet rays are applied so that the bumps are buried on one surface of the semiconductor device. A curable insulating adhesive is applied thickly and each connecting terminal portion of the substrate is formed narrower than the bump, and each bump of the semiconductor device is formed on the substrate through the insulating adhesive. The semiconductor device is characterized in that the semiconductor device and the substrate are pressed relative to each other and aligned with each corresponding connection terminal portion, and in this state, ultraviolet rays are irradiated to cure the insulating adhesive. And board bonding method.
JP4020897A 1992-02-06 1992-02-06 Method of joining semiconductor device and substrate Expired - Lifetime JPH06103705B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4020897A JPH06103705B2 (en) 1992-02-06 1992-02-06 Method of joining semiconductor device and substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4020897A JPH06103705B2 (en) 1992-02-06 1992-02-06 Method of joining semiconductor device and substrate

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP60033949A Division JPH0638436B2 (en) 1985-02-22 1985-02-22 Method of joining semiconductor pellet and substrate

Publications (2)

Publication Number Publication Date
JPH0563027A true JPH0563027A (en) 1993-03-12
JPH06103705B2 JPH06103705B2 (en) 1994-12-14

Family

ID=12040020

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4020897A Expired - Lifetime JPH06103705B2 (en) 1992-02-06 1992-02-06 Method of joining semiconductor device and substrate

Country Status (1)

Country Link
JP (1) JPH06103705B2 (en)

Also Published As

Publication number Publication date
JPH06103705B2 (en) 1994-12-14

Similar Documents

Publication Publication Date Title
JP3962449B2 (en) Method and structure for bonding substrates
US5561323A (en) Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto
US5949142A (en) Chip size package and method of manufacturing the same
KR100368698B1 (en) Semiconductor package, semiconductor device using the same and manufacturing method thereof
US5633533A (en) Electronic package with thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto
WO1997047031A1 (en) Method for mounting semiconductor chip
US20060081999A1 (en) Connection structure for connecting semiconductor element and wiring board, and semiconductor device
JPH0638436B2 (en) Method of joining semiconductor pellet and substrate
JPH10112478A (en) Ball grid array semiconductor device and its mounting method
JP2553491B2 (en) How to join electronic components
JPH11102989A (en) Bga semiconductor device
JPH0563027A (en) Bonding method for semiconductor device and substrate
JP3225800B2 (en) Semiconductor device
JPH0563031A (en) Bonding method for semiconductor device and substrate
JPH0436574B2 (en)
JP3155811B2 (en) Method for manufacturing resin-encapsulated semiconductor device
JPH06139824A (en) Anisotropic conducting film
JP2002118148A (en) Method of mounting semiconductor chip to printed circuit board, and mounting sheet used for embodying the method
JP3457547B2 (en) Semiconductor device, method of manufacturing the same, and film carrier
JPH0638437B2 (en) Method of joining semiconductor pellets
JPH0779192B2 (en) How to join electronic components
JP3472342B2 (en) Method of manufacturing semiconductor device package
JP3527589B2 (en) Semiconductor device package and method of manufacturing the same
JP2836264B2 (en) Board mounting method for pad grid array package
JPH0563028A (en) Bonding method for semiconductor device

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term