JP2002118148A - Method of mounting semiconductor chip to printed circuit board, and mounting sheet used for embodying the method - Google Patents

Method of mounting semiconductor chip to printed circuit board, and mounting sheet used for embodying the method

Info

Publication number
JP2002118148A
JP2002118148A JP2000310211A JP2000310211A JP2002118148A JP 2002118148 A JP2002118148 A JP 2002118148A JP 2000310211 A JP2000310211 A JP 2000310211A JP 2000310211 A JP2000310211 A JP 2000310211A JP 2002118148 A JP2002118148 A JP 2002118148A
Authority
JP
Japan
Prior art keywords
semiconductor chip
wiring board
printed wiring
thermosetting resin
bump electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000310211A
Other languages
Japanese (ja)
Other versions
JP4441090B2 (en
Inventor
Kunio Nishihara
邦夫 西原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui Chemicals Inc
Original Assignee
Mitsui Chemicals Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui Chemicals Inc filed Critical Mitsui Chemicals Inc
Priority to JP2000310211A priority Critical patent/JP4441090B2/en
Publication of JP2002118148A publication Critical patent/JP2002118148A/en
Application granted granted Critical
Publication of JP4441090B2 publication Critical patent/JP4441090B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/27001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/27003Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the layer preform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81192Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PROBLEM TO BE SOLVED: To provide a novel semiconductor chip mounting method which can avoid a problem such as an improper connection between bump electrodes of a printed circuit board and terminals of semiconductor chips in a simple step and at low cost, and also to provide a mounting sheet used for embodying the method. SOLUTION: A sheet 2 for mounting of semiconductor chips having a thermosetting resin layer 2-1 of nearly the same thickness as the height of bump electrodes 1-2 of a printed circuit board 1 is manufactured on one surface of a synthetic resin film 2-2, the sheet is compression bonded against a surface of the board 1 provided with the bump electrodes 1-2, the film is peeled off therefrom, the bump electrodes 1-2 are bonded to terminals 3-2 on the chips 3 so that the electrodes are positioned as to correctly face the terminals 3-2 and as contacted therewith, the resin layer 2-1 is heated and cured.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、プリント配線基板
に半導体チップを装着する方法及びその方法の実施に用
いる半導体チップ装着用シートに関する.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor chip on a printed wiring board and a semiconductor chip mounting sheet used for carrying out the method.

【0002】[0002]

【従来の技術】従来、MPUやゲートアレー等に用いる
多ピンのLSIパッケージをプリント配線基板に実装す
る場合には、半導体チップの接続パッド部に共晶ハン
ダ、高温ハンダ、金等から成るバンプ電極を形成し、所
謂フェースダウン方式により、それらのバンプ電極をプ
リント配線基板上の相対応する端子部に対面、接触さ
せ、溶融/拡散接合するフリップチップ実装方法が採用
されてきた。然し、この方法によるときは、温度の周期
的変動を受けたとき、半導体チップとプリント配線基板
の熱膨張係数の違いにより接合部が破断する恐れがある
ため、フェースダウンで接続された半導体チップのバン
プ電極が設けられた面全体と、相対向するプリント配線
基板の間の間隙に液状の熱硬化性樹脂(アンダーフィル
材)を注入、硬化させ、バンプ接合部全面をプリント配
線基板に接合してバンプ電極に集中する熱応力を分散さ
せ、破断を防止する方法が提案されている。然しなが
ら、フリップチップ実装における半導体チップとプリン
ト配線基板の間の空隙は40〜200μmと小さく、そ
のためアンダーフィル材をボイドなく含浸させる工程に
は相当の時間が掛ること、及び、アンダーフィル材のロ
ット間の粘度管理が煩雑なこと等の問題がある。
2. Description of the Related Art Conventionally, when a multi-pin LSI package used for an MPU, a gate array, or the like is mounted on a printed wiring board, bump electrodes made of eutectic solder, high-temperature solder, gold, or the like are provided on connection pads of a semiconductor chip. And a flip-chip mounting method in which the bump electrodes are brought into contact with the corresponding terminal portions on the printed wiring board by a so-called face-down method, and are fused / diffusion-bonded. However, according to this method, when the semiconductor chip and the printed wiring board are subjected to periodic fluctuations in temperature, the junction may be broken due to a difference in thermal expansion coefficient between the semiconductor chip and the printed wiring board. Liquid thermosetting resin (underfill material) is injected into the gap between the entire surface on which the bump electrodes are provided and the opposing printed wiring board and cured, and the entire bump joint is joined to the printed wiring board. There has been proposed a method of dispersing thermal stress concentrated on a bump electrode to prevent breakage. However, the gap between the semiconductor chip and the printed wiring board in flip-chip mounting is as small as 40 to 200 μm, so that the step of impregnating the underfill material without voids takes a considerable amount of time, and the lot of the underfill material between lots. There is a problem that the viscosity management is complicated.

【0003】この解決方法として、シート状の熱硬化性
樹脂或いは熱可塑性樹脂を半導体チップとプリント配線
基板の間に挟み、熱圧着する技術が、例えば、特開平9
−213741号、特開平10−242208号、特開
平10−270497号などにより提案されている。然
しながら、特開平9−213741号の技術は、別途封
止材によりバンプ部を囲むように封止部を設ける工程が
必要であり、工程が煩雑になると同時にボイドの発生を
完全に回避することができないという問題がある。又、
特開平10−242208号の提案では、アンダーフィ
ル樹脂の位置合わせが必要であり、場所によりアンダー
フィル樹脂量の過不足が発生したり、逃げ穴によるボイ
ド発生の可能性があることが否めない。又更に、特開平
10−270497号では、絶縁接着フィルムに半導体
チップのバンプ電極を食い込ませてプリント配線基板の
端子部に接続させているため、バンプ電極先端には絶縁
接着フィルムの被膜が残存し、接続の信頼性を損ねるこ
とがあるなど、工程の面、信頼性の面より問題がある。
As a solution to this problem, a technique of sandwiching a sheet-like thermosetting resin or thermoplastic resin between a semiconductor chip and a printed wiring board and thermocompression bonding is disclosed in, for example, Japanese Patent Application Laid-Open No.
Japanese Patent Application Laid-Open Nos. 213741 and 10-242208 and 10-270497. However, the technique disclosed in Japanese Patent Application Laid-Open No. 9-213741 requires a step of separately providing a sealing portion so as to surround the bump portion with a sealing material, which makes the process complicated and completely avoids the generation of voids. There is a problem that can not be. or,
In the proposal of Japanese Patent Application Laid-Open No. H10-242208, it is necessary to position the underfill resin, and it is unavoidable that the amount of the underfill resin may be excessive or deficient depending on the location, or that voids may occur due to relief holes. Further, in JP-A-10-270497, since the bump electrode of the semiconductor chip is cut into the insulating adhesive film and connected to the terminal portion of the printed wiring board, the coating of the insulating adhesive film remains at the tip of the bump electrode. However, there is a problem in terms of process and reliability, for example, the connection reliability may be impaired.

【0004】[0004]

【発明が解決しようとする課題】本発明は上記の問題を
解決するためなされたものであって、その目的とすると
ころは、工程が単純で、コストが掛らず、かつプリント
配線基板のバンプ電極と半導体チップの端子が確実に接
続され、接続不良等の問題を生じることのない新規な半
導体チップ実装方法及びその方法の実施に用いる装着用
シートを提供することにある。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a simple and inexpensive process for bumping a printed wiring board. An object of the present invention is to provide a novel semiconductor chip mounting method in which an electrode and a terminal of a semiconductor chip are securely connected and no problem such as poor connection occurs, and a mounting sheet used for implementing the method.

【0005】[0005]

【課題を解決するための手段】本発明の上記第一の目的
は、下記〔a〕〜〔e〕のステップ、即ち、〔a〕合成
樹脂フィルムの一方の面に、プリント配線基板のバンプ
電極の高さHと同一程度の厚みTを有する熱硬化性樹脂
層を設けて成る半導体チップ装着用シートを製造するス
テップと、〔b〕プリント配線基板のバンプ電極が設け
られた面に、上記半導体チップ装着用シートの熱硬化性
樹脂層を圧着するステップと、〔c〕プリント配線基板
のバンプ電極面に圧着した半導体チップ装着用シートの
合成樹脂フィルムを引き剥がすステップと、〔d〕プリ
ント配線基板のバンプ電極が、対応する半導体チップ上
の端子に正しく対面し、接触するよう位置決めするステ
ップと、〔e〕プリント配線基板のバンプ電極を、半導
体チップ上の対応する端子に接合すると共に、熱硬化性
樹脂を加熱硬化するステップと、を含むことを特徴とす
る、プリント配線基板に半導体チップを装着する方法に
よって達成される。尚、ここで熱硬化性樹脂層の厚みT
を装着すべきプリント配線基板のバンプ電極の高さHと
同一程度とするということは、具体的には、(H−T)
を、±30μm以内、望ましくは±15μm以内とする
ことを意味する。この偏差(H−T)の許容限界は実際
にはバンプ電極の形状、寸法、分布密度、配置、熱硬化
性樹脂の粘度などにもよるもので特定し難いが、上記の
如くすることにより殆ど総ての半導体チップに対して目
的を達成し得るものである。
The first object of the present invention is to provide the following steps [a] to [e], ie, [a] forming a bump electrode of a printed wiring board on one surface of a synthetic resin film. Manufacturing a semiconductor chip mounting sheet provided with a thermosetting resin layer having a thickness T substantially equal to the height H of the semiconductor device; and [b] mounting the semiconductor on the surface of the printed wiring board on which the bump electrodes are provided. Pressing the thermosetting resin layer of the chip mounting sheet; [c] peeling off the synthetic resin film of the semiconductor chip mounting sheet pressed on the bump electrode surface of the printed wiring board; [d] printing wiring board Positioning the bump electrodes of the printed circuit board so that the bump electrodes of the printed circuit board correctly face and contact the corresponding terminals on the semiconductor chip; and That together joined to the terminal, characterized by comprising the steps of heating and curing the thermosetting resin, and is achieved by a method for mounting a semiconductor chip on a printed wiring board. Here, the thickness T of the thermosetting resin layer
Is about the same as the height H of the bump electrode of the printed wiring board to be mounted, specifically, (HT)
Is within ± 30 μm, preferably within ± 15 μm. The allowable limit of the deviation (HT) actually depends on the shape, dimensions, distribution density, arrangement, viscosity of the thermosetting resin and the like of the bump electrode, and is difficult to specify. The objective can be achieved for all the semiconductor chips.

【0006】本発明の第二の目的は、合成樹脂フィルム
の一方の面に、プリント配線基板のバンプ電極の高さH
と同一程度の厚みTを有する熱硬化性樹脂層を設けて成
ることを特徴とする、請求項1に記載のプリント配線基
板に半導体チップを装着する方法の実施に用いる半導体
チップ装着用シートによって達成される。このとき使用
する合成樹脂フィルムは、その上に積層される熱硬化性
樹脂の硬化温度より低いガラス転移温度を有するもので
あることが望ましい。熱硬化性樹脂としては、プリント
配線基板のバンプ電極と半導体チップの端子の接合温度
より低い硬化温度を有するエポキシ樹脂組成物が推奨さ
れる。又更に、そのエポキシ樹脂組成物は、50重量%
以上の無機質充填材を含むものであることが望ましい。
A second object of the present invention is to provide, on one surface of a synthetic resin film, a height H of a bump electrode of a printed wiring board.
A semiconductor chip mounting sheet used for carrying out a method for mounting a semiconductor chip on a printed wiring board according to claim 1, characterized in that it is provided with a thermosetting resin layer having the same thickness T as that of the semiconductor chip mounting sheet. Is done. It is desirable that the synthetic resin film used at this time has a glass transition temperature lower than the curing temperature of the thermosetting resin laminated thereon. As the thermosetting resin, an epoxy resin composition having a curing temperature lower than the joining temperature between the bump electrode of the printed wiring board and the terminal of the semiconductor chip is recommended. Still further, the epoxy resin composition is 50% by weight.
It is desirable to include the above-mentioned inorganic filler.

【0007】[0007]

【発明の実施の形態】以下、図面により本発明の一実施
例について説明する。図は、本発明方法の構成を示す説
明図であるが、説明を判りやすくするため、これらの図
面には、バンプ電極と、装着用シートが誇張して表示さ
れている。図1は、プリント配線基板の構成中、本発明
に関係する部分を示す一部拡大断面図、図2は、半導体
チップ装着用シートの拡大断面図、図3はプリント配線
基板のバンプ電極側のフェース面上に半導体チップ装着
用シートを貼り合わせた状態を示す一部拡大断面図、図
4は、貼り合せた半導体チップ装着用シートの合成樹脂
フィルム完全に引き剥がした状態を示す一部拡大断面
図、図5は、図4に示されたプリント配線基板に半導体
チップを実装した状態を示す一部拡大断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. The drawings are explanatory views showing the configuration of the method of the present invention, but in order to make the description easier to understand, these drawings show bump electrodes and a mounting sheet in an exaggerated manner. FIG. 1 is a partially enlarged sectional view showing a portion related to the present invention in the configuration of a printed wiring board, FIG. 2 is an enlarged sectional view of a semiconductor chip mounting sheet, and FIG. FIG. 4 is a partially enlarged cross-sectional view showing a state in which a semiconductor chip mounting sheet is bonded on a face surface, and FIG. 4 is a partially enlarged cross-sectional view showing a state in which the synthetic resin film of the bonded semiconductor chip mounting sheet is completely peeled off. FIG. 5 and FIG. 5 are partially enlarged sectional views showing a state where a semiconductor chip is mounted on the printed wiring board shown in FIG.

【0008】而して、これらの図中、1はプリント配線
基板、1−1 はその基板、1−2はバンプ電極であり、
バンプ電極の形成は、ハンダ、ニッケル、金等のメッキ
法、銀ペースト、金ペーストを用いた導電ペースト印刷
法、金ワイアのボールボンディング法、ハンダプリコー
ト法、ハンダペースト印刷リフロー法、ハンダボールリ
フロー法等の方法により形成される。2は、合成樹脂フ
ィルム2−2の一方の面に熱硬化性樹脂層2−1を形成
して成る半導体チップ装着用シート(以下、単に『装着
用シート』ともいう。)、3は半導体チップであり、チ
ップ配線面3−1の上に、プリント配線基板1のバンプ
電極1−2に対応する端子3−2を具備する。
In these figures, 1 is a printed wiring board, 1-1 is its board, 1-2 is a bump electrode,
The bump electrodes are formed by plating with solder, nickel, gold, etc., conductive paste printing using silver paste or gold paste, gold wire ball bonding, solder precoating, solder paste printing reflow, solder ball reflow. And the like. Reference numeral 2 denotes a semiconductor chip mounting sheet (hereinafter, simply referred to as “mounting sheet”) formed by forming a thermosetting resin layer 2-1 on one surface of a synthetic resin film 2-2, and 3 denotes a semiconductor chip. And a terminal 3-2 corresponding to the bump electrode 1-2 of the printed wiring board 1 is provided on the chip wiring surface 3-1.

【0009】而して、本発明方法により、プリント配線
基板1上に半導体チップ3を実装する場合には、先ず、
前記〔a〕ステップに記載の如く、合成樹脂フィルム2
−2の一方の面に熱硬化性樹脂層2−1を形成して成る
半導体チップ装着用シート2を製造する。その場合の熱
硬化性樹脂層2−1の厚さTは、この装着用シート2を
プリント配線基板1に貼り付けた際、バンプ電極1−2
の先端が熱硬化性樹脂層2−1を貫通して合成樹脂フィ
ルム2−2に接触すると共に、その貼着領域の周縁に適
量の熱硬化性樹脂がはみ出し、貼着面にボイドが残らな
いように定める。熱硬化性樹脂層2−1の厚さTの上限
及び下限は、厳密にはプリント配線基板1に形成された
バンプ電極1−2の寸法、形状、数、全体積及び分布状
況、並びに、熱硬化性樹脂層の硬度などにより定められ
るが、一般に用いられているプリント配線基板に対して
は概ねそのバンプ電極1−2の高さHと同一とすること
により上記の条件を成就することができる。
When mounting the semiconductor chip 3 on the printed wiring board 1 by the method of the present invention, first,
As described in the step (a), the synthetic resin film 2
-2, a semiconductor chip mounting sheet 2 having the thermosetting resin layer 2-1 formed on one surface is manufactured. In this case, the thickness T of the thermosetting resin layer 2-1 is such that when the mounting sheet 2 is attached to the printed wiring board 1, the bump electrodes 1-2 are formed.
Is penetrated through the thermosetting resin layer 2-1 and comes into contact with the synthetic resin film 2-2, and an appropriate amount of the thermosetting resin protrudes around the periphery of the bonding area, leaving no void on the bonding surface. It is determined as follows. Strictly speaking, the upper limit and the lower limit of the thickness T of the thermosetting resin layer 2-1 are the size, shape, number, total volume and distribution state of the bump electrodes 1-2 formed on the printed wiring board 1, as well as heat. Although determined by the hardness of the curable resin layer or the like, the above condition can be satisfied for a generally used printed wiring board by making the height H substantially equal to the height H of the bump electrode 1-2. .

【0010】量産プラントにおいては、熱硬化性樹脂層
2−1の厚さTを常時完全にバンプ電極1−2の高さH
と同一値に保持することは困難である。然しながら、熱
硬化性樹脂層2−1の厚さTを、バンプ電極1−2の高
さHの±30μm以内とすれば、殆ど全てのプリント配
線基板1に対して良好な結果が得られることが判明し
た。熱硬化性樹脂層2−1の厚さTの更に望ましい値
は、バンプ電極1−2の高さH±15μm以内である。
熱硬化性樹脂層の厚みTがこの範囲にあると、装着用シ
ート2の圧着が容易であり、適切な圧着力でバンプ電極
の先端を合成樹脂フィルム2−2に接触させることがで
き、かつ、貼着面にボイドが残らず、貼着領域の周縁に
はみ出す熱硬化性樹脂も適量に留まる。
In a mass production plant, the thickness T of the thermosetting resin layer 2-1 is always completely set to the height H of the bump electrode 1-2.
It is difficult to keep the same value as However, if the thickness T of the thermosetting resin layer 2-1 is within ± 30 μm of the height H of the bump electrode 1-2, good results can be obtained for almost all the printed wiring boards 1. There was found. A more desirable value of the thickness T of the thermosetting resin layer 2-1 is within a height H ± 15 μm of the bump electrode 1-2.
When the thickness T of the thermosetting resin layer is within this range, the mounting sheet 2 can be easily pressed, and the tip of the bump electrode can be brought into contact with the synthetic resin film 2-2 with an appropriate pressing force. In addition, no void remains on the sticking surface, and an appropriate amount of the thermosetting resin that protrudes to the periphery of the sticking region also remains.

【0011】熱硬化性樹脂層の厚みTが、バンプ電極の
高さH+30μmを超えると、装着用シート2をプリン
ト配線基板に圧着した際、バンプ電極が熱硬化性樹脂層
を貫通せず、半導体チップの端子との接続が不充分とな
る恐れがある上、貼着領域の周縁にはみ出す熱硬化性樹
脂量が過大になり不都合を生じる。又逆に、その厚みT
が、H−30μm以下となると、半導体チップとプリン
ト配線基板との間隙を熱硬化性樹脂により十分に埋める
ことが出来ず、ボイドの発生する恐れが生じる。
When the thickness T of the thermosetting resin layer exceeds the height H of the bump electrode + 30 μm, when the mounting sheet 2 is pressed against the printed wiring board, the bump electrode does not penetrate the thermosetting resin layer, and There is a possibility that the connection with the terminal of the chip may be insufficient, and the amount of the thermosetting resin protruding to the peripheral edge of the sticking area becomes excessive, which causes inconvenience. Conversely, its thickness T
However, if the thickness is less than or equal to 30 μm, the gap between the semiconductor chip and the printed wiring board cannot be sufficiently filled with the thermosetting resin, and there is a possibility that voids may be generated.

【0012】熱硬化性樹脂層2−1を構成するエポキシ
樹脂組成物としては、単官能エポキシ樹脂、ビスフェノ
ールA型エポキシ樹脂、ビスフェノールF型エポキシ樹
脂、フェノールノボラック型エポキシ樹脂、クレゾール
ノボラック型エポキシ樹脂等の多官能エポキシ樹脂及び
これらの臭素化物の1種又は2種以上から成るエポキシ
樹脂と、多価フェノール化合物、尿素誘導体、アミン化
合物、イミダゾール化合物、変性アミン化合物、変性イ
ミダゾール化合物、酸無水物の1種又は2種以上を混合
して得た硬化剤より成る組成物が推奨される。
The epoxy resin composition constituting the thermosetting resin layer 2-1 includes a monofunctional epoxy resin, a bisphenol A epoxy resin, a bisphenol F epoxy resin, a phenol novolak epoxy resin, a cresol novolak epoxy resin, and the like. And polyepoxy resins comprising one or more of these bromides; and polyhydric phenol compounds, urea derivatives, amine compounds, imidazole compounds, modified amine compounds, modified imidazole compounds, and acid anhydrides. A composition comprising a curing agent obtained by mixing seeds or two or more is recommended.

【0013】この組成物には、結晶シリカ、溶融シリ
カ、アルミナ、窒化アルミ、窒化ボロン、窒化珪素、マ
グネシア、マグネシウムシリケートなどの無機質充填
材、ゴム成分、粘性調整剤、難燃剤などを加えても良
い。無機質充填材の添加量は、50重量%以上が好まし
く、それ以下では熱膨張係数の低減効果、熱伝導効果が
乏しくなり、信頼性が低下する。尚、この組成物として
は、プリント配線基板のバンプ電極と半導体チップの端
子との接合温度より低い硬化温度を有するものが強く推
奨される。硬化温度が接合温度より高いと、接合後に接
合温度より高い温度での熱処理が必要となるので、工程
が煩雑となるばかりでなく、接合部の信頼性の低下を招
くからである。このエポキシ樹脂組成物は、通常、溶剤
にて適正な粘度に調整され、適宜の合成樹脂フィルムに
塗布、乾燥せしめられ、熱硬化性樹脂層を形成する。
The composition may contain inorganic fillers such as crystalline silica, fused silica, alumina, aluminum nitride, boron nitride, silicon nitride, magnesia, magnesium silicate, etc., rubber components, viscosity modifiers, flame retardants, etc. good. The addition amount of the inorganic filler is preferably 50% by weight or more, and if it is less than that, the effect of reducing the thermal expansion coefficient and the effect of heat conduction are poor, and the reliability is reduced. It is strongly recommended that the composition has a curing temperature lower than the bonding temperature between the bump electrode of the printed wiring board and the terminal of the semiconductor chip. If the curing temperature is higher than the bonding temperature, a heat treatment at a temperature higher than the bonding temperature is required after the bonding, which not only complicates the process but also lowers the reliability of the bonded portion. This epoxy resin composition is usually adjusted to an appropriate viscosity with a solvent, applied to an appropriate synthetic resin film, and dried to form a thermosetting resin layer.

【0014】合成樹脂フィルム2−2は、単に熱硬化性
樹脂層のキャリアーに過ぎないので、材質などには特段
の限定はないが、上記熱硬化性樹脂組成物の硬化温度よ
り低いガラス転移温度を有する熱可塑性樹脂、例えば、
ポリエチレン、ポリプロピレン等のポリオレフィン、エ
チレン酢酸ビニル共重合体、エチレン−アルキルアクリ
レート共重合体、ポリエステル、ポリ塩化ビニール、ポ
リ塩化ビニリデン、ポリウレタン、ポリアミド、ポリア
ミドイミド、ポリエーテルイミド、ポリスルホン、ポリ
エーテルスルホン、メチルペンテンコポリマー等により
作製された熱可塑性のフィルムが採用できる。フィルム
の厚さは特に限定しないが、通常30〜500μmの厚
さで使用される。
The synthetic resin film 2-2 is merely a carrier of the thermosetting resin layer, and thus there is no particular limitation on the material and the like, but the glass transition temperature is lower than the curing temperature of the thermosetting resin composition. A thermoplastic resin having, for example,
Polyolefins such as polyethylene and polypropylene, ethylene vinyl acetate copolymer, ethylene-alkyl acrylate copolymer, polyester, polyvinyl chloride, polyvinylidene chloride, polyurethane, polyamide, polyamideimide, polyetherimide, polysulfone, polyethersulfone, methyl A thermoplastic film made of a pentene copolymer or the like can be used. Although the thickness of the film is not particularly limited, it is usually used at a thickness of 30 to 500 μm.

【0015】この装着用シート2は、図2及び図3に示
すように、その熱硬化性樹脂層2−1をプリント配線基
板1のバンプ電極1−2が設けられている面に貼り合わ
される。貼り合わせる方法は特に限定されないが、通常
ロールラミネーション、プレスラミネーションにより行
われる。貼り合せは、硬化前の熱硬化性樹脂層の軟化温
度以上、硬化温度以下にて行われる。従って、この段階
では熱硬化性樹脂層2−1は硬化前の状態である。この
貼り合せ工程により、プリント配線基板のバンプ電極1
−2は、装着用シートの熱硬化性樹脂層2−1を貫通
し、それらの先端が合成樹脂フィルム2−2に接触し、
場合によってはその表面を強く押圧するようになる。
As shown in FIGS. 2 and 3, the mounting sheet 2 has its thermosetting resin layer 2-1 bonded to the surface of the printed wiring board 1 on which the bump electrodes 1-2 are provided. . The bonding method is not particularly limited, but is usually performed by roll lamination or press lamination. The bonding is performed at a temperature equal to or higher than the softening temperature of the thermosetting resin layer before hardening and equal to or lower than the curing temperature. Therefore, at this stage, the thermosetting resin layer 2-1 is in a state before being cured. By this bonding step, the bump electrode 1 of the printed wiring board is formed.
-2 penetrates the thermosetting resin layer 2-1 of the mounting sheet, and their ends contact the synthetic resin film 2-2;
In some cases, the surface is strongly pressed.

【0016】次いで、装着用シート2の合成樹脂フィル
ム2−2を引き剥がす。図4は、合成樹脂フィルム2−
2が完全に取り除かれた状態を示す。このとき、バンプ
電極1−2の先端は、熱硬化性樹脂層2−1の表面より
露出した状態となっている。最後に、図5に示す如く、
フェースダウン方式で、プリント配線基板の各バンプ電
極1−2を、半導体チップ3のそれぞれ対応する端子3
−2と正しく対面、接触させるよう位置決めし、熱圧に
より、更には必要に応じ超音波振動を与えることにより
接合を行う。熱硬化性樹脂層2−1の樹脂組成物は、接
合時加えられた熱により軟化し、然る後、硬化し、半導
体チップ3とプリント配線基板1の間に強固な硬化樹脂
層を形成する。このように接合した後に、必要に応じて
熱処理を加えても構わないが、その場合、接合温度より
低い温度であることが必要である。
Next, the synthetic resin film 2-2 of the mounting sheet 2 is peeled off. FIG. 4 shows a synthetic resin film 2-
2 shows a state where it has been completely removed. At this time, the tip of the bump electrode 1-2 is exposed from the surface of the thermosetting resin layer 2-1. Finally, as shown in FIG.
In the face-down method, each bump electrode 1-2 of the printed wiring board is connected to the corresponding terminal 3 of the semiconductor chip 3.
-2 is positioned so as to face and contact correctly, and bonding is performed by applying heat and pressure and, if necessary, ultrasonic vibration. The resin composition of the thermosetting resin layer 2-1 is softened by the heat applied at the time of joining, and then hardens to form a strong cured resin layer between the semiconductor chip 3 and the printed wiring board 1. . After joining in this manner, heat treatment may be applied as necessary, but in this case, the temperature must be lower than the joining temperature.

【0017】以下、本発明方法により、実際に市販され
ている半導体チップを、プリント基板に実装する実施例
を示す。 〔実施例1〕フェノールノボラック型エポキシ樹脂、ビ
スフェノールF型エポキシ樹脂、フェノールノボラック
樹脂、尿素誘導体からなるエポキシ樹脂組成物100重
量部に、球状アルミナ260重量部と溶剤を加えて混練
分散し、得られた硬化温度160℃のエポキシ樹脂組成
物を、ガラス転移温度−20℃、厚み100μmのエチ
レン酢酸ビニル共重合体フィルムに塗付、乾燥し、半導
体チップ装着用シートを得た。熱硬化性樹脂層の厚みは
90μmであった。
Hereinafter, an embodiment of mounting a commercially available semiconductor chip on a printed circuit board by the method of the present invention will be described. [Example 1] 260 parts by weight of spherical alumina and a solvent were added to 100 parts by weight of an epoxy resin composition composed of a phenol novolak type epoxy resin, a bisphenol F type epoxy resin, a phenol novolak resin, and a urea derivative, and kneaded and dispersed. The epoxy resin composition having a curing temperature of 160 ° C. was applied to an ethylene-vinyl acetate copolymer film having a glass transition temperature of −20 ° C. and a thickness of 100 μm and dried to obtain a semiconductor chip mounting sheet. The thickness of the thermosetting resin layer was 90 μm.

【0018】この装着用シートを、装着すべき半導体チ
ップの大きさに打ち抜き、共晶ハンダペースト印刷、リ
フローにより高さ100μmのバンプ電極が100箇所
に形成されたプリント配線基板のバンプ電極面にプレス
により貼り付けを行った。貼り付け温度は80℃であっ
た。その後、このプリント配線基板から装着用シートの
エチレン酢酸ビニル共重合体フィルムを剥し取って、バ
ンプ電極の先端を露出させ、バンプ電極と半導体チップ
の端子との位置合わせを行い、220℃で2分間加熱加
圧を行って、両者を接合すると同時に、熱硬化性樹脂層
を硬化させた。接合後、更に180℃にて1時間熱処理
し熱硬化性樹脂の硬化を完了させた。このときのプリン
ト配線基板のバンプ電極と半導体チップの端子の接合は
100箇所とも良好であり、−55℃と125℃の温度
サイクル試験1000サイクル後も接続部の破断は生じ
なかった。
This mounting sheet is punched into the size of a semiconductor chip to be mounted, pressed by eutectic solder paste printing, and pressed on a bump electrode surface of a printed wiring board on which bump electrodes having a height of 100 μm are formed at 100 locations by reflow. Was applied. The sticking temperature was 80 ° C. Thereafter, the ethylene vinyl acetate copolymer film of the mounting sheet is peeled off from the printed wiring board, the tip of the bump electrode is exposed, and the position of the bump electrode and the terminal of the semiconductor chip is adjusted. Heat and pressure were applied to join the two, and at the same time, the thermosetting resin layer was cured. After joining, heat treatment was further performed at 180 ° C. for 1 hour to complete the curing of the thermosetting resin. At this time, the bonding between the bump electrode of the printed wiring board and the terminal of the semiconductor chip was good at all 100 points, and the connection portion did not break even after 1000 cycles of the temperature cycle test at −55 ° C. and 125 ° C.

【0019】〔実施例2〕クレゾールノボラック型エポ
キシ樹脂、ビスフェノールA型エポキシ樹脂、酸無水
物、窒化アルミ、溶剤から成る硬化温度180℃の熱硬
化性樹脂組成物を、ガラス転移温度70℃、厚さ50μ
mのポリエステルフィルムに塗布、乾燥し、半導体チッ
プ装着用シートを得た。熱硬化性樹脂層の厚みは165
μmであった。この装着用シートを、装着すべき半導体
チップの大きさに打ち抜き、金ワイアのボールボンディ
ングにより形成された高さ120μmのバンプ電極を1
00箇所に有するプリント配線基板に、熱ロールによる
ラミネートにより120℃で貼り付けた。その後、この
プリント配線基板から装着用シートのポリエステルフィ
ルムを剥し取って、バンプ電極の先端を露出させ、バン
プ電極と半導体チップの端子との位置合わせを行い、3
00℃にて30秒間超音波振動を与えつつ加熱加圧を行
い、両者を接合すると同時に熱硬化性樹脂層を硬化させ
た。このときのプリント配線基板のバンプ電極と半導体
チップの端子の接合は100箇所とも良好であり、−5
5℃と125℃の温度サイクル試験1000サイクル後
も接続部の破断は生じなかった。
Example 2 A thermosetting resin composition comprising a cresol novolak type epoxy resin, a bisphenol A type epoxy resin, an acid anhydride, aluminum nitride, and a solvent at a curing temperature of 180 ° C. was prepared. 50μ
m, and dried by drying to obtain a semiconductor chip mounting sheet. The thickness of the thermosetting resin layer is 165
μm. This mounting sheet is punched into a size of a semiconductor chip to be mounted, and a bump electrode having a height of 120 μm formed by ball bonding of gold wires is formed on each of the semiconductor chips.
It was attached to a printed circuit board at 00 at 120 ° C. by lamination using a hot roll. Thereafter, the polyester film of the mounting sheet is peeled off from the printed wiring board, the tip of the bump electrode is exposed, and the bump electrode and the terminal of the semiconductor chip are aligned.
Heat and pressure were applied while applying ultrasonic vibration at 00 ° C. for 30 seconds to join the two and simultaneously cure the thermosetting resin layer. At this time, the bonding between the bump electrode of the printed wiring board and the terminal of the semiconductor chip was good at all 100 points, and -5
After 1000 cycles of the temperature cycle test at 5 ° C. and 125 ° C., the connection did not break.

【0020】〔比較例1〕実施例1にて用いた熱硬化性
樹脂組成物をシート状に成形し、実施例1で使用した個
片の半導体チップとプリント配線基板の間に直接挟み、
80℃にて加熱圧した後、220℃に昇温し接合を行っ
た。プリント配線基板のバンプ電極と半導体チップの端
子との接続部は、17箇所が不良となった。
[Comparative Example 1] The thermosetting resin composition used in Example 1 was molded into a sheet, and directly sandwiched between the individual semiconductor chips used in Example 1 and the printed wiring board.
After heating and pressing at 80 ° C., the temperature was raised to 220 ° C. to perform joining. In the connection portion between the bump electrode of the printed wiring board and the terminal of the semiconductor chip, 17 locations were defective.

【0021】[0021]

【発明の効果】本発明は叙上の如く構成されるから、本
発明によるときは、工程が単純で、コストが掛らず、し
かもプリント配線基板のバンプ電極が確実に半導体チッ
プの端子に接続され、接続不良等の問題を生じることの
ない新規な半導体チップ実装方法及びその方法の実施に
用いる装着用シートを提供することができる。
Since the present invention is constructed as described above, according to the present invention, the process is simple, the cost is low, and the bump electrodes of the printed wiring board are securely connected to the terminals of the semiconductor chip. In addition, it is possible to provide a novel semiconductor chip mounting method which does not cause a problem such as a connection failure and a mounting sheet used for carrying out the method.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 プリント配線基板の構成中、本発明に関係す
る部分を示す一部拡大断面図である。
FIG. 1 is a partially enlarged cross-sectional view showing a portion related to the present invention in a configuration of a printed wiring board.

【図2】 半導体チップ装着用シートの一部拡大断面図
である。
FIG. 2 is a partially enlarged sectional view of a semiconductor chip mounting sheet.

【図3】 プリント配線基板のバンプ電極側のフェース
面上に半導体チップ装着用シートを貼り合わせた状態を
示す一部拡大断面である。
FIG. 3 is a partially enlarged cross-sectional view showing a state in which a semiconductor chip mounting sheet is bonded to a face side of a printed wiring board on a bump electrode side.

【図4】 装着用シートの合成樹脂フィルムを完全に引
き剥がした状態を示す一部拡大断面図である。
FIG. 4 is a partially enlarged cross-sectional view showing a state where the synthetic resin film of the mounting sheet is completely peeled off.

【図5】 図4に示されたプリント配線基板に、フェー
スダウン方式により半導体チップを実装した状態を示す
一部拡大断面図である。
FIG. 5 is a partially enlarged cross-sectional view showing a state where a semiconductor chip is mounted on the printed wiring board shown in FIG. 4 by a face-down method.

【符号の説明】[Explanation of symbols]

1 プリント配線基板 1−1 基板 1−2 バンプ電極 2 半導体チップ装着用シート 2−1 熱硬化性樹脂層 2−2 合成樹脂フィルム 3 半導体チップ 3−1 基板 3−2 端子 DESCRIPTION OF SYMBOLS 1 Printed wiring board 1-1 Substrate 1-2 Bump electrode 2 Semiconductor chip mounting sheet 2-1 Thermosetting resin layer 2-2 Synthetic resin film 3 Semiconductor chip 3-1 Substrate 3-2 Terminal

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 下記のステップ〔a〕〜〔e〕を含むこ
とを特徴とする、プリント配線基板(1)に半導体チッ
プ(3)を装着する方法。 〔a〕合成樹脂フィルム(2−2)の一方の面に、プリ
ント配線基板(1)のバンプ電極(1−2)の高さHと
同一程度の厚みTを有する熱硬化性樹脂層(2−1)を
設けて成る半導体チップ装着用シート(2)を製造する
ステップ。 〔b〕プリント配線基板(1)のバンプ電極(1−2)
が設けられた面に、上記半導体チップ装着用シート
(2)の熱硬化性樹脂層(2−1)を圧着するステッ
プ。 〔c〕プリント配線基板(1)のバンプ電極面に圧着し
た半導体チップ装着用シート(2)の合成樹脂フィルム
(2−2)を引き剥がすステップ。 〔d〕プリント配線基板(1)のバンプ電極(1−2)
が、対応する半導体チップ(3)上の端子(3−2)に
正しく対面し、接触するよう位置決めするステップ。 〔e〕プリント配線基板(1)のバンプ電極(1−2)
を、半導体チップ(3)上の対応する端子(3−2)に
接合すると共に、熱硬化性樹脂(2−1)を加熱硬化す
るステップ。
1. A method for mounting a semiconductor chip (3) on a printed wiring board (1), comprising the following steps [a] to [e]. [A] On one surface of the synthetic resin film (2-2), a thermosetting resin layer (2) having the same thickness T as the height H of the bump electrode (1-2) of the printed wiring board (1). Manufacturing a semiconductor chip mounting sheet (2) provided with -1). [B] Bump electrode (1-2) of printed wiring board (1)
Pressure bonding the thermosetting resin layer (2-1) of the semiconductor chip mounting sheet (2) to the surface provided with. [C] a step of peeling off the synthetic resin film (2-2) of the semiconductor chip mounting sheet (2) pressed against the bump electrode surface of the printed wiring board (1). [D] Bump electrode (1-2) of printed wiring board (1)
Is positioned so as to correctly face and contact the terminal (3-2) on the corresponding semiconductor chip (3). [E] Bump electrode (1-2) of printed wiring board (1)
Bonding to the corresponding terminals (3-2) on the semiconductor chip (3) and heat-curing the thermosetting resin (2-1).
【請求項2】 合成樹脂フィルム(2−2)の一方の面
に、プリント配線基板(1)のバンプ電極(1−2)の
高さHと同一程度の厚みTを有する熱硬化性樹脂層(2
−1)を設けて成ることを特徴とする、請求項1に記載
のプリント配線基板に半導体チップを装着する方法の実
施に用いる半導体チップ装着用シート(2)。
2. A thermosetting resin layer having a thickness T substantially equal to the height H of the bump electrode (1-2) of the printed wiring board (1) on one surface of the synthetic resin film (2-2). (2
The semiconductor chip mounting sheet (2) used for carrying out the method for mounting a semiconductor chip on a printed wiring board according to claim 1, characterized in that the sheet (2) is provided.
【請求項3】 合成樹脂フィルム(2−2)が、熱硬化
性樹脂(2−1)の硬化温度より低いガラス転移温度を
有する、請求項2に記載の半導体チップ装着用シート
(2)。
3. The semiconductor chip mounting sheet (2) according to claim 2, wherein the synthetic resin film (2-2) has a glass transition temperature lower than the curing temperature of the thermosetting resin (2-1).
【請求項4】 熱硬化性樹脂(2−1)がエポキシ樹脂
組成物より成り、そのエポキシ樹脂組成物が、プリント
配線基板(1)のバンプ電極(1−2)と半導体チップ
(3)の端子(3−2)の接合温度より低い硬化温度を
有する、請求項2又は3に記載の半導体チップ装着用シ
ート(2)。
4. The thermosetting resin (2-1) is made of an epoxy resin composition, and the epoxy resin composition is used for forming a bump electrode (1-2) on a printed wiring board (1) and a semiconductor chip (3). The semiconductor chip mounting sheet (2) according to claim 2 or 3, having a curing temperature lower than a bonding temperature of the terminal (3-2).
【請求項5】 熱硬化性樹脂(2−1)が、50重量%
以上の無機質充填材を含む、請求項2乃至4の何れか一
に記載の半導体チップ装着用シート(2)。
5. The thermosetting resin (2-1) contains 50% by weight.
The semiconductor chip mounting sheet (2) according to any one of claims 2 to 4, comprising the above inorganic filler.
【請求項6】 熱硬化性樹脂層(2−1)の厚みT(単
位μm。以下同様。)が、装着すべきプリント配線基板
(1)のバンプ電極(1−2)の高さをHとしたとき、
H−30≦T≦H+30の範囲内にある、請求項2乃至5の
何れか一に記載の半導体チップ装着用シート(2)。
6. The thickness T (unit: μm; the same applies hereinafter) of the thermosetting resin layer (2-1) is set so that the height of the bump electrode (1-2) of the printed wiring board (1) to be mounted is H. And when
The semiconductor chip mounting sheet (2) according to any one of claims 2 to 5, wherein H-30≤T≤H + 30.
JP2000310211A 2000-10-11 2000-10-11 Method of mounting a semiconductor chip on a printed wiring board Expired - Fee Related JP4441090B2 (en)

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Application Number Priority Date Filing Date Title
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JP4441090B2 JP4441090B2 (en) 2010-03-31

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004047772A (en) * 2002-07-12 2004-02-12 Matsushita Electric Ind Co Ltd Electronic component bonding material and method of mounting the electronic component
JP2006128567A (en) * 2004-11-01 2006-05-18 Three M Innovative Properties Co Method of connecting semiconductor package to printed wiring board
JP2006261529A (en) * 2005-03-18 2006-09-28 Lintec Corp Underfill tape for flip chip mount and manufacturing method of semiconductor device
JP2009259924A (en) * 2008-04-15 2009-11-05 Shinko Electric Ind Co Ltd Method of manufacturing semiconductor device
JP2011243922A (en) * 2010-05-21 2011-12-01 Murata Mfg Co Ltd Method of manufacturing electronic component module

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004047772A (en) * 2002-07-12 2004-02-12 Matsushita Electric Ind Co Ltd Electronic component bonding material and method of mounting the electronic component
JP2006128567A (en) * 2004-11-01 2006-05-18 Three M Innovative Properties Co Method of connecting semiconductor package to printed wiring board
JP2006261529A (en) * 2005-03-18 2006-09-28 Lintec Corp Underfill tape for flip chip mount and manufacturing method of semiconductor device
JP2009259924A (en) * 2008-04-15 2009-11-05 Shinko Electric Ind Co Ltd Method of manufacturing semiconductor device
JP2011243922A (en) * 2010-05-21 2011-12-01 Murata Mfg Co Ltd Method of manufacturing electronic component module

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