JP3155811B2 - Method for manufacturing resin-encapsulated semiconductor device - Google Patents

Method for manufacturing resin-encapsulated semiconductor device

Info

Publication number
JP3155811B2
JP3155811B2 JP07487092A JP7487092A JP3155811B2 JP 3155811 B2 JP3155811 B2 JP 3155811B2 JP 07487092 A JP07487092 A JP 07487092A JP 7487092 A JP7487092 A JP 7487092A JP 3155811 B2 JP3155811 B2 JP 3155811B2
Authority
JP
Japan
Prior art keywords
resin
sealing
semiconductor element
metal layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP07487092A
Other languages
Japanese (ja)
Other versions
JPH05283453A (en
Inventor
章 善積
英男 太田
カオ・ミン・タイ
新悦 藤枝
道也 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP07487092A priority Critical patent/JP3155811B2/en
Priority to KR1019930005371A priority patent/KR0124494B1/en
Publication of JPH05283453A publication Critical patent/JPH05283453A/en
Application granted granted Critical
Publication of JP3155811B2 publication Critical patent/JP3155811B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は樹脂封止をインラインで
行うことが可能な樹脂封止型半導体装置の製造方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a resin-sealed semiconductor device capable of performing in-line resin sealing.

【0002】[0002]

【従来の技術】樹脂封止型半導体装置は、これまで一般
的には、トランスファー成形法により半導体素子を樹脂
封止することによって製造されている。これは、例えば
エポキシ樹脂および無機充填剤などを主体としたエポキ
シ成形材料の粉末からなるタブレットを加熱して溶融さ
せ、トランスファー成形機を用いて金型に注入して高温
高圧状態で成形し、硬化されたエポキシ樹脂組成物によ
って半導体素子を樹脂封止する方法である。
2. Description of the Related Art Resin-sealed semiconductor devices have hitherto been generally manufactured by resin-sealing semiconductor elements by a transfer molding method. This is done by heating and melting a tablet made of, for example, an epoxy molding material powder mainly composed of an epoxy resin and an inorganic filler, injecting it into a mold using a transfer molding machine, molding at a high temperature and high pressure, and curing. This is a method of resin-sealing a semiconductor element with the obtained epoxy resin composition.

【0003】ところで、樹脂封止型半導体装置のパッケ
ージは、最近大型化と薄型化の傾向を強めており、この
傾向は上述したようなトランスファー成形法の使用を困
難なものにしている。さらに最近ではパッケージの種類
が多様化して、小品種大量生産から多品種少量生産へと
移り変わりつつあり、トランスファー成形法は基本的に
多品種少量生産のようなフレキシブルな生産様式には適
していないことから、トランスファー成形法に代わる新
たな方法が現在求められている。
[0003] By the way, packages of resin-encapsulated semiconductor devices have recently been increasing in size and decreasing in thickness, and this tendency has made it difficult to use the transfer molding method as described above. More recently, the variety of packages has been diversifying, and the shift from small-volume, high-volume production to multi-volume, small-volume production has been made. Transfer molding is basically not suitable for flexible production styles, such as multi-volume, small-volume production. Therefore, a new method replacing the transfer molding method is currently required.

【0004】これに対し特開平3−265162号に
は、金属層とこの両面に形成された樹脂層とを具備した
封止用絶縁体を半導体素子に加熱圧着して樹脂封止する
ことにより、樹脂封止型半導体装置を製造する技術が開
示されている。図15(a)、(b)に、この樹脂封止
型半導体装置の製造プロセスおよび封止後の断面図を示
す。すなわちこのような方法では、まず図15(a)に
示すように、樹脂層14、金属層15および樹脂層16
をこの順に積層した2枚の封止用絶縁体17を樹脂層1
4が対向するように配置し、これらの封止用絶縁体17
の間に、バンプ18でフィルムキャリア19とボンディ
ングされたTAB(テープ オートメーティッド ボン
ディング)タイプの半導体素子20を配置する。次い
で、2枚の封止用絶縁体17の樹脂層14をプレート加
熱または赤外線加熱などにより加熱して軟化溶融状態と
して、半導体素子20を2枚の封止用絶縁体17で挟み
込んで圧着する。こうしたプロセスにより、図15
(b)に示すように半導体素子20が樹脂層14内に封
止され、その外側に金属層15および樹脂層16が配置
された樹脂封止型半導体装置が得られる。このような方
法によれば、樹脂封止をインラインで行うことが可能と
なるうえ、多品種の半導体素子20を樹脂封止する場合
も、その都度構造、形状などの異なる封止用絶縁体17
を供給するだけでフレキシブルに対応でき、しかもパッ
ケージの大型化、薄型化にも適している。しかしなが
ら、上述したような樹脂封止型半導体装置においては、
封止用絶縁体17中に金属層15と樹脂層14、16と
の界面が存在するため、この界面での剥離が発生しやす
いという問題点があった。
On the other hand, Japanese Patent Application Laid-Open No. 3-265162 discloses that a sealing insulator having a metal layer and a resin layer formed on both surfaces thereof is heat-pressed to a semiconductor element and sealed with a resin. A technique for manufacturing a resin-sealed semiconductor device has been disclosed. FIGS. 15A and 15B show a manufacturing process of the resin-sealed semiconductor device and cross-sectional views after sealing. That is, in such a method, first, as shown in FIG. 15A, the resin layer 14, the metal layer 15, and the resin layer 16 are formed.
Are laminated in this order, and two sealing insulators 17 are formed on the resin layer 1.
4 so as to face each other, and these sealing insulators 17 are provided.
A TAB (tape automated bonding) type semiconductor element 20 bonded to a film carrier 19 by a bump 18 is arranged between the bumps 18. Subsequently, the resin layer 14 of the two sealing insulators 17 is heated by plate heating or infrared heating to a softened and molten state, and the semiconductor element 20 is sandwiched between the two sealing insulators 17 and pressed. By such a process, FIG.
As shown in (b), a resin-sealed semiconductor device in which the semiconductor element 20 is sealed in the resin layer 14 and the metal layer 15 and the resin layer 16 are disposed outside the semiconductor element 20 is obtained. According to such a method, resin sealing can be performed in-line, and even when many types of semiconductor elements 20 are sealed with resin, the sealing insulators 17 having different structures, shapes, etc. each time.
Can be flexibly handled simply by supplying the package, and is also suitable for making the package larger and thinner. However, in the resin-encapsulated semiconductor device as described above,
Since the interface between the metal layer 15 and the resin layers 14 and 16 is present in the sealing insulator 17, there has been a problem that separation at the interface is likely to occur.

【0005】[0005]

【発明が解決しようとする課題】以上のように従来の樹
脂封止型半導体装置では、封止用絶縁体の金属層と樹脂
層との界面における剥離の発生が問題となっていた。特
に、ASIC(Application Specif
ic IC)などのゲートアレイやスタンダードセル方
式LSIに代表される表面実装型パッケージの場合、樹
脂封止型半導体装置を基板に実装する際に、ベーパーフ
ェイズリフロー、赤外線リフロー、半田浸漬などの工程
において高温(215〜260℃)にさらされる。この
ため、パッケージ内部に吸湿されていた水分が金属層と
樹脂層との界面で爆発的にガス化しようとして高圧が加
わり、結果として、金属層と樹脂層との界面が剥離して
パッケージクラックが発生するなど樹脂封止型半導体装
置の信頼性を低下させていた。
As described above, in the conventional resin-encapsulated semiconductor device, there has been a problem that separation occurs at the interface between the metal layer and the resin layer of the sealing insulator. In particular, ASIC (Application Specialization)
In the case of a surface mount type package typified by a gate array such as a ic IC) or a standard cell type LSI, when a resin-encapsulated semiconductor device is mounted on a substrate, a process such as vapor phase reflow, infrared reflow, and solder immersion is performed. Exposure to high temperatures (215-260 ° C). For this reason, the moisture absorbed inside the package is explosively gasified at the interface between the metal layer and the resin layer, and a high pressure is applied. As a result, the interface between the metal layer and the resin layer is separated, and a package crack occurs. For example, the reliability of the resin-encapsulated semiconductor device is reduced.

【0006】本発明の目的は、表面実装時などのパッケ
ージクラックの発生が抑えられ、耐湿信頼性が高く、か
つ大型化、薄型化への対応が容易な樹脂封止型半導体装
の製造方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a resin-encapsulated semiconductor device which suppresses the occurrence of package cracks during surface mounting and the like, has high moisture resistance reliability, and can easily cope with an increase in size and thickness. To provide.

【0007】[0007]

【課題を解決するための手段】本発明の樹脂封止型半導
体装置の製造方法は、貫通孔を有する金属層と前記金属
層の両面に形成された樹脂層とを具備した封止用絶縁体
を形成する工程と、前記封止用絶縁体と半導体素子とを
重ねて配置する工程と、重ねて配置された前記封止用絶
縁体を加熱加圧することにより前記半導体素子を樹脂封
止する工程とを有し、前記金属層の貫通孔は前記半導体
素子の能動面と対向する位置をはずして設けられている
ことを特徴とする。
According to the present invention, there is provided a method of manufacturing a resin-sealed semiconductor device, comprising: a sealing insulator having a metal layer having a through hole and resin layers formed on both surfaces of the metal layer. forming a step and a step of placing overlapping with said sealing insulator and the semiconductor element, insulation for the seal which is arranged to overlap
And a step of the semiconductor element is resin-sealed by heating and pressing the Entai, through hole of the metal layer is a semiconductor
It is characterized by being provided at a position facing the active surface of the element .

【0008】本発明において、封止用絶縁体を構成する
樹脂層に用いられる樹脂は、得られる樹脂封止型半導体
装置の信頼性を確保するために、電気絶縁抵抗が大きい
こと、吸湿性が小さいこと、耐熱性が高いこと、強度が
高いこと、接着性が高いこと、などが要求される。この
ような樹脂としては、ポリイミド樹脂、エポキシ樹脂、
不飽和ポリエステル樹脂、フェノール樹脂、マレイミド
樹脂、メラミン樹脂、ユリア樹脂、ジアリルフタレート
樹脂、シリコーン樹脂、フラン樹脂、キシレン−ホルム
アルデヒド樹脂、ケトン−ホルムアルデヒド樹脂、アニ
リン樹脂、アルキド樹脂、トリアリルシアヌレート樹
脂、アクロレイン樹脂、トリアジン系樹脂、ジシクロペ
ンタジエン系樹脂などの熱硬化性樹脂が挙げられる。こ
の他に、熱可塑性樹脂、エンジニアリングプラスチック
スを用いてもよい。
In the present invention, the resin used for the resin layer constituting the sealing insulator has a large electric insulation resistance and a good hygroscopic property in order to secure the reliability of the obtained resin-sealed semiconductor device. Smallness, high heat resistance, high strength, high adhesiveness, and the like are required. Such resins include polyimide resins, epoxy resins,
Unsaturated polyester resin, phenol resin, maleimide resin, melamine resin, urea resin, diallyl phthalate resin, silicone resin, furan resin, xylene-formaldehyde resin, ketone-formaldehyde resin, aniline resin, alkyd resin, triallyl cyanurate resin, acrolein Thermosetting resins such as resin, triazine-based resin, and dicyclopentadiene-based resin are exemplified. In addition, a thermoplastic resin or engineering plastics may be used.

【0009】これらの樹脂には、樹脂層の熱膨張率を調
整しかつ強度を向上するために、各種の繊維、クロス、
または無機もしくは有機充填材を添加してもよい。繊維
としては、ガラス繊維や石英繊維などの無機繊維、ナイ
ロン、ポリエステル、フェノールなどの有機繊維が挙げ
られる。クロスとしては、ガラスクロス、炭素繊維クロ
ス、ポリアミド繊維クロスなどの各種の織布が挙げられ
る。無機充填材としては、石英粉末、溶融シリカ粉末、
球状溶融シリカ、チッ化ケイ素、チッ化アルミ、炭化ケ
イ素などが挙げられる。有機充填材としては、フェノー
ル樹脂硬化粉末、ポリイミド樹脂硬化粉末などが挙げら
れる。
In order to adjust the coefficient of thermal expansion of the resin layer and improve the strength, these resins include various fibers, cloths,
Alternatively, an inorganic or organic filler may be added. Examples of the fibers include inorganic fibers such as glass fibers and quartz fibers, and organic fibers such as nylon, polyester, and phenol. Examples of the cloth include various woven fabrics such as a glass cloth, a carbon fiber cloth, and a polyamide fiber cloth. As the inorganic filler, quartz powder, fused silica powder,
Examples include spherical fused silica, silicon nitride, aluminum nitride, and silicon carbide. Examples of the organic filler include phenol resin cured powder, polyimide resin cured powder, and the like.

【0010】さらにこれらの樹脂には、必要に応じて、
シリコーンゴム、MBSゴムなどのゴム、エラストマー
を始めとする耐クラック性向上剤、ハロゲン系や三酸化
アンチモンなどの難燃化剤、などを添加することができ
る。
[0010] Further, if necessary, these resins
Rubbers such as silicone rubber and MBS rubber, crack resistance improvers such as elastomers, flame retardants such as halogens and antimony trioxide, and the like can be added.

【0011】本発明において、金属層は、フィルムでも
よいし、ある程度の強度をもつ板でもよい。金属層の厚
さは、要求される封止用絶縁体の厚さに応じて適当に設
定される。金属層の材質としては、鉄、ニッケル、銅、
金、銀、アルミニウム、すず、ステンレス、および鉛、
ならびにこれらの合金などが挙げられる。金属層には貫
通孔が少なくとも1個設けられる。
In the present invention, the metal layer may be a film or a plate having a certain strength. The thickness of the metal layer is appropriately set according to the required thickness of the sealing insulator. The material of the metal layer is iron, nickel, copper,
Gold, silver, aluminum, tin, stainless steel, and lead,
And alloys thereof. At least one through hole is provided in the metal layer.

【0012】本発明に係る封止用絶縁体は、貫通孔を有
する金属層の両面に樹脂層を形成した構造、すなわち少
なくとも樹脂層、金属層および樹脂層からなる3層構造
を有している。金属層の上下両面の2層の樹脂層のう
ち、半導体素子の能動面に直接接する樹脂層は、高い信
頼性を有する必要がある。このため、エポキシ樹脂また
はポリイミド樹脂などに、溶融シリカまたはチッ化ケイ
素などの無機充填材を添加した一般的な封止用樹脂を用
いることが好ましい。また、ガラスクロスに樹脂溶液を
含浸させることでエポキシ樹脂、ポリイミド樹脂などを
付着させた封止用樹脂を用いてもよい。一方、2層の樹
脂層のうち、半導体素子に直接接しない外面側の樹脂層
は、特に限定されない。すなわち、半導体素子に直接接
する樹脂層と同一の封止用樹脂を用いてもよいし、通常
のコーティング樹脂を用いてもよい。
The sealing insulator according to the present invention has a structure in which resin layers are formed on both surfaces of a metal layer having a through hole, that is, a three-layer structure including at least a resin layer, a metal layer, and a resin layer. . Of the two resin layers on the upper and lower surfaces of the metal layer, the resin layer directly in contact with the active surface of the semiconductor element needs to have high reliability. Therefore, it is preferable to use a general sealing resin in which an inorganic filler such as fused silica or silicon nitride is added to an epoxy resin or a polyimide resin. Alternatively, a sealing resin to which an epoxy resin, a polyimide resin, or the like is attached by impregnating a glass cloth with a resin solution may be used. On the other hand, of the two resin layers, the resin layer on the outer surface that is not in direct contact with the semiconductor element is not particularly limited. That is, the same sealing resin as the resin layer directly in contact with the semiconductor element may be used, or an ordinary coating resin may be used.

【0013】このような封止用絶縁体は、金属層の両面
に同一の封止用樹脂を塗布する方法、金属層の一方の面
(半導体素子側)に信頼性の高い封止用樹脂を塗布し、
他方の面に通常のコーティング樹脂を塗布する方法、ガ
ラスクロスに樹脂を付着させた後、金属層とともに積層
して張りつける方法などにより作製できる。
[0013] Such a sealing insulator is obtained by applying the same sealing resin to both surfaces of a metal layer, or by coating a highly reliable sealing resin on one surface (semiconductor element side) of the metal layer. Apply,
It can be produced by a method of applying a normal coating resin to the other surface, a method of attaching a resin to a glass cloth, and then laminating and attaching the resin to a metal layer.

【0014】本発明に係る封止用絶縁体においては、金
属層の上下両面に設けられる2層の樹脂層は金属層に設
けられた貫通孔を通して互いにつながり、その結果樹脂
層と金属層とが強固に一体化される。金属層に設ける貫
通孔の大きさ、数、位置は、樹脂封止型半導体装置の信
頼性に影響を及ぼす。すなわち、金属層に貫通孔を設け
る際には、2層の樹脂層と金属層とを強固に一体化する
とともに、水分の侵入を極力抑制できるようにし、高温
にさらされる表面実装工程を経ても封止されている半導
体素子が劣化しないように考慮する必要がある。
In the sealing insulator according to the present invention, the two resin layers provided on the upper and lower surfaces of the metal layer are connected to each other through through holes provided in the metal layer. As a result, the resin layer and the metal layer are connected to each other. Strongly integrated. The size, number, and position of the through holes provided in the metal layer affect the reliability of the resin-encapsulated semiconductor device. That is, when providing the through holes in the metal layer, the two resin layers and the metal layer are firmly integrated, and the penetration of moisture is suppressed as much as possible. It is necessary to take care that the sealed semiconductor element does not deteriorate.

【0015】ここで、貫通孔は水分の侵入路になるの
で、半導体素子の能動面と対向する位置をはずして設け
るのが好ましいと考えられ、例えば半導体素子の4隅の
近傍に対向する位置に設けることが好ましい。ただし、
表面実装工程での高温に耐えることを重視した場合、半
導体素子の能動面と対向する位置に貫通孔を設けてもよ
い。また、2層の樹脂層と金属層とを強固に一体化する
ためには、半導体素子の4隅の近傍に対応する位置のほ
かに、半導体素子の4辺の近傍に対応する位置に各辺に
沿って1個または複数個の貫通孔を設けることが好まし
い。貫通孔の大きさは、直径0.5〜2.0mmの丸
孔、または一辺0.5〜2.0mmの角孔が好ましい。
貫通孔の全面積は、水分の侵入を抑制しかつ2層の樹脂
層と金属層との結合を強固にすることの両者を考慮し
て、半導体素子の面積の1/2以下が好ましく、さらに
10%以下がより好ましい。
Here, since the through-holes serve as a water entry path, it is preferable that the through-holes are provided at positions opposed to the active surface of the semiconductor element. For example, the through-holes are provided at positions opposed to the vicinity of four corners of the semiconductor element. Preferably, it is provided. However,
When importance is placed on withstanding high temperatures in the surface mounting step, a through hole may be provided at a position facing the active surface of the semiconductor element. Further, in order to firmly integrate the two resin layers and the metal layer, in addition to the positions corresponding to the vicinity of the four corners of the semiconductor element, each side is positioned at the position corresponding to the vicinity of the four sides of the semiconductor element. It is preferable to provide one or a plurality of through-holes along. The size of the through hole is preferably a round hole having a diameter of 0.5 to 2.0 mm or a square hole having a side of 0.5 to 2.0 mm.
The total area of the through hole is preferably 1 / or less of the area of the semiconductor element in consideration of both suppressing the penetration of moisture and strengthening the bond between the two resin layers and the metal layer. 10% or less is more preferable.

【0016】金属層に設けられる貫通孔の配置例を図9
〜図14を参照して説明する。図9の金属層において
は、半導体素子の4隅の近傍に対向する位置に4個の丸
孔の貫通孔11が形成されている。図10の金属層にお
いては、半導体素子の中央部に対向する位置に1個の丸
孔の貫通孔11が形成されている。図11の金属層にお
いては、半導体素子の4隅の近傍および半導体素子の各
辺の中央の近傍に対向する位置に合計8個の丸孔の貫通
孔11が形成されている。図12の金属層においては、
半導体素子の中央部に対向する位置に1個、その周囲に
4個、半導体素子の4隅の近傍に対向する位置に4個、
半導体素子の各辺の近傍に対向する位置に各辺に沿って
5個ずつ、合計29個の丸孔の貫通孔(丸孔)11が形
成されている。図13の金属層においては、半導体素子
の中央部に対向する位置を中心として等間隔で多数の丸
孔の貫通孔(丸孔)11が形成されている。図14の金
属層においては、半導体素子の中央部に対向する位置に
1個の角孔の貫通孔11および半導体素子の各辺の近傍
に対向する位置に各辺に沿って4個の長孔の貫通孔11
が形成されている。
FIG. 9 shows an example of the arrangement of through holes provided in the metal layer.
This will be described with reference to FIGS. In the metal layer of FIG. 9, four round through-holes 11 are formed at positions facing the vicinity of the four corners of the semiconductor element. In the metal layer of FIG. 10, one round through-hole 11 is formed at a position facing the center of the semiconductor element. In the metal layer of FIG. 11, eight round through holes 11 are formed at positions facing the vicinity of the four corners of the semiconductor element and the vicinity of the center of each side of the semiconductor element. In the metal layer of FIG.
One at a position facing the center of the semiconductor device, four around the semiconductor device, four at positions near the four corners of the semiconductor device,
A total of 29 round holes (round holes) 11 are formed at positions facing each of the sides of the semiconductor element, each of which has five holes along each side. In the metal layer of FIG. 13, a large number of round through holes (round holes) 11 are formed at equal intervals around a position facing the center of the semiconductor element. In the metal layer shown in FIG. 14, one rectangular through hole 11 is provided at a position facing the center of the semiconductor device, and four long holes are provided along each side at a position facing each side of the semiconductor device. Through hole 11
Are formed.

【0017】本発明において、半導体素子の非能動面側
は、封止してもよいし、封止しなくてもよい。半導体素
子の非能動面側を封止する場合でも、封止用絶縁体とし
て、半導体素子の能動面側に用いられるのと同じ封止用
絶縁体を用いてもよいし、金属層のない封止用樹脂、通
常のコーティング樹脂などを用いてもよい。
In the present invention, the non-active surface side of the semiconductor element may or may not be sealed. Even when the non-active surface side of the semiconductor element is sealed, the same sealing insulator as that used on the active surface side of the semiconductor element may be used as the sealing insulator, or the sealing without a metal layer may be used. A stopping resin, a normal coating resin, or the like may be used.

【0018】本発明に係る封止用絶縁体を用いた樹脂封
止型半導体装置の代表例を図1〜図8に示す。なお、い
ずれの図でも、(a)は樹脂封止型半導体装置の製造プ
ロセスを示す断面図、(b)は樹脂封止後の状態を示す
断面図である。
Representative examples of a resin-sealed semiconductor device using a sealing insulator according to the present invention are shown in FIGS. In each of the drawings, (a) is a cross-sectional view showing a manufacturing process of a resin-sealed semiconductor device, and (b) is a cross-sectional view showing a state after resin sealing.

【0019】図1はワイヤボンディング方式の半導体素
子3を封止するものである。この例では、半導体素子3
の能動面側および非能動面側ともに、金属層7の両面に
封止用樹脂からなる樹脂層6が形成された封止用絶縁体
8で封止されている。
FIG. 1 shows a semiconductor device 3 of a wire bonding type. In this example, the semiconductor element 3
Both the active surface side and the non-active surface side are sealed with a sealing insulator 8 in which a resin layer 6 made of a sealing resin is formed on both surfaces of a metal layer 7.

【0020】図2はTAB(テープオートメーティッド
ボンディング)方式の半導体素子3を封止するものであ
る。すなわち、半導体素子3上にはボンディング金属5
´が形成され、このボンディング金属5´がテープ状の
絶縁フィルム9上に形成されたリード線4とボンディン
グされている。この例では、半導体素子3の能動面側お
よび非能動面側ともに、金属層7の両面に封止用樹脂か
らなる樹脂層6が形成された封止用絶縁体8で封止され
ている。
FIG. 2 shows a semiconductor device 3 of a TAB (tape automated bonding) method. That is, the bonding metal 5 is provided on the semiconductor element 3.
′ Is formed, and the bonding metal 5 ′ is bonded to the lead wire 4 formed on the tape-shaped insulating film 9. In this example, both the active surface side and the non-active surface side of the semiconductor element 3 are sealed with a sealing insulator 8 in which a resin layer 6 made of a sealing resin is formed on both surfaces of a metal layer 7.

【0021】図3はTAB方式の半導体素子3を封止す
るものである。この例では、半導体素子3の能動面側
(および側面)のみが、金属層7の両面に封止用樹脂か
らなる樹脂層6が形成された封止用絶縁体8で封止さ
れ、半導体素子3の非能動面側は封止されていない。
FIG. 3 is a view for encapsulating the semiconductor element 3 of the TAB method. In this example, only the active surface side (and side surface) of the semiconductor element 3 is sealed with a sealing insulator 8 in which a resin layer 6 made of a sealing resin is formed on both surfaces of a metal layer 7. The non-active surface side of 3 is not sealed.

【0022】図4はTAB方式の半導体素子3を封止す
るものである。この例では、半導体素子3の能動面側お
よび非能動面側ともに、金属層7の一方の面(半導体素
子3側)に封止用樹脂からなる樹脂層6、他方の面(外
面側)にコーティング樹脂からなる樹脂層10が形成さ
れた封止用絶縁体8で封止されている。
FIG. 4 shows a method for sealing the semiconductor element 3 of the TAB method. In this example, on both the active surface side and the non-active surface side of the semiconductor element 3, a resin layer 6 made of a sealing resin is provided on one surface (the semiconductor element 3 side) of the metal layer 7 and on the other surface (an outer surface side). It is sealed with a sealing insulator 8 on which a resin layer 10 made of a coating resin is formed.

【0023】図5はTAB方式の半導体素子3を封止す
るものである。この例では、半導体素子3の能動面側
は、金属層7の一方の面(半導体素子3側)に封止用樹
脂からなる樹脂層6、他方の面(外面側)にコーティン
グ樹脂からなる樹脂層10が形成された封止用絶縁体8
で封止されている。また、半導体素子3の非能動面側に
は、金属層7の一方の面(半導体素子3側)に封止用樹
脂からなる樹脂層6が形成された封止用絶縁体12が用
いられている。
FIG. 5 is a view for encapsulating the TAB type semiconductor element 3. In this example, the active surface side of the semiconductor element 3 has a resin layer 6 made of a sealing resin on one surface (semiconductor element 3 side) of the metal layer 7 and a resin made of a coating resin on the other surface (outer surface side). Sealing insulator 8 on which layer 10 is formed
It is sealed with. On the non-active surface side of the semiconductor element 3, a sealing insulator 12 in which a resin layer 6 made of a sealing resin is formed on one surface (the semiconductor element 3 side) of the metal layer 7 is used. I have.

【0024】図6はTAB方式の半導体素子3を封止す
るものである。この例では、半導体素子3の能動面側
は、金属層7の一方の面(半導体素子3側)に封止用樹
脂からなる樹脂層6、他方の面(外面側)にコーティン
グ樹脂からなる樹脂層10が形成された封止用絶縁体8
で封止されている。また、半導体素子3の非能動面側
は、金属層7の一方の面(半導体素子3側)にコーティ
ング樹脂からなる樹脂層10が形成された封止用絶縁体
12が用いられている。
FIG. 6 shows a method of sealing the TAB type semiconductor element 3. In this example, the active surface side of the semiconductor element 3 has a resin layer 6 made of a sealing resin on one surface (semiconductor element 3 side) of the metal layer 7 and a resin made of a coating resin on the other surface (outer surface side). Sealing insulator 8 on which layer 10 is formed
It is sealed with. On the non-active surface side of the semiconductor element 3, a sealing insulator 12 in which a resin layer 10 made of a coating resin is formed on one surface (the semiconductor element 3 side) of the metal layer 7 is used.

【0025】図7は半導体素子3の側面を囲むように、
絶縁フィルム9を介してリード線4が設けられた半導体
素子3を封止するものである。この例では、半導体素子
3の能動面側は、金属層7の一方の面(半導体素子3
側)に封止用樹脂からなる樹脂層6、他方の面(外面
側)にコーティング樹脂からなる樹脂層10が形成され
た封止用絶縁体8で封止されている。また、半導体素子
3の非能動面側は、封止用樹脂からなる樹脂層6のみで
封止されている。
FIG. 7 shows a state surrounding the side surface of the semiconductor element 3.
This seals the semiconductor element 3 provided with the lead wire 4 via the insulating film 9. In this example, the active surface side of the semiconductor element 3 is connected to one surface of the metal layer 7 (the semiconductor element 3).
This is sealed by a sealing insulator 8 in which a resin layer 6 made of a sealing resin is formed on one side and a resin layer 10 made of a coating resin is formed on the other surface (outer surface side). The non-active surface side of the semiconductor element 3 is sealed only with the resin layer 6 made of a sealing resin.

【0026】図8は絶縁基板上に配線層が形成された配
線基板13上にボンディングされた半導体素子3を封止
するものである。この例では、半導体素子3の能動面側
が、金属層7の一方の面(半導体素子3側)に封止用樹
脂からなる樹脂層6、他方の面(外面側)にコーティン
グ樹脂からなる樹脂層10が形成された封止用絶縁体8
で封止されている。
FIG. 8 is a view for sealing a semiconductor element 3 bonded on a wiring board 13 having a wiring layer formed on an insulating substrate. In this example, the active surface side of the semiconductor element 3 has a resin layer 6 made of a sealing resin on one surface (semiconductor element 3 side) of the metal layer 7 and a resin layer made of a coating resin on the other surface (outer surface side). Sealing insulator 8 on which 10 is formed
It is sealed with.

【0027】[0027]

【作用】本発明の樹脂封止型半導体装置は、少なくとも
半導体素子の能動面が、貫通孔を有する金属層の両面に
樹脂層を形成した封止用絶縁体で封止されている。この
封止用絶縁体を構成する金属層により、パッケージ内部
への水分の侵入を抑制できるので、半導体素子上のアル
ミニウム配線の腐食などを防止できる。また、金属層に
は貫通孔が設けられているため、この金属層とその上下
両面に形成される樹脂層が強固に一体化されている。こ
のため、パッケージを表面実装する際に高温加熱されて
も、パッケージ内部の水分が低減されているため高温加
熱されても水分の急激な気化膨張を抑制でき、かつ強固
に一体化された金属層と樹脂層との剥離が起こらないた
め、パッケージクラックによる破裂を防止して不良の発
生を抑えられる。
In the resin-sealed semiconductor device of the present invention, at least the active surface of the semiconductor element is sealed with a sealing insulator in which resin layers are formed on both surfaces of a metal layer having a through hole. The metal layer constituting the sealing insulator can prevent moisture from entering the inside of the package, so that corrosion of aluminum wiring on the semiconductor element can be prevented. Further, since the metal layer is provided with through holes, the metal layer and the resin layers formed on both upper and lower surfaces thereof are firmly integrated. For this reason, even if the package is heated to a high temperature when surface-mounted, the moisture inside the package is reduced, so that even if the package is heated to a high temperature, rapid vaporization and expansion of the moisture can be suppressed, and a strongly integrated metal layer is formed. Since the resin and the resin layer do not peel off, rupture due to package cracks is prevented, and occurrence of defects can be suppressed.

【0028】さらに本発明の樹脂封止型半導体装置は、
予め形成しておいた封止用絶縁体を用いて樹脂封止した
ものであるから、この特徴によって次のような特別の利
点が得られる。即ち、従来のトランスファー成形法によ
り樹脂封止された樹脂封止型半導体装置は、樹脂封止を
インラインで行うことができない。これに対して、本発
明の樹脂封止型半導体装置は、平板もしくは簡単な金型
を用いて樹脂封止ができるため、樹脂封止をアセンブリ
ー工程に組み込んでインラインで行うことが可能であ
る。従って、この特徴を生かすことにより、本発明の樹
脂封止型半導体装置は連続的かつ自動化された製造ライ
ンでの製造が可能となる。
Further, the resin-encapsulated semiconductor device of the present invention
Since the resin sealing is performed using the sealing insulator formed in advance, the following special advantages are obtained by this feature. That is, a resin-sealed semiconductor device sealed with a resin by a conventional transfer molding method cannot perform resin sealing inline. On the other hand, the resin-sealed semiconductor device of the present invention can be resin-sealed using a flat plate or a simple mold, so that the resin sealing can be incorporated in an assembly process and performed inline. Therefore, by utilizing this feature, the resin-encapsulated semiconductor device of the present invention can be manufactured on a continuous and automated manufacturing line.

【0029】[0029]

【実施例】以下、本発明の実施例および比較例を詳細に
説明する。 (1)樹脂溶液の調製 樹脂溶液(A) クレゾールノボラック型エポキシ樹脂:主剤(軟化点86℃) 80重量部 ブロム化ビスフェノールA型エポキシ樹脂:難燃化剤 (軟化点88℃) 20重量部 ノボラック型フェノール樹脂:硬化剤(軟化点76℃) 50重量部 トリフェニルホスフィン:触媒 2重量部 加熱ゲル化タイプ液状シリコーン:柔軟性付与/接着付与剤 5重量部 MBSゴム粉末:柔軟性付与剤 15重量部 球状シリカ粉末:無機充填材 120重量部 破砕状溶融シリカ粉末:無機充填材 190重量部 三酸化アンチモン粉末:難燃助剤 15重量部 カーボン粉末:顔料 3重量部 エチルセロソルブ:溶剤 2000重量部 樹脂溶液(B) ビスマレイミド樹脂:主剤(軟化点90℃) 80重量部 ブロム化ビスマレイミド樹脂:難燃化剤(軟化点96℃) 20重量部 ノボラック型フェノール樹脂:硬化剤(軟化点76℃) 50重量部 トリフェニルホスフィン:触媒 1重量部 過酸化ベンゾイル:触媒 1重量部 加熱ゲル化タイプ液状シリコーン:柔軟性付与/接着付与剤 5重量部 MBSゴム粉末:柔軟性付与剤 15重量部 球状シリカ粉末:無機充填材 120重量部 破砕状溶融シリカ粉末:無機充填材 190重量部 三酸化アンチモン粉末:難燃助剤 15重量部 カーボン粉末:顔料 3重量部 エチルセロソルブ:溶剤 2000重量部 樹脂溶液(C)の調製 クレゾールノボラック型エポキシ樹脂:主剤(軟化点86℃) 80重量部 ブロム化ビスフェノールA型エポキシ樹脂:難燃化剤 (軟化点88℃) 20重量部 ノボラック型フェノール樹脂:硬化剤(軟化点76℃) 50重量部 トリフェニルホスフィン:触媒 2重量部 加熱ゲル化タイプ液状シリコーン:柔軟性付与/接着付与剤 5重量部 MBSゴム粉末:柔軟性付与剤 15重量部 三酸化アンチモン粉末:難燃助剤 15重量部 カーボン粉末:顔料 3重量部 エチルセロソルブ:溶剤 1000重量部 樹脂溶液(D)の調製 ビスマレイミド樹脂:主剤(軟化点90℃) 80重量部 ブロム化ビスマレイミド樹脂:難燃化剤(軟化点96℃) 20重量部 ノボラック型フェノール樹脂:硬化剤(軟化点76℃) 50重量部 トリフェニルホスフィン:触媒 1重量部 過酸化ベンゾイル:触媒 1重量部 加熱ゲル化タイプ液状シリコーン:柔軟性付与/接着付与剤 5重量部 MBSゴム粉末:柔軟性付与剤 15重量部 三酸化アンチモン粉末:難燃助剤 15重量部 カーボン粉末:顔料 3重量部 エチルセロソルブ:溶剤 1000重量部
EXAMPLES Examples and comparative examples of the present invention will be described below in detail. (1) Preparation of resin solution Resin solution (A) Cresol novolak type epoxy resin: main component (softening point 86 ° C.) 80 parts by weight Brominated bisphenol A type epoxy resin: flame retardant (softening point 88 ° C.) 20 parts by weight novolak Type phenolic resin: curing agent (softening point: 76 ° C.) 50 parts by weight Triphenylphosphine: catalyst 2 parts by weight Heat gelling liquid silicone: 5 parts by weight for imparting flexibility / adhesiveness MBS rubber powder: 15 parts by weight for flexibility imparting agent Part Spherical silica powder: inorganic filler 120 parts by weight Crushed fused silica powder: inorganic filler 190 parts by weight Antimony trioxide powder: flame retardant auxiliary agent 15 parts by weight Carbon powder: pigment 3 parts by weight Ethyl cellosolve: solvent 2,000 parts by weight Resin Solution (B) Bismaleimide resin: Main component (softening point 90 ° C.) 80 parts by weight Brominated bismaleimide resin: Difficult Burning agent (softening point 96 ° C) 20 parts by weight Novolak type phenolic resin: curing agent (softening point 76 ° C) 50 parts by weight Triphenylphosphine: 1 part by weight of catalyst Benzoyl peroxide: 1 part by weight of heat-curing liquid silicone : Flexibility imparting / adhesive imparting agent 5 parts by weight MBS rubber powder: Flexibility imparting agent 15 parts by weight Spherical silica powder: 120 parts by weight inorganic filler Fragmented fused silica powder: 190 parts by weight inorganic filler Antimony trioxide powder: difficult Flame aid 15 parts by weight Carbon powder: Pigment 3 parts by weight Ethyl cellosolve: Solvent 2,000 parts by weight Preparation of resin solution (C) Cresol novolak type epoxy resin: Main agent (softening point 86 ° C) 80 parts by weight Brominated bisphenol A type epoxy resin : Flame retardant (softening point 88 ° C) 20 parts by weight Novolak type phenol resin: Curing agent (softening point 76) C) 50 parts by weight Triphenylphosphine: Catalyst 2 parts by weight Heat gelling type liquid silicone: Flexibility / adhesion imparting agent 5 parts by weight MBS rubber powder: Flexibility imparting agent 15 parts by weight Antimony trioxide powder: Flame retardant aid 15 parts by weight Carbon powder: pigment 3 parts by weight Ethyl cellosolve: solvent 1000 parts by weight Preparation of resin solution (D) Bismaleimide resin: main agent (softening point 90 ° C.) 80 parts by weight Brominated bismaleimide resin: flame retardant (softening) 20 parts by weight Novolak-type phenolic resin: curing agent (softening point: 76 ° C.) 50 parts by weight triphenylphosphine: 1 part by weight catalyst Benzoyl peroxide: 1 part by weight catalyst Gelled liquid silicone: flexibility / Adhesion-imparting agent 5 parts by weight MBS rubber powder: Flexibility-imparting agent 15 parts by weight Antimony trioxide powder: Flame retardant auxiliary agent 15 layers Part carbon powder: pigment 3 parts by weight of ethyl cellosolve: solvent 1000 parts by weight

【0030】以上の各成分をボールミルにより混練し、
必要に応じて加熱し、各樹脂溶液を調製した。なお、樹
脂溶液(A)および(B)は無機充填材を含むため、半
導体素子に直接接する樹脂層にも、封止用絶縁体の外面
を構成する樹脂層にも用いることができる。一方、樹脂
溶液(C)および(D)は無機充填材を含んでおらず信
頼性に劣るため、半導体素子に直接接する樹脂層に用い
られることはなく、封止用絶縁体の外面を構成する樹脂
層にのみ用いられる。 (2)封止用絶縁体の作製 封止用絶縁体(A) 厚さ36μmの両面黒化銅箔に、図9に示すように開孔
を設けた。この銅箔の両面に樹脂溶液(A)を塗布して
乾燥し、封止用絶縁体(A)を得た。 封止用絶縁体(B) 厚さ36μmの両面黒化銅箔に、図9に示すように開孔
を設けた。この銅箔の両面に樹脂溶液(B)を塗布して
乾燥し、封止用絶縁体(B)を得た。 封止用絶縁体(C) 厚さ36μmの両面黒化銅箔に、図10に示すように開
孔を設けた。この銅箔の両面に樹脂溶液(A)を塗布し
て乾燥し、封止用絶縁体(C)を得た。 封止用絶縁体(D) 厚さ36μmの両面黒化銅箔に、図11に示すように開
孔を設けた。この銅箔の両面に樹脂溶液(A)を塗布し
て乾燥し、封止用絶縁体(D)を得た。 封止用絶縁体(E)
The above components are kneaded by a ball mill,
It heated as needed and prepared each resin solution. Since the resin solutions (A) and (B) contain an inorganic filler, they can be used for a resin layer directly in contact with a semiconductor element and a resin layer constituting an outer surface of a sealing insulator. On the other hand, since the resin solutions (C) and (D) do not contain an inorganic filler and are inferior in reliability, they are not used for the resin layer directly in contact with the semiconductor element and constitute the outer surface of the sealing insulator. Used only for resin layers. (2) Production of Sealing Insulator Sealing Insulator (A) A double-sided blackened copper foil having a thickness of 36 μm was provided with openings as shown in FIG. The resin solution (A) was applied to both surfaces of the copper foil and dried to obtain a sealing insulator (A). Sealing insulator (B) Openings were formed in a 36 μm-thick double-sided blackened copper foil as shown in FIG. 9. The resin solution (B) was applied to both surfaces of the copper foil and dried to obtain a sealing insulator (B). Sealing insulator (C) A double-sided blackened copper foil having a thickness of 36 μm was provided with openings as shown in FIG. The resin solution (A) was applied to both surfaces of the copper foil and dried to obtain a sealing insulator (C). Sealing insulator (D) Openings were formed in a 36 μm thick double-sided blackened copper foil as shown in FIG. A resin solution (A) was applied to both surfaces of the copper foil and dried to obtain a sealing insulator (D). Insulator for sealing (E)

【0031】厚さ36μmの両面黒化銅箔に、図9に示
すように開孔を設けた。この銅箔の一方の面(半導体素
子側)に樹脂溶液(A)を塗布して乾燥し、他方の面
(外面側)に樹脂溶液(C)を塗布して乾燥し、封止用
絶縁体(E)を得た。 封止用絶縁体(F)
Openings were provided in a 36 μm thick double-sided blackened copper foil as shown in FIG. A resin solution (A) is applied to one surface (semiconductor element side) of the copper foil and dried, and a resin solution (C) is applied to the other surface (outer surface side) and dried. (E) was obtained. Insulator for sealing (F)

【0032】厚さ36μmの両面黒化銅箔に、図9に示
すように開孔を設けた。この銅箔の一方の面(半導体素
子側)に樹脂溶液(B)を塗布して乾燥し、他方の面
(外面側)に樹脂溶液(D)を塗布して乾燥し、封止用
絶縁体(F)を得た。 封止用絶縁体(G)
Openings were formed in a 36 μm-thick blackened double-sided copper foil as shown in FIG. A resin solution (B) is applied to one surface (semiconductor element side) of the copper foil and dried, and a resin solution (D) is applied to the other surface (outer surface side) and dried. (F) was obtained. Insulating insulator (G)

【0033】平織りガラスクロスの両面に、樹脂溶液
(A)を塗布して乾燥した。また、厚さ36μmの両面
黒化銅箔に、図9に示すように開孔を設けた。この銅箔
の一方の面(外面側)に樹脂溶液(C)を塗布して乾燥
した。樹脂が塗布された銅箔の未塗布面(半導体素子
側)に、樹脂が付着された平織りガラスクロスを重ね、
低温で加圧して複合タイプの封止用絶縁体(G)を得
た。 封止用絶縁体(H)
The resin solution (A) was applied to both sides of a plain woven glass cloth and dried. Also, holes were formed in a 36 μm thick double-sided blackened copper foil as shown in FIG. 9. The resin solution (C) was applied to one surface (outer surface side) of the copper foil and dried. On the uncoated surface (semiconductor element side) of the resin-coated copper foil, a plain-woven glass cloth with the resin
Pressing was performed at a low temperature to obtain a composite-type sealing insulator (G). Sealing insulator (H)

【0034】平織りガラスクロスの両面に、樹脂溶液
(A)を塗布して乾燥した。また、厚さ36μmの両面
黒化銅箔に、図12に示すように開孔を設けた。この銅
箔の一方の面(外面側)に樹脂溶液(C)を塗布して乾
燥した。樹脂が塗布された銅箔の未塗布面(半導体素子
側)に、樹脂が付着された平織りガラスクロスを重ね、
低温で加圧して複合タイプの封止用絶縁体(H)を得
た。 封止用絶縁体(I)
The resin solution (A) was applied to both sides of a plain-woven glass cloth and dried. In addition, a hole was formed in a 36 μm thick double-sided blackened copper foil as shown in FIG. The resin solution (C) was applied to one surface (outer surface side) of the copper foil and dried. On the uncoated surface (semiconductor element side) of the resin-coated copper foil, a plain-woven glass cloth with the resin
Pressing was performed at a low temperature to obtain a composite-type sealing insulator (H). Insulator for sealing (I)

【0035】平織りガラスクロスの両面に、樹脂溶液
(A)を塗布して乾燥した。また、厚さ36μmの両面
黒化銅箔に、図13に示すように開孔を設けた。この銅
箔の一方の面(外面側)に樹脂溶液(C)を塗布して乾
燥した。樹脂が塗布された銅箔の未塗布面(半導体素子
側)に、樹脂が付着された平織りガラスクロスを重ね、
低温で加圧して複合タイプの封止用絶縁体(I)を得
た。 封止用絶縁体(J)
The resin solution (A) was applied to both sides of a plain-woven glass cloth and dried. In addition, an opening was formed in a double-sided blackened copper foil having a thickness of 36 μm as shown in FIG. The resin solution (C) was applied to one surface (outer surface side) of the copper foil and dried. On the uncoated surface (semiconductor element side) of the resin-coated copper foil, a plain-woven glass cloth with the resin
Pressing was performed at low temperature to obtain a composite-type sealing insulator (I). Insulator for sealing (J)

【0036】平織りガラスクロスの両面に、樹脂溶液
(A)を塗布して乾燥した。また、厚さ36μmの両面
黒化銅箔に、図14に示すように開孔を設けた。この銅
箔の一方の面(外面側)に樹脂溶液(C)を塗布して乾
燥した。樹脂が塗布された銅箔の未塗布面(半導体素子
側)に、樹脂が付着された平織りガラスクロスを重ね、
低温で加圧して複合タイプの封止用絶縁体(J)を得
た。 封止用絶縁体(K)
The resin solution (A) was applied to both sides of a plain-woven glass cloth and dried. In addition, openings were formed in a 36 μm-thick blackened double-sided copper foil as shown in FIG. The resin solution (C) was applied to one surface (outer surface side) of the copper foil and dried. On the uncoated surface (semiconductor element side) of the resin-coated copper foil, a plain-woven glass cloth with the resin
Pressing was performed at a low temperature to obtain a composite-type sealing insulator (J). Insulator for sealing (K)

【0037】平織りガラスクロスの両面に、樹脂溶液
(A)を塗布して乾燥し、封止用絶縁体(K)を得た。
このように、封止用絶縁体(K)は金属層が設けられて
いない。 封止用絶縁体(L)
The resin solution (A) was applied to both sides of the plain-woven glass cloth and dried to obtain a sealing insulator (K).
As described above, the sealing insulator (K) has no metal layer. Insulator for sealing (L)

【0038】平織りガラスクロスの両面に、樹脂溶液
(A)を塗布して乾燥した。また、厚さ45μmのアル
ミニウム箔に、図9に示すように開孔を設けた。このア
ルミニウム箔の一方の面(外面側)に樹脂溶液(C)を
塗布して乾燥した。樹脂が塗布されたアルミニウム箔の
未塗布面(半導体素子側)に、樹脂が付着された平織り
ガラスクロスを重ね、低温で加圧して複合タイプの封止
用絶縁体(L)を得た。 封止用絶縁体(M)
The resin solution (A) was applied to both sides of a plain-woven glass cloth and dried. Also, apertures were formed in a 45 μm-thick aluminum foil as shown in FIG. The resin solution (C) was applied to one surface (outer surface side) of the aluminum foil and dried. A plain-woven glass cloth to which the resin was applied was overlaid on the uncoated surface (semiconductor element side) of the aluminum foil to which the resin was applied, and pressed at a low temperature to obtain a composite-type sealing insulator (L). Insulator for sealing (M)

【0039】ケブラークロスの両面に、樹脂溶液(A)
を塗布して乾燥した。また、厚さ36μmの両面黒化銅
箔に、図9に示すように開孔を設けた。この銅箔の一方
の面(外面側)に樹脂溶液(C)を塗布して乾燥した。
樹脂が塗布された銅箔の未塗布面(半導体素子側)に、
樹脂が付着されたケブラークロスを重ね、低温で加圧し
て複合タイプの封止用絶縁体(M)を得た。 封止用絶縁体(N) 厚さ36μmの両面黒化銅箔に、図9に示すように開孔
を設けた。この銅箔の両面に樹脂溶液(C)を塗布して
乾燥し、封止用絶縁体(N)を得た。 封止用絶縁体(O)
On both sides of the Kevlar cloth, apply the resin solution (A)
And dried. Also, holes were formed in a 36 μm thick double-sided blackened copper foil as shown in FIG. 9. The resin solution (C) was applied to one surface (outer surface side) of the copper foil and dried.
On the uncoated surface (semiconductor element side) of the copper foil coated with resin,
The Kevlar cloth to which the resin was attached was overlaid and pressed at a low temperature to obtain a composite-type sealing insulator (M). Sealing insulator (N) A double-sided blackened copper foil having a thickness of 36 μm was provided with openings as shown in FIG. A resin solution (C) was applied to both surfaces of the copper foil and dried to obtain a sealing insulator (N). Sealing insulator (O)

【0040】平織りガラスクロスの両面に、溶融シリカ
粉末を50重量%含有するホットメルト型フッ素樹脂
(PFA)シートを加熱プレスした。また、厚さ45μ
mのアルミニウム箔に、図9に示すように開孔を設け
た。このアルミニウム箔の一方の面(外面側)にフッ素
樹脂(PFA)フィルムを加熱プレスした。PFAフィ
ルムが貼付されたアルミニウム箔の未貼付面(半導体素
子側)に、PFAシートが貼付された平織りガラスクロ
スを重ね、加熱加圧して複合タイプの封止用絶縁体
(O)を得た。 封止用絶縁体(P)
A hot-melt fluororesin (PFA) sheet containing 50% by weight of fused silica powder was hot-pressed on both sides of the plain-woven glass cloth. In addition, thickness 45μ
A hole was formed in the aluminum foil of m as shown in FIG. A fluororesin (PFA) film was hot-pressed on one surface (outer surface side) of the aluminum foil. A plain-woven glass cloth on which a PFA sheet was adhered was laminated on the unattached surface (semiconductor element side) of the aluminum foil on which the PFA film was adhered, and heated and pressed to obtain a composite-type sealing insulator (O). Sealing insulator (P)

【0041】平織りガラスクロスの両面に、溶融シリカ
粉末を50重量%含有するポリフェニレンサルファイド
(PPS)シートを加熱プレスした。また、厚さ45μ
mのアルミニウム箔に、図9に示すように開孔を設け
た。このアルミニウム箔の一方の面(外面側)にポリフ
ェニレンサルファイド(PPS)フィルムを加熱プレス
した。PPSフィルムが貼付されたアルミニウム箔の未
貼付面(半導体素子側)に、PPSシートが貼付された
平織りガラスクロスを重ね、加熱加圧して複合タイプの
封止用絶縁体(P)を得た。 封止用絶縁体(Q)
A polyphenylene sulfide (PPS) sheet containing 50% by weight of fused silica powder was hot-pressed on both sides of a plain-woven glass cloth. In addition, thickness 45μ
A hole was formed in the aluminum foil of m as shown in FIG. A polyphenylene sulfide (PPS) film was hot-pressed on one surface (outer surface side) of the aluminum foil. A plain-woven glass cloth to which a PPS sheet was attached was overlaid on the unattached surface (semiconductor element side) of the aluminum foil to which the PPS film was attached, and heated and pressed to obtain a composite-type sealing insulator (P). Insulator for sealing (Q)

【0042】平織りガラスクロスの両面に、溶融シリカ
粉末を30重量%、ガラス短繊維30重量%を含有する
ホットメルト型フッ素樹脂(PFA)シートを加熱プレ
スした。また、厚さ45μmのアルミニウム箔に、図9
に示すように開孔を設けた。このアルミニウム箔の一方
の面(外面側)にフッ素樹脂(PFA)フィルムを加熱
プレスした。PFAフィルムが貼付されたアルミニウム
箔の未貼付面(半導体素子側)に、PFAシートが貼付
された平織りガラスクロスを重ね、加熱加圧して複合タ
イプの封止用絶縁体(Q)を得た。 封止用絶縁体(R)
A hot-melt type fluororesin (PFA) sheet containing 30% by weight of fused silica powder and 30% by weight of short glass fibers was hot-pressed on both sides of a plain-woven glass cloth. FIG. 9 shows an aluminum foil having a thickness of 45 μm.
An opening was provided as shown in FIG. A fluororesin (PFA) film was hot-pressed on one surface (outer surface side) of the aluminum foil. A plain-woven glass cloth on which a PFA sheet was adhered was laminated on the unattached surface (semiconductor element side) of the aluminum foil on which the PFA film was adhered, and heated and pressed to obtain a composite-type sealing insulator (Q). Insulator for sealing (R)

【0043】平織りガラスクロスの両面に、溶融シリカ
粉末を40重量%、球状フェノール樹脂硬化粉末10重
量%を含有するポリフェニレンサルファイド(PPS)
シートを加熱プレスした。また、厚さ45μmのアルミ
ニウム箔に、図9に示すように開孔を設けた。このアル
ミニウム箔の一方の面(外面側)にポリフェニレンサル
ファイド(PPS)フィルムを加熱プレスした。PPS
フィルムが貼付されたアルミニウム箔の未貼付面(半導
体素子側)に、PPSシートが貼付された平織りガラス
クロスを重ね、加熱加圧して複合タイプの封止用絶縁体
(R)を得た。 封止用絶縁体(S)
Polyphenylene sulfide (PPS) containing 40% by weight of fused silica powder and 10% by weight of hardened spherical phenol resin powder on both sides of a plain-woven glass cloth
The sheet was hot pressed. Also, apertures were formed in a 45 μm-thick aluminum foil as shown in FIG. A polyphenylene sulfide (PPS) film was hot-pressed on one surface (outer surface side) of the aluminum foil. PPS
A plain-woven glass cloth to which a PPS sheet was attached was overlaid on the unattached surface (semiconductor element side) of the aluminum foil to which the film was attached, and heated and pressed to obtain a composite-type sealing insulator (R). Insulator for sealing (S)

【0044】厚さ36μmの両面黒化銅箔の両面に樹脂
溶液(A)を塗布して乾燥し、封止用絶縁体(S)を得
た。このように、封止用絶縁体(S)の銅箔には、貫通
孔が設けられていない。 封止用絶縁体(T)
A resin solution (A) was applied to both sides of a 36 μm thick blackened double-sided copper foil and dried to obtain a sealing insulator (S). Thus, no through hole is provided in the copper foil of the sealing insulator (S). Insulator for sealing (T)

【0045】平織りガラスクロスの両面に、樹脂溶液
(A)を塗布して乾燥した。また、厚さ36μmの両面
黒化銅箔の一方の面(外面側)に樹脂溶液(C)を塗布
して乾燥した。樹脂が塗布された銅箔の未塗布面(半導
体素子側)に、樹脂が付着された平織りガラスクロスを
重ね、低温で加圧して複合タイプの封止用絶縁体(T)
を得た。このように、封止用絶縁体(T)の銅箔には、
貫通孔が設けられていない。 封止用絶縁体(U)
The resin solution (A) was applied to both sides of a plain-woven glass cloth and dried. Further, a resin solution (C) was applied to one surface (outer surface side) of a double-sided blackened copper foil having a thickness of 36 μm and dried. Plain woven glass cloth to which the resin is applied is laminated on the uncoated surface (semiconductor element side) of the copper foil to which the resin is applied, and pressed at a low temperature to form a composite-type sealing insulator (T).
I got Thus, the copper foil of the sealing insulator (T) includes:
No through hole is provided. Insulating insulator (U)

【0046】平織りガラスクロスの両面に、溶融シリカ
粉末を50重量%含有するホットメルト型フッ素樹脂
(PFA)シートを加熱プレスした。また、厚さ45μ
mのアルミニウム箔の一方の面(外面側)にフッ素樹脂
(PFA)フィルムを加熱プレスした。PFAフィルム
が貼付されたアルミニウム箔の未貼付面(半導体素子
側)に、PFAシートが貼付された平織りガラスクロス
を重ね、加熱加圧して複合タイプの封止用絶縁体(U)
を得た。このように、封止用絶縁体(U)の銅箔には、
貫通孔が設けられていない。 封止用絶縁体(V)
A hot-melt fluororesin (PFA) sheet containing 50% by weight of fused silica powder was hot-pressed on both sides of the plain-woven glass cloth. In addition, thickness 45μ
A fluororesin (PFA) film was hot-pressed on one surface (outer surface side) of the aluminum foil of m. A plain-woven glass cloth on which a PFA sheet is adhered is superimposed on the unattached surface (semiconductor element side) of the aluminum foil on which the PFA film is adhered, and heated and pressed to form a composite-type sealing insulator (U)
I got Thus, the copper foil of the sealing insulator (U) includes:
No through hole is provided. Insulator for sealing (V)

【0047】平織りガラスクロスの両面に、溶融シリカ
粉末を50重量%含有するポリフェニレンサルファイド
(PPS)シートを加熱プレスした。また、厚さ45μ
mのアルミニウム箔の一方の面(外面側)にポリフェニ
レンサルファイド(PPS)フィルムを加熱プレスし
た。PPSフィルムが貼付されたアルミニウム箔の未貼
付側(半導体素子側)に、PPSシートが貼付された平
織りガラスクロスを重ね、加熱加圧して複合タイプの封
止用絶縁体(V)を得た。このように、封止用絶縁体
(V)の銅箔には、貫通孔が設けられていない。 (3)テスト素子の準備 テスト素子(A)
A polyphenylene sulfide (PPS) sheet containing 50% by weight of fused silica powder was hot-pressed on both sides of the plain-woven glass cloth. In addition, thickness 45μ
A polyphenylene sulfide (PPS) film was hot-pressed on one surface (outer surface side) of the aluminum foil of m. A plain-woven glass cloth on which a PPS sheet was adhered was overlaid on the unattached side (semiconductor element side) of the aluminum foil on which the PPS film was adhered, and heated and pressed to obtain a composite-type sealing insulator (V). Thus, no through-hole is provided in the copper foil of the sealing insulator (V). (3) Test element preparation Test element (A)

【0048】ダイパッドサイズ15.5mm×15.5
mm、板厚150μmの4,2アロイ製リードフレーム
に、チップ厚さ300μm、チップ面積15.0mm×
15.0mmであり、表面がポリイミド樹脂でパッシベ
ーションコートされた、耐湿性テスト回路内蔵の半導体
素子を搭載し、25μm径のボンディングワイヤーでボ
ンディングしたものを用意した。 テスト素子(B)
Die pad size 15.5 mm × 15.5
mm, 4,2 alloy lead frame with 150 μm plate thickness, chip thickness 300 μm, chip area 15.0 mm ×
A semiconductor device having a built-in moisture resistance test circuit with a surface of 15.0 mm and passivated by a polyimide resin and bonded with a bonding wire having a diameter of 25 μm was prepared. Test element (B)

【0049】TABテープに、チップ厚さ300μm、
チップ面積15.0mm×15.0mmであり、表面が
ポリイミド樹脂でパッシベーションコートされた、耐湿
性テスト回路内蔵の半導体素子をボンディングしたもの
を用意した。 (4)本発明の樹脂封止型半導体装置の作製および評価
On a TAB tape, a chip thickness of 300 μm,
A chip was prepared by bonding a semiconductor element having a chip area of 15.0 mm × 15.0 mm and having a surface subjected to passivation coating with a polyimide resin and having a built-in moisture resistance test circuit. (4) Production and evaluation of resin-encapsulated semiconductor device of the present invention

【0050】表1および表2に示す組み合わせで、
(3)のテスト素子の上部および下部に、(2)の封止
用絶縁体を配置し、ボイドおよび剥離を防止するために
金型内を減圧しながら、加熱加圧することにより樹脂封
止した。
In the combinations shown in Tables 1 and 2,
The sealing insulator of (2) was disposed above and below the test element of (3), and the inside of the mold was heated and pressurized while reducing the pressure in the mold in order to prevent voids and separation. .

【0051】[0051]

【表1】 [Table 1]

【0052】[0052]

【表2】 [Table 2]

【0053】次に、実施例1〜20、比較例1〜6の樹
脂封止型半導体装置について、以下のようにして、印刷
配線基板に実装する際の高温はんだ処理に対する耐性を
調べた。まず、各樹脂封止型半導体装置を、温度85
℃、湿度85%RHの高温高湿条件で168時間吸湿処
理した。その後、基板への表面実装工程を想定した21
5℃×2分間のVPS(ベーパーフェイズリフロー)処
理を行った。
Next, the resistance of the resin-sealed semiconductor devices of Examples 1 to 20 and Comparative Examples 1 to 6 to high-temperature soldering when mounted on a printed wiring board was examined as follows. First, each resin-encapsulated semiconductor device was heated to a temperature of 85 ° C.
The film was subjected to a moisture absorption treatment under high temperature and high humidity conditions of 85 ° C. and a relative humidity of 85% for 168 hours. After that, assuming a surface mounting process on a substrate 21
VPS (vapor phase reflow) treatment was performed at 5 ° C. × 2 minutes.

【0054】VPS処理後の各樹脂封止型半導体装置に
ついて、目視観察により外部に達するクラックの有無を
調べた。次に、VSP処理後の樹脂封止型半導体装置を
温度127℃、2.5気圧の飽和水蒸気中(プレッシャ
クッカー)に入れ、一定時間毎に取り出してテスト素子
の断線(オープン)不良を調べることにより、耐湿信頼
性試験(PCT)を行った。これらの結果を表3および
表4に示す。
Each resin-encapsulated semiconductor device after the VPS treatment was visually inspected for cracks reaching the outside. Next, the resin-encapsulated semiconductor device after the VSP process is placed in saturated steam at a temperature of 127 ° C. and 2.5 atm (pressure cooker), taken out at regular intervals, and examined for disconnection (open) failure of the test element. , A humidity resistance test (PCT) was performed. The results are shown in Tables 3 and 4.

【0055】表3および表4から明らかなように、実施
例1〜20の樹脂封止型半導体装置は、比較例1〜6に
比べて優れた耐湿信頼性を示している。これは、実施例
では金属層により水分が遮断され、かつ金属層に設けら
れた開孔を通して上下の樹脂層がつながりこれらが強固
に一体化されていることから、VPS処理時の樹脂層の
剥離が防止されるためである。
As is evident from Tables 3 and 4, the resin-sealed semiconductor devices of Examples 1 to 20 exhibit superior moisture resistance reliability as compared with Comparative Examples 1 to 6. This is because, in the embodiment, since the moisture is blocked by the metal layer, and the upper and lower resin layers are connected to each other through the opening provided in the metal layer and these are firmly integrated, the resin layer is peeled off during the VPS process. Is to be prevented.

【0056】[0056]

【表3】 [Table 3]

【0057】[0057]

【表4】 [Table 4]

【0058】[0058]

【発明の効果】以上詳述したごとく本発明によれば、パ
ッケージ内部への水分の侵入が抑制され、かつ樹脂封止
型半導体装置にとって最も過酷な工程であるVPS処理
工程を経ても外部クラックや剥離がないため、高い耐湿
信頼性を有し、しかも製造が容易であり、今後の半導体
素子の大型化や薄型化志向に十分に対応可能な樹脂封止
型半導体装置を提供することができる。
As described above in detail, according to the present invention, the invasion of moisture into the package is suppressed, and external cracks and cracks are prevented even after the VPS processing step, which is the most severe step for the resin-encapsulated semiconductor device. Since there is no peeling, it is possible to provide a resin-encapsulated semiconductor device that has high moisture resistance reliability, is easy to manufacture, and can sufficiently cope with the future trend toward larger and thinner semiconductor elements.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)は本発明に係る樹脂封止型半導体装置の
製造プロセスを示す断面図、(b)は同樹脂封止型半導
体装置の封止後の断面図。
FIG. 1A is a cross-sectional view illustrating a manufacturing process of a resin-sealed semiconductor device according to the present invention, and FIG. 1B is a cross-sectional view of the resin-sealed semiconductor device after sealing.

【図2】(a)は本発明に係る樹脂封止型半導体装置の
製造プロセスを示す断面図、(b)は同樹脂封止型半導
体装置の封止後の断面図。
FIG. 2A is a cross-sectional view illustrating a manufacturing process of the resin-sealed semiconductor device according to the present invention, and FIG. 2B is a cross-sectional view of the resin-sealed semiconductor device after sealing.

【図3】(a)は本発明に係る樹脂封止型半導体装置の
製造プロセスを示す断面図、(b)は同樹脂封止型半導
体装置の封止後の断面図。
3A is a cross-sectional view illustrating a manufacturing process of the resin-sealed semiconductor device according to the present invention, and FIG. 3B is a cross-sectional view of the resin-sealed semiconductor device after sealing.

【図4】(a)は本発明に係る樹脂封止型半導体装置の
製造プロセスを示す断面図、(b)は同樹脂封止型半導
体装置の封止後の断面図。
4A is a cross-sectional view illustrating a manufacturing process of the resin-sealed semiconductor device according to the present invention, and FIG. 4B is a cross-sectional view of the resin-sealed semiconductor device after sealing.

【図5】(a)は本発明に係る樹脂封止型半導体装置の
製造プロセスを示す断面図、(b)は同樹脂封止型半導
体装置の封止後の断面図。
5A is a cross-sectional view illustrating a manufacturing process of the resin-encapsulated semiconductor device according to the present invention, and FIG. 5B is a cross-sectional view of the resin-encapsulated semiconductor device after encapsulation.

【図6】(a)は本発明に係る樹脂封止型半導体装置の
製造プロセスを示す断面図、(b)は同樹脂封止型半導
体装置の封止後の断面図。
6A is a cross-sectional view illustrating a manufacturing process of the resin-sealed semiconductor device according to the present invention, and FIG. 6B is a cross-sectional view of the resin-sealed semiconductor device after sealing.

【図7】(a)は本発明に係る樹脂封止型半導体装置の
製造プロセスを示す断面図、(b)は同樹脂封止型半導
体装置の封止後の断面図。
7A is a cross-sectional view illustrating a manufacturing process of the resin-sealed semiconductor device according to the present invention, and FIG. 7B is a cross-sectional view of the resin-sealed semiconductor device after sealing.

【図8】(a)は本発明に係る樹脂封止型半導体装置の
製造プロセスを示す断面図、(b)は同樹脂封止型半導
体装置の封止後の断面図。
8A is a cross-sectional view illustrating a manufacturing process of the resin-sealed semiconductor device according to the present invention, and FIG. 8B is a cross-sectional view of the resin-sealed semiconductor device after sealing.

【図9】本発明において用いられる開孔が設けられた金
属層の例を示す平面図。
FIG. 9 is a plan view showing an example of a metal layer provided with an opening used in the present invention.

【図10】本発明において用いられる開孔が設けられた
金属層の例を示す平面図。
FIG. 10 is a plan view showing an example of a metal layer provided with an opening used in the present invention.

【図11】本発明において用いられる開孔が設けられた
金属層の例を示す平面図。
FIG. 11 is a plan view showing an example of a metal layer provided with openings used in the present invention.

【図12】本発明において用いられる開孔が設けられた
金属層の例を示す平面図。
FIG. 12 is a plan view showing an example of a metal layer provided with an opening used in the present invention.

【図13】本発明において用いられる開孔が設けられた
金属層の例を示す平面図。
FIG. 13 is a plan view showing an example of a metal layer provided with openings used in the present invention.

【図14】本発明において用いられる開孔が設けられた
金属層の例を示す平面図。
FIG. 14 is a plan view showing an example of a metal layer provided with an opening used in the present invention.

【図15】(a)は従来の樹脂封止型半導体装置の製造
プロセスを示す断面図、(b)は同樹脂封止型半導体装
置の封止後の断面図。
15A is a cross-sectional view illustrating a manufacturing process of a conventional resin-sealed semiconductor device, and FIG. 15B is a cross-sectional view of the same resin-sealed semiconductor device after sealing.

【符号の説明】[Explanation of symbols]

3、20…半導体素子、6、10、14、16…樹脂
層、7、15…金属層、8、12、17…封止用絶縁
体、11…貫通孔。
3, 20: semiconductor element, 6, 10, 14, 16: resin layer, 7, 15: metal layer, 8, 12, 17: sealing insulator, 11: through hole.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 藤枝 新悦 神奈川県川崎市幸区小向東芝町1番地 株式会社東芝総合研究所内 (72)発明者 東 道也 神奈川県川崎市幸区小向東芝町1番地 株式会社東芝総合研究所内 (56)参考文献 特開 昭60−257153(JP,A) 特開 昭63−308355(JP,A) 実開 昭48−73568(JP,U) (58)調査した分野(Int.Cl.7,DB名) H01L 21/56,23/28 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinetsu Fujieda 1 Toshiba-cho, Komukai-shi, Kawasaki-shi, Kanagawa Prefecture Inside Toshiba Research Institute, Inc. (72) Inventor Michiya Higashi Toshiba Komukai-shi, Kawasaki-shi, Kanagawa No. 1, Toshiba Research Institute, Inc. (56) References JP-A-60-257153 (JP, A) JP-A-63-308355 (JP, A) JP-A-48-73568 (JP, U) (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21 / 56,23 / 28

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 貫通孔を有する金属層と前記金属層の両
面に形成された樹脂層とを具備した封止用絶縁体を形成
する工程と、 前記封止用絶縁体と半導体素子とを重ねて配置する工程
と、 重ねて配置された前記封止用絶縁体を加熱加圧すること
により前記半導体素子を樹脂封止する工程とを有し、 前記金属層の貫通孔は前記半導体素子の能動面と対向す
る位置をはずして設けられている ことを特徴とする樹脂
封止型半導体装置の製造方法。
A step of forming a sealing insulator including a metal layer having a through hole and resin layers formed on both surfaces of the metal layer; and laminating the sealing insulator and a semiconductor element. placing Te, the semiconductor device by heating and pressurizing the sealing insulator disposed to overlap and a step of resin-sealing, the through holes of the metal layer is an active surface of the semiconductor element Oppose
A method for manufacturing a resin-encapsulated semiconductor device, wherein the semiconductor device is provided at a different position .
JP07487092A 1992-03-31 1992-03-31 Method for manufacturing resin-encapsulated semiconductor device Expired - Fee Related JP3155811B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP07487092A JP3155811B2 (en) 1992-03-31 1992-03-31 Method for manufacturing resin-encapsulated semiconductor device
KR1019930005371A KR0124494B1 (en) 1992-03-31 1993-03-31 Plastic package semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07487092A JP3155811B2 (en) 1992-03-31 1992-03-31 Method for manufacturing resin-encapsulated semiconductor device

Publications (2)

Publication Number Publication Date
JPH05283453A JPH05283453A (en) 1993-10-29
JP3155811B2 true JP3155811B2 (en) 2001-04-16

Family

ID=13559801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP07487092A Expired - Fee Related JP3155811B2 (en) 1992-03-31 1992-03-31 Method for manufacturing resin-encapsulated semiconductor device

Country Status (1)

Country Link
JP (1) JP3155811B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5977717B2 (en) * 2013-07-29 2016-08-24 信越化学工業株式会社 Semiconductor encapsulating substrate encapsulating material, semiconductor encapsulating substrate encapsulating material manufacturing method, and semiconductor device manufacturing method
JP2015080824A (en) * 2013-10-21 2015-04-27 利昌工業株式会社 Carrier material for polishing
JP2015179769A (en) * 2014-03-19 2015-10-08 信越化学工業株式会社 Sealant with substrate for semiconductor encapsulation, semiconductor apparatus, and manufacturing method of semiconductor apparatus
KR102387029B1 (en) 2017-01-27 2022-04-18 디아이씨 가부시끼가이샤 Metal/resin composite structure and manufacturing method thereof

Also Published As

Publication number Publication date
JPH05283453A (en) 1993-10-29

Similar Documents

Publication Publication Date Title
US6528893B2 (en) Low-pin-count chip package and manufacturing method thereof
JP3962449B2 (en) Method and structure for bonding substrates
US6541872B1 (en) Multi-layered adhesive for attaching a semiconductor die to a substrate
US5805427A (en) Ball grid array electronic package standoff design
JP3661444B2 (en) Semiconductor device, semiconductor wafer, semiconductor module, and semiconductor device manufacturing method
US7038325B2 (en) Wiring tape for semiconductor device including a buffer layer having interconnected foams
US6118183A (en) Semiconductor device, manufacturing method thereof, and insulating substrate for same
JPH08335653A (en) Semiconductor device, its production and tape carrier for semiconductor device used for production of the semiconductor device
US6589812B2 (en) Pre-applied adhesion promoter
US10398026B2 (en) Laminated substrate and method of manufacturing laminated substrate
JP3207286B2 (en) Resin-sealed semiconductor device
JP3155811B2 (en) Method for manufacturing resin-encapsulated semiconductor device
US6649833B1 (en) Negative volume expansion lead-free electrical connection
JP2002064162A (en) Semiconductor chip
JP3795628B2 (en) Manufacturing method of wiring board mounting semiconductor chip
JP3539528B2 (en) Semiconductor device and manufacturing method thereof
JP2002064161A (en) Semiconductor chip and manufacturing method thereof
JP2001068604A (en) Fixing resin, anisotropic conductive resin, semiconductor device and manufacture thereof, circuit board and electronic equipment
JP2967080B1 (en) Method of manufacturing semiconductor device package
JP3314142B2 (en) Semiconductor package manufacturing method
JPH07105405B2 (en) Semiconductor device
JPH0442922Y2 (en)
JP2937398B2 (en) Manufacturing method of encapsulated semiconductor device
JP2001168232A (en) Circuit part connection body and its manufacturing method, double-sided circuit board and its manufacturing method, circuit part packaging body, and multilayer circuit board
JPH1084055A (en) Semiconductor device and its manufacturing method

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080202

Year of fee payment: 7

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090202

Year of fee payment: 8

LAPS Cancellation because of no payment of annual fees