JPH0562786B2 - - Google Patents

Info

Publication number
JPH0562786B2
JPH0562786B2 JP61166981A JP16698186A JPH0562786B2 JP H0562786 B2 JPH0562786 B2 JP H0562786B2 JP 61166981 A JP61166981 A JP 61166981A JP 16698186 A JP16698186 A JP 16698186A JP H0562786 B2 JPH0562786 B2 JP H0562786B2
Authority
JP
Japan
Prior art keywords
address
devices
comparator
hardware
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61166981A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6324343A (ja
Inventor
Teru Morimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16698186A priority Critical patent/JPS6324343A/ja
Publication of JPS6324343A publication Critical patent/JPS6324343A/ja
Publication of JPH0562786B2 publication Critical patent/JPH0562786B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/063—Address space extension for I/O modules, e.g. memory mapped I/O

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP16698186A 1986-07-16 1986-07-16 Ｉ／ｏアドレスデコ−ド方式 Granted JPS6324343A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16698186A JPS6324343A (ja) 1986-07-16 1986-07-16 Ｉ／ｏアドレスデコ−ド方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16698186A JPS6324343A (ja) 1986-07-16 1986-07-16 Ｉ／ｏアドレスデコ−ド方式

Publications (2)

Publication Number Publication Date
JPS6324343A JPS6324343A (ja) 1988-02-01
JPH0562786B2 true JPH0562786B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-09-09

Family

ID=15841189

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16698186A Granted JPS6324343A (ja) 1986-07-16 1986-07-16 Ｉ／ｏアドレスデコ−ド方式

Country Status (1)

Country Link
JP (1) JPS6324343A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02253460A (ja) * 1989-03-28 1990-10-12 Nec Eng Ltd 制御システム
US5561821A (en) * 1993-10-29 1996-10-01 Advanced Micro Devices System for performing I/O access and memory access by driving address of DMA configuration registers and memory address stored therein respectively on local bus
JPH07183926A (ja) * 1993-12-24 1995-07-21 Uchu Tsushin Kiso Gijutsu Kenkyusho:Kk Ｑｐｓｋプリアンブル信号発生器

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58223831A (ja) * 1982-06-23 1983-12-26 Nec Corp 入出力機器選択方式
JPS60122449A (ja) * 1983-12-07 1985-06-29 Mitsubishi Electric Corp アドレス可変方式の入出力制御装置

Also Published As

Publication number Publication date
JPS6324343A (ja) 1988-02-01

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