JPH0562383B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address translation device in an information processing system.

In an information processing system using a microprocessor, when the microprocessor selects one of the various input/output ports connected to it, when the microprocessor sends out a corresponding address signal, the address translation device selects the desired input/output port. The signal is converted into an input/output selection signal for selecting a desired input/output port.

Note that if the configuration of the information processing system is changed and the addresses assigned to each input/output port are changed, the microprocessor must be able to immediately select the required input/output port using the new address signal. requested.

[Conventional technology]

FIG. 2 is a diagram showing an example of a conventional address translation device, and FIG. 3 is a diagram showing another example of a conventional address translation device.

In FIG. 2, of an address signal a sent from a microprocessor (not shown) to an address bus 1, several high-order bits are input to a decoder 2, and the remaining low-order bits are input to decoders 3 and 4.

The decoder 2 converts the input upper bits into either circuit designation signals c1 or c2, and when the address valid signal b sent from the microprocessor is input to the decoder 2, the converted circuit designation signal c1 or output from c2 and transmit it to decoder 3 or 4.

Decoders 3 and 4 convert the lower bits of the input address signal a into an input/output selection signal d that selects the corresponding input/output port, but when the circuit designation signal c1 is output from the decoder 2, the decoder 3 outputs an input/output selection signal d, and when a circuit designation signal c2 is output, a decoder 4 outputs an input/output selection signal d, which is transmitted to an input/output port (not shown).

In such an address conversion device, since the input/output selection signal d converted and outputted with respect to the input address signal a is fixed by the decoders 2 to 4, the address given to the input/output port is changed. In this case, it is necessary to replace decoders 2 to 4.

Next, in FIG. 3, read-only memories (ROM) 5 and 6 are used in place of decoders 3 and 4 in FIG. 2, respectively.
The read-only memories 5 and 6 have an address signal a
Corresponding input/output selection signals d are stored at the addresses indicated by the lower bits of .

Also in FIG. 3, of the address signal a sent from a microprocessor (not shown) to the address bus 1, several high-order bits are input to the decoder 2, and the remaining low-order bits are input to the read-only memories 5 and 6.

As in FIG. 2, the decoder 2 converts the input upper bit into either circuit designation signal c1 or c2, and when the address valid signal b is input from the microprocessor, the converted circuit designation signal c1 or c2 is output and transmitted to read-only memory 5 or 6.

The read-only memory 5 or 6 to which the circuit designation signal c1 or c2 is input extracts the input/output selection signal d corresponding to the lower bit of the input address signal a and transmits it to an input/output port (not shown).

In such an address conversion device, the input/output selection signal d converted and outputted with respect to the input address signal a is fixed by the decoder 2 and the read-only memories 5 and 6, so that the input/output selection signal d applied to the input/output port is If the address changes, the decoder 2 and read-only memories 5 and 6 must be converted.

[Problem that the invention seeks to solve]

As is clear from the above explanation, in a conventional address conversion device, the input/output selection signal d to be converted and output is fixed for the input address signal a, so the address given to the input/output port is If the address changes, it is necessary to replace the decoder or the read-only memory, making it impossible to quickly deal with the address change.

[Means for solving problems]

The above problem can be solved by the present invention, which includes a comparison circuit that compares the upper few bits of the address signal from the data bus with the upper few bits of the address signal from the address bus, and outputs a circuit designation signal if they match; Write in which the lower bits of the signal excluding the upper few bits, the circuit designation signal from the comparison circuit, the input/output selection signal corresponding to the address signal from the data bus via the gate, and the write or read signal are applied. Consisting of a read memory, the upper few bits of the address signal from the data bus and an input/output selection signal corresponding to the address signal,
When the address signal and write signal from the address bus are input, the circuit designation signal from the comparison circuit, the lower bits excluding the upper few bits from the address bus, the input/output selection signal from the data bus, and the write signal are input. The input/output selection signal is written into the read/write memory at the location corresponding to the lower bits of the address signal and the circuit designation signal, and the upper bits of the address signal from the data bus and the upper bits of the address signal from the address bus are written into the read/write memory. When the address signal and read signal are input,
An address characterized in that an input/output selection signal corresponding to an address signal is outputted from a write/read memory by a circuit designation signal from a comparison circuit, lower bits excluding the upper few bits from an address bus, and a read signal. The problem is solved by a converter.

[Effect]

That is, according to the present invention, since the input/output selection signal converted and output in response to the input address signal can be written from the microprocessor to the read/write memory, the address given to the input/output port is When the address is changed, by immediately updating the input/output selection signal in the write/read memory, it becomes possible to easily correspond to the new address.

Further, according to the present invention, since only the lower bits of the address signal are used as the address of the read/write memory, it is possible to reduce the capacity of the memory.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an address translation device according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 1, a register 7 and a comparison circuit 8 are used instead of the decoder 2 in FIGS. 2 and 3.
However, a write/read memory (RAM) 9 is provided in place of the decoders 3 and 4 in FIG. 2 or the read-only memories 5 and 6 in FIG. 3.

In FIG. 1, when storing the input/output selection signal d from the write/read memory 9 from a microprocessor (not shown), an address signal a is sent to the address bus 1, and an input signal corresponding to the address signal a is sent to the data bus 10. It sends out the output selection signal d and the upper few bits of the address signal a, and also inputs the write signal w to the register 7 and the write/read memory 9, and the conduction state control signal to the gates 11 to 13. register 7
is the address signal a input from the data bus 10
The upper bits of the data are accumulated and transmitted to the comparator circuit 8.
Address signal a input from address bus 1
The upper few bits are input to the comparison circuit 8, and the remaining lower bits are input to the write/read memory 9. Since the upper bits transmitted from the register and the upper bits input from the address bus match, the comparator circuit 8 outputs a circuit designation signal c and transmits it to the read/write memory 9. Further, the input/output selection signal d input to the data bus 10 is input to the write/read memory 9 via the gate 11 which is in a conductive state, but the conductive state control signal is inverted and given to the gate 12. The gate 12 is in a cutoff state, and the input/output selection signal d is not transmitted to an input/output port (not shown). Furthermore, gate 1 is in a conductive state.
A write signal w input from the microprocessor is input to the write/read memory 9 via the microprocessor 3.

As a result, in the write/read memory 9, the input/output selection signal d is stored at the address corresponding to the lower bit of the address signal a and the circuit designation signal.
Once stored, the microprocessor switches to gate 1.
The conduction state control signals input to terminals 1 to 13 are stopped. As a result, gates 11 and 13 are turned off, and gate 12 is turned on.

Similarly, the corresponding input/output selection signal d is stored in each address of the write/read memory 9.

Next, when the microprocessor sends the address signal a to the address bus 1 and the upper few bits of the address signal to the data bus 10 in order to transmit the input/output selection signal d to the input/output port, the upper bits of the address signal a Several bits are input to the comparison circuit 8, and the remaining lower bits are input to the read/write memory 9.
Comparison circuit 8 compares the upper bits stored in register 7 and the upper bits input from address bus 1, and if they match, it outputs circuit designation signal c and transmits it to read/write memory 9. . Further, when the read signal r from the microprocessor is input to the write/read memory 9 via the gate 13 which is in a conductive state, the read/write memory 9 outputs a signal corresponding to the lower bit of the input address signal a. The stored input/output selection signal d is extracted and transmitted to the input/output port via the gate 12 which is in a conductive state.

As is clear from the above explanation, according to the present embodiment, any input/output selection signal d can be stored in the write/read memory 9 at any address from the microprocessor, and the address can be stored from the microprocessor. By inputting , it becomes possible to output the stored input/output selection signal d. Therefore, even if the address given to the input/output port is changed, the change can be easily handled by updating the input/output selection signal d stored in the write/read memory 9.

Furthermore, since the input/output selection signal to the write/read memory is stored in a position specified by only the lower bits of the address signal, a small capacity write/read memory is required.

Note that FIG. 1 is only one embodiment of the present invention, and for example, the number of write/read memories 9 is not limited to one set, and it is possible to provide a plurality of sets.
In either case, the effects of the present invention remain the same.

〔Effect of the invention〕

As described above, according to the present invention, in the information processing system, the input/output selection signal converted and output in response to the input address signal can be written from the microprocessor to the read/write memory.
When the address given to the input/output port is changed, by immediately updating the input/output selection signal in the write/read memory, it becomes possible to easily correspond to the new address.

Further, since only the lower bits of the address signal are used to designate the address of the read/write memory, the capacity of the memory can be small.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an address translation device according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a conventional address translation device, and FIG. 3 is a diagram showing another example of a conventional address translation device. It is a diagram. In the figure, 1 is an address bus, 2 to 4 are decoders, 5 and 6 are read-only memories (ROM),
7 is a register, 8 is a comparison circuit, 9 is a write/read memory (RAM), 10 is a data bus, 11 to 13
is a gate, a is an address signal, b is an address valid signal, c, c1 and c2 are circuit designation signals, and d is an input/output selection signal.

Claims (1)

[Claims] 1 Comparison circuit that compares the high-order bits of the address signal from the data bus with the high-order bits of the address signal from the address bus and outputs a circuit designation signal if they match, and the high-order bits of the address signal from the address bus. It consists of a write/read memory to which lower bits excluding the data bus, a circuit designation signal from a comparator circuit, an input/output selection signal corresponding to an address signal from a data bus via a gate, and a write or read signal are applied. When the upper few bits of the address signal and the input/output selection signal corresponding to the address signal, the address signal from the address bus, and the write signal are input from the bus, the circuit designation signal from the comparator circuit and the input/output selection signal corresponding to the address signal are input from the comparator circuit, The input/output selection signal is set in the write/read memory at the location corresponding to the lower bits of the address signal and the circuit designation signal by the lower bits excluding the upper few bits, the input/output selection signal from the data bus, and the write signal. written, the upper few bits of the address signal from the data bus,
When the address signal and read signal from the address bus are input, the circuit designation signal from the comparison circuit, the lower bits excluding the upper few bits from the address bus, and the read signal are used to perform input/output corresponding to the address signal. An address translation device characterized in that a selection signal is output from a read/write memory.