JPS5930139A - Bit pattern comparing device - Google Patents

Abstract

PURPOSE:To reduce a hardware quantity, by forming a comparing data by the address of an RAM, and forming the compared result output by a data, in a bit pattern comparing device of channel interface control. CONSTITUTION:A coincidence signal and a comparison result output signal are written in an address of an RAM, which coincides with a bit pattern of an address signal. Therefore, a signal line 6 and 15 are connected by switching a selector 12, an address signal is inputted, and in accordance with it, the coincidence signal and the comparison result output signal are written in a data column from a write data signal line 11. An address signal on a signal line 1 is inputted through the signal line 15 by switching the selector 12, and only when the bit pattern coincides with the address of the RAM, a signal is outputted to a coincidence output signal line 5 and a comparison result output signal line 9. In this way, the bit pattern is compared by the RAM.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a bit pattern comparison device for comparing bit patterns of address signals for channel interface control in input/output control.

Structure of the Prior Art Conventionally, there has been a device of this type as shown in Fig. 1. In the figure, (1) is an address signal line, and (2-re) is an address signal line.

<2-2) e...-(2-n) are address registers, (3-1), (3-2), ------
(3-n) are comparators, (4; is an OR circuit, (
5; is a coincidence output signal line, (6) is a data signal line, (7-
1), (7-2), ... (7-n) are set signal lines, ()l-1), (8-2), ... (8-++
) are address registers ('2-1) and (2-2
), =・(2-n), the output signal line that outputs 'IO+, (9-1), (9-2), ... (9-n) is the ratio ll@l'd'ii, respectively. (3-1), (3-2),
...(3n) comparison result output signal line.

For convenience of explanation below, the address signal is composed of 8 bits, and therefore the signal lines t1. l, +61, +8
1 performs bit parallel transmission using eight signal lines.

Operation of the Prior Art The device shown in FIG.
The bit pattern of class m is the address register (21), (
22L...(2-n) is stored in advance.

To store this, output the address signal of the bit pattern to be stored in the address register (2-1) on the signal line (61), send a set signal to the signal line (7-1), and then (6) Output the address signal of the bit pattern to be stored in the address register (2-2) on the
It is sufficient to send a set signal to i (7-2), repeat this operation, and finally store the address signal of the nth bit pattern in the address register (2-n).

Each address register (2-1) + (2-2), -(2-
1) When the address signal is sent from the channel to the signal # (I+) after the setting to each comparator (3-1
), (3-2).

...If there is a match after the comparison is made in (3-n), the signal logic of the comparison result output signal line (9-i) of the comparator becomes "1", and the match output signal line (5) The above coincidence output signal also becomes logic "1".

Disadvantages of the prior art Since the conventional device is configured as described above, it has n address registers, n comparators, and n input OR circuits.
There is a drawback that as the value of hair binding n increases, the amount of hardware increases.

Purpose of the Invention The present invention was made to eliminate the drawbacks of the conventional ones as described in (1) above.
It is an object of the present invention to provide a comparator that requires less hardware by writing MK and reading it from a RAM using an address signal from a channel.

Structure of the Present Invention The following is a detailed explanation of the present invention with reference to the drawings. Figure 2 is a block diagram showing an embodiment of the present invention, in which the same reference numerals as in Figure 1 indicate the same parts, and the case where n=7 is shown. ing.

(10) is RAM, (Ill is 1 data signal line, θ
One is the selector, (1, 31 are switching signal lines, 04 is RA
Write command signal line to M++01, α→ is RAM+1
The contents of the signal line [11 or (61) are output on the address signal line to 111.

As in the numerical example in FIG. 1, the address on the signal line (1) has an 8-bit configuration, and RAMll0I has an 8-bit address configuration. Figure 3'3 shows an example of the contents of R-AMjlUl, and the value obtained by reading the bit pattern of the 8-bit address as a 2-digit hexadecimal number is shown in the HEX column. About the HEX column 01, 03゜05
, (This shows an example of detecting whether any of the seven types (n=7) of bit patterns of 17, 09, OB, and OD match the bit pattern of the address signal of the signal line fil 1.RAMtlOi The data also has an 8-bit configuration, and the bit numbers are indicated by 0 to 7.
The number pit is a specific bit and this is used as a coincidence output signal.

Due to the bit pattern of bits other than this specific bit, that is, pits 0 to 6, the matched bit pattern is 7
Indicates which species it is. That is, when the 0th bit is rlJ, it means that HEX (01) matches, and when the 1st bit is rlJ, it means that HEX (03) matches.

Operation of the present invention First, data shown in the data column of FIG. 3 is written. That is, the selector αa outputs the data signal on the signal m(6) as an address signal on the signal line αυ, and this signal changes sequentially from HEX(00) to HEX(FFn), that is, from 0 to 28-1. Corresponding to this change, the signal on the write data signal line (Ill) changes as shown in the data column in Figure 3. Every time a command signal is sent to the write command signal line 0→, the signal line (11) at that time The above data signal is put into the negative address position indicated by the address signal on the signal line a9, and the content of the RAM song becomes as shown in Figure 3. The data at the address location is 8 “0”
” pits, so when initializing the RAM 11■, set all bits of data to 10” and connect the signal line (6
The address signals on 1 are 01, 03,
05, 07.

There are only seven types of changes: 09, OB, and OD, and only the corresponding data needs to be written. Also, RAM+
If the content that should be put in 101 does not change, RAM
110), a ROM (read-only memory) may be used and 1 may be written to the ROM only once at the beginning.

When writing to RAM l1f)l is completed, switch the selector α.

If the signals on the signal lines fil, J, : are output as address signals on the signal line αυ, the bit pattern of the address signal on the signal line tll becomes RAM f as shown in FIG.
HEXOl in the address field of lof, 03, 05, 07,
09. OB.

The 7th bit of the read data word becomes "1" and is output on the match output signal line (5) only when it matches any of the ODs, and any of the 0th to 6th bits becomes "1".
l' and the comparison result output signal lines (9-1), (9-2
), ... (9-7).

Other Embodiments of the Invention Although the present invention has been described above with reference to an example of detecting coincidence of bit patterns of address signals, it is possible to detect coincidence of bit patterns of any digital signal, not just address signals. Furthermore, although we have described the case where the address signal to be detected for all matches of bit patterns has an 8-bit configuration, it is also possible to detect matches of bit patterns of digital signals with m-pit configuration by setting m to any positive integer. In this case, the RAM address has an m-bit configuration.

Furthermore, in the example shown in Fig. 3, each one of bits 0 to 6 of the data column is directly output to each comparison result output line, but a code representing the comparison result output signal is constructed using a plurality of Piratra, and the code is output by a decoder. If this code is decoded and output to each comparison result output line, the type of bit pattern to be compared will be 1 (the number corresponding to n in Figure 1).
can be further increased.

Effects of the present invention As described above, according to the present invention, comparative data can be stored in RAM.
The match output and comparison result output are configured with the address of RA.
Since it is configured with data for the above address of M, it is possible to obtain a bit pattern comparison device with a reduced amount of hardware and improved reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing the RA of FIG.
It is a figure which shows an example of the content of M. +11...address signal line, (5:...match output signal line, (6)...-data signal line, 10)...RAM
,flt...Write data (line 8, Q selector, (9)...address signal line, (9-1), (9-
2)...(9-7)...Comparison result output signal lines. Note that the same reference numerals in the figures indicate the same or equivalent parts. Figure 1 6 Figure 2

Claims (1)

[Claims] In a bit pattern comparison device that detects whether the bit pattern of a word consisting of m bits (one word consists of m bits) (m is any positive integer) matches any of a plurality of predetermined bit patterns, A memory device that has continuous addresses between 1 and 2m-1 and is capable of reading and writing data at a specified address position, and any one of the plurality of predetermined bit patterns in this memory device. means for writing logic "C1" into all bits of data at an address position having a bit pattern that does not match with any of the bit patterns; A specific hit in the data at an address position with a pattern is given a logic “match” output signal.
m bits to be compared; and means for reading out the memory device using a word as an address.