JPH0559584B2 - - Google Patents

Info

Publication number
JPH0559584B2
JPH0559584B2 JP58020044A JP2004483A JPH0559584B2 JP H0559584 B2 JPH0559584 B2 JP H0559584B2 JP 58020044 A JP58020044 A JP 58020044A JP 2004483 A JP2004483 A JP 2004483A JP H0559584 B2 JPH0559584 B2 JP H0559584B2
Authority
JP
Japan
Prior art keywords
circuit
wiring
signal line
flip
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58020044A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59145564A (ja
Inventor
Masahiro Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP58020044A priority Critical patent/JPS59145564A/ja
Publication of JPS59145564A publication Critical patent/JPS59145564A/ja
Publication of JPH0559584B2 publication Critical patent/JPH0559584B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65—Integrated injection logic

Landscapes

  • Bipolar Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP58020044A 1983-02-09 1983-02-09 半導体集積装置 Granted JPS59145564A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58020044A JPS59145564A (ja) 1983-02-09 1983-02-09 半導体集積装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58020044A JPS59145564A (ja) 1983-02-09 1983-02-09 半導体集積装置

Publications (2)

Publication Number Publication Date
JPS59145564A JPS59145564A (ja) 1984-08-21
JPH0559584B2 true JPH0559584B2 (enrdf_load_stackoverflow) 1993-08-31

Family

ID=12016053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58020044A Granted JPS59145564A (ja) 1983-02-09 1983-02-09 半導体集積装置

Country Status (1)

Country Link
JP (1) JPS59145564A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2587924B2 (ja) * 1986-10-11 1997-03-05 日本電信電話株式会社 薄膜形成装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS492872A (enrdf_load_stackoverflow) * 1972-04-22 1974-01-11
JPS57111045A (en) * 1980-12-26 1982-07-10 Fujitsu Ltd Laying out method for integrated circuit cell

Also Published As

Publication number Publication date
JPS59145564A (ja) 1984-08-21

Similar Documents

Publication Publication Date Title
US3138747A (en) Integrated semiconductor circuit device
US3849872A (en) Contacting integrated circuit chip terminal through the wafer kerf
US3762037A (en) Method of testing for the operability of integrated semiconductor circuits having a plurality of separable circuits
US5378941A (en) Bipolar transistor MOS transistor hybrid semiconductor integrated circuit device
JPH061802B2 (ja) 半導体装置
US4388755A (en) Structure for and method of manufacturing a semiconductor device by the master slice method
EP0021661B1 (en) Semiconductor master-slice device
JPH0559584B2 (enrdf_load_stackoverflow)
US3993934A (en) Integrated circuit structure having a plurality of separable circuits
KR920004225B1 (ko) 마스터 슬라이스(Master slice)방법을 사용하여 반도체 집적회로를 형성하는 방법
JPS6329826B2 (enrdf_load_stackoverflow)
JP2687970B2 (ja) Ｉｉｌ半導体集積回路装置
EP0073608B1 (en) Masterslice integrated circuit device and method for manufacturing the same
JP2811740B2 (ja) 集積回路
JPH0425710B2 (enrdf_load_stackoverflow)
US5237215A (en) ECL master slice gates with different power levels
JPH04225548A (ja) 集積回路装置
JPS6128257B2 (enrdf_load_stackoverflow)
JPH0120538B2 (enrdf_load_stackoverflow)
JPS59222958A (ja) 半導体集積装置
JP2878765B2 (ja) 半導体装置
JPS61114568A (ja) 半導体装置
JPS63234553A (ja) 半導体集積回路装置
JPS614978A (ja) 論理集積回路
JPH0226046A (ja) マスター・スライス半導体集積回路装置