JPH0556029B2 - - Google Patents
Info
- Publication number
- JPH0556029B2 JPH0556029B2 JP12950487A JP12950487A JPH0556029B2 JP H0556029 B2 JPH0556029 B2 JP H0556029B2 JP 12950487 A JP12950487 A JP 12950487A JP 12950487 A JP12950487 A JP 12950487A JP H0556029 B2 JPH0556029 B2 JP H0556029B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- active layer
- donut
- light emitting
- shaped recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000013307 optical fiber Substances 0.000 description 9
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000007774 longterm Effects 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
Description
この発明は、高出力で且つ光フアイバに効率良
く光を入射させることのできる、光通信に好適な
発光ダイオード関する。
The present invention relates to a light emitting diode suitable for optical communication, which has high output and can efficiently input light into an optical fiber.
光通信システムの長距離化や伝送マージンの向
上を図るため、発光ダイオードの高出力化ととも
に、光フアイバに効率良く光を入射させることが
できる構造を有する発光ダイオードが研究されて
いる。
発光ダイオードは基本的に、たとえば第３図に
示すような構造となつている。すなわち、ｎ−
InP基板１０の裏面上にｎ−InP層（バツフア層）
１１、ｐ−InGaAsP層（活性層）１２、ｐ−InP
層（バツフア層）１３、ｐ−InGaAsP層（キヤ
ツプ層）１４を順次にエピタキシヤル成長させ、
さらにその上にSiO2層（絶縁層）１５を設け、
このSiO2層１５に窓を形成してｐ−電極１６を
付けることによつて窓部分でのみコンタクトを形
成する。そして表面上にｎ−電極１７を設けて、
これらの電極間に電流を流すことによつて、pn
接合に順方向電流を流して活性層１２から光を発
生させる。
なお、この明細書ではｎ−InP層１１、ｐ−
InP層１３をバツフア層１３というが、一般には
クラツド層と称されることも多い。
この場合、ｐ−電極１６がSiO2層１５の窓部
でのみｐ−InGaAsP層１４に接触するようにし
たのはなるべく狭い範囲で電流を流すことにより
発光領域を限定するためであるが、それでも第３
図の構造の場合はｐ−電極１６から注入された電
流はキヤツプ層１４、バツフア層１３を経て活性
層１２に流れ、その電流の拡がりに応じて発光領
域が大きくなつてしまうことが避けられない。そ
のため、たとえばｐ−電極１６の直径を30μｍと
したときでも発光領域は直径50μｍ程度となつて
しまう。その結果、この光を光フアイバに光を入
射させる場合、結合効率が悪くて入射パワーがそ
れほど大きくならない欠点がある。これを避ける
ために電極１６の直径を小さくすることも考えら
れなくもないが、そうすると電極１６部分の抵抗
が大きくなつて抵抗発熱などの問題が生じる。
そこで、第４図のように裏面側からエツチング
して活性層１２を貫通するようなドーナツ状凹部
６１を形成して、この凹部６１の内側の活性層１
２のみを発光領域とすることが提案されている
（特開昭61−125092号公報）。
In order to extend the distance and improve the transmission margin of optical communication systems, research is being carried out on increasing the output of light emitting diodes and on light emitting diodes that have a structure that allows light to enter optical fibers efficiently. A light emitting diode basically has a structure as shown in FIG. 3, for example. That is, n-
n-InP layer (buffer layer) on the back surface of the InP substrate 10
11, p-InGaAsP layer (active layer) 12, p-InP
A layer (buffer layer) 13 and a p-InGaAsP layer (cap layer) 14 are epitaxially grown in sequence.
Furthermore, a SiO 2 layer (insulating layer) 15 is provided on it,
By forming a window in this SiO 2 layer 15 and attaching the p-electrode 16, a contact is formed only at the window portion. Then, an n-electrode 17 is provided on the surface,
By passing a current between these electrodes, pn
Light is generated from the active layer 12 by passing a forward current through the junction. Note that in this specification, the n-InP layer 11, the p-
Although the InP layer 13 is called a buffer layer 13, it is generally often called a cladding layer. In this case, the reason why the p-electrode 16 is brought into contact with the p-InGaAsP layer 14 only at the window portion of the SiO 2 layer 15 is to limit the light-emitting region by flowing current in as narrow a range as possible. Third
In the structure shown in the figure, the current injected from the p-electrode 16 flows through the cap layer 14 and the buffer layer 13 to the active layer 12, and it is inevitable that the light emitting region will become larger as the current spreads. . Therefore, even if the diameter of the p-electrode 16 is 30 μm, the light emitting region will have a diameter of about 50 μm. As a result, when this light is made to enter an optical fiber, there is a drawback that the coupling efficiency is poor and the incident power is not very large. In order to avoid this, it is possible to reduce the diameter of the electrode 16, but this would increase the resistance of the electrode 16 and cause problems such as resistance heat generation. Therefore, as shown in FIG. 4, a donut-shaped recess 61 that penetrates the active layer 12 is formed by etching from the back side, and the active layer 1 inside the recess 61 is etched.
It has been proposed to make only 2 the light emitting region (Japanese Patent Application Laid-Open No. 125092/1982).
しかしながら、上記の第４図のようなドーナツ
状凹部６１を設ける場合、活性層１２の側面がエ
ツチング時に露出し、しかもその上にSiO2層１
５が設けられるので、その界面で非発光のリーク
電流が生じたり、熱膨張差に起因する歪を受ける
など、長期信頼性の点及び高電流動作の点などで
問題がある。
この発明は、発光領域の広がりを抑えて光フア
イバとの結合効率を良好にすることができ、しか
も長期信頼性に優れた発光ダイオードを提供する
ことを目的とする。
However, when providing the donut-shaped recess 61 as shown in FIG .
5, there are problems in terms of long-term reliability and high current operation, such as non-emission leakage current occurring at the interface and distortion due to thermal expansion difference. SUMMARY OF THE INVENTION An object of the present invention is to provide a light emitting diode that can suppress the spread of the light emitting region and improve the coupling efficiency with an optical fiber, and has excellent long-term reliability.
この発明によれば、半導体基板の１表面上に活
性層とバツフア層とを順次成長させてなる発光ダ
イオードにおいて、上記の表面側から上記活性層
とバツフア層との境界面までを除去して発光領域
とすべき部分の周囲にドーナツ状の凹部を形成
し、該ドーナツ状凹部に囲まれ中央に残つた部分
と上記基板の他の表面上とに電極を設けたことを
特徴とする。
According to this invention, in a light emitting diode in which an active layer and a buffer layer are sequentially grown on one surface of a semiconductor substrate, the portion from the surface side to the interface between the active layer and the buffer layer is removed to emit light. It is characterized in that a donut-shaped recess is formed around the portion to be the region, and electrodes are provided on the portion surrounded by the donut-shaped recess and remaining in the center and on the other surface of the substrate.
ドーナツ状凹部に囲まれ中央に残つた部分に電
極が設けられているため、このドーナツ状凹部に
囲まれた部分の活性層のみに電流が流れ、電流の
拡がりがないので発光効率が向上し、しかも発光
領域がこのドーナツ状凹部に囲まれた部分に限定
されるため、光フアイバへの入射効率が向上す
る。
ドーナツ状凹部は活性層を貫通することなく、
活性層とバツフア層との境界面までにとどまつて
いるため、活性層の側面が外気に晒されず、その
結果、界面での非発光のリーク電流が生じない。
Since the electrode is provided in the part surrounded by the donut-shaped recess and left in the center, current flows only in the active layer in the part surrounded by the donut-shaped recess, and the current does not spread, improving luminous efficiency. Furthermore, since the light emitting region is limited to the area surrounded by the donut-shaped recess, the efficiency of incidence into the optical fiber is improved. The donut-shaped recess does not penetrate the active layer.
Since it remains at the interface between the active layer and the buffer layer, the side surfaces of the active layer are not exposed to the outside air, and as a result, no non-luminous leakage current occurs at the interface.
第１図において、ｎ−InP基板１０の裏面上に
ｎ−InP層（バツフア層）１１、InGaAsP層（活
性層）１２、ｐ−InP層（バツフア層）１３、ｐ
−InGaAsP層（キヤツプ層）１４を順次エピタ
キシヤル成長させる。次に裏面側からエツチング
を行なつて、直径約30μｍの発光領域の周囲に、
たとえば幅20μｍのドーナツ状凹部２１を形成す
る。このとき、活性層１２とバツフア層１３との
界面までがエツチングにより取り除かれる。この
ようにエツチングを活性層１２とバツフア層１３
との界面で停止させることは、選択エツチング法
を使用することにより容易に実行できる。
その後、SiO2層（絶縁層）１５を全面に形成
する。そしてドーナツ状凹部２１に囲まれた部分
の頂上の位置に、SiO2層１５に窓を形成し、ｐ
−電極１６を付ける。さらにｎ−InP基板１０の
表面側にｎ−電極１７と反射防止コート１８を設
ける。また、裏面側にAuめつき層２２を設けて
Siヒートシンク２３上に配置する。ｐ側およびｎ
側の電極１６，１７はいずれもAuPtTi系高融点
金属を用いる。
このように、ドーナツ状凹部２１により囲ま
れ、残つている部分の活性層１２にのみ電流が流
れるような構造としたので、発光領域が直径約３
０μｍとなる。また、ドーナツ状凹部２１の中央
に残つている部分のバツフア層１３にのみ電流が
流れ、電流の拡がりがないため、発光効率が高
く、また発光領域が小さいため光フアイバとの結
合効率も高くなる。したがつて、光フアイバへの
入射光パワーを大きくでき、光通信用光源として
好適である。
また、ドーナツ状凹部２１はその深さが活性層
１２とバツフア層１３との界面にまでしか到達し
ないので、活性層１２の側面が露出せず、さらに
この側面の絶縁層１５が形成されることもないの
で、界面での非発光のリーク電流が生じることが
なく、さらに熱膨張係数差に起因する信頼性の低
下原因もない。
第２の実施例では、第２図に示すように活性層
１２とバツフア層１３との間に予めInGaAsPエ
ツチ止層２４が設けられている。そのため、ドー
ナツ状の凹部２１を形成するためのエツチングを
このエツチ停止層２４でとどめることができ、活
性層１２は全く外気に触れることがなくなるの
で、長期信頼性が一層高い。このエツチ停止層２
４は活性層１２よりもエネルギーギヤツプが広く
とられており、そのため注入キヤリアは活性層１
２に注入される。
In FIG. 1, on the back surface of an n-InP substrate 10, an n-InP layer (buffer layer) 11, an InGaAsP layer (active layer) 12, a p-InP layer (buffer layer) 13, a p-InP layer (buffer layer) 11,
- Sequentially epitaxially grow InGaAsP layers (cap layers) 14; Next, etching is performed from the back side, and the area around the light emitting area with a diameter of approximately 30 μm is etched.
For example, a donut-shaped recess 21 having a width of 20 μm is formed. At this time, even the interface between the active layer 12 and the buffer layer 13 is removed by etching. In this way, etching is performed on the active layer 12 and the buffer layer 13.
Stopping at the interface can be easily achieved by using a selective etching method. Thereafter, a SiO 2 layer (insulating layer) 15 is formed over the entire surface. Then, a window is formed in the SiO 2 layer 15 at the top position of the portion surrounded by the donut-shaped recess 21, and p
- Attach the electrode 16. Furthermore, an n-electrode 17 and an antireflection coating 18 are provided on the front side of the n-InP substrate 10. In addition, an Au plating layer 22 is provided on the back side.
It is placed on the Si heat sink 23. p side and n
The side electrodes 16 and 17 are both made of AuPtTi-based high melting point metal. In this way, the structure is such that current flows only through the remaining active layer 12 surrounded by the donut-shaped recess 21, so that the light emitting region has a diameter of approximately 3 mm.
It becomes 0 μm. In addition, since the current flows only in the portion of the buffer layer 13 remaining in the center of the donut-shaped recess 21 and there is no spread of the current, the light emitting efficiency is high, and since the light emitting area is small, the coupling efficiency with the optical fiber is also high. . Therefore, the power of the light incident on the optical fiber can be increased, making it suitable as a light source for optical communication. Further, since the depth of the donut-shaped recess 21 reaches only the interface between the active layer 12 and the buffer layer 13, the side surface of the active layer 12 is not exposed and the insulating layer 15 is formed on this side surface. Therefore, there is no non-luminous leakage current at the interface, and there is no cause for reliability deterioration due to a difference in thermal expansion coefficient. In the second embodiment, as shown in FIG. 2, an InGaAsP etch stop layer 24 is provided in advance between the active layer 12 and the buffer layer 13. Therefore, the etching for forming the donut-shaped recess 21 can be stopped by the etch stop layer 24, and the active layer 12 is not exposed to the outside air at all, resulting in higher long-term reliability. This sex stop layer 2
4 has a wider energy gap than the active layer 12, so the injection carrier is in the active layer 1.
Injected into 2.
この発明による発光ダイオードは、発光領域の
広がりを抑えることができるので光フアイバと結
合効率が高いことから、光フアイバ通信に好適で
ある。また、活性層の側面が外気に晒されること
がないので、界面での非発光のリーク電流が生ぜ
ず、発光効率が高くなる。さらに、活性層の側面
に絶縁膜を設けていないので、熱膨張係数差によ
る歪を受けず、その結果、長期信頼性に優れる。
The light emitting diode according to the present invention is suitable for optical fiber communication because it can suppress the spread of the light emitting area and has a high coupling efficiency with an optical fiber. Furthermore, since the side surfaces of the active layer are not exposed to the outside air, non-emission leakage current does not occur at the interface, increasing luminous efficiency. Furthermore, since no insulating film is provided on the side surfaces of the active layer, there is no distortion due to differences in thermal expansion coefficients, resulting in excellent long-term reliability.
第１図はこの発明の一実施例の断面図、第２図
は他の実施例の断面図、第３図および第４図は従
来例の断面図である。
１０……ｎ−InP基板、１１……ｎ−InP層、
１２……活性層、１３……ｐ−InP層、１４……
ｐ−InGaAsP層、１５……SiO2層、１６……ｐ
−電極、１７……ｎ−電極、１８……反射防止コ
ート、２１，６１……ドーナツ状凹部、２２……
Auめつき層、２３……Siヒートシンク、２４…
…エツチ停止層。
FIG. 1 is a sectional view of one embodiment of the present invention, FIG. 2 is a sectional view of another embodiment, and FIGS. 3 and 4 are sectional views of a conventional example. 10... n-InP substrate, 11... n-InP layer,
12... Active layer, 13... p-InP layer, 14...
p-InGaAsP layer, 15...SiO 2 layer, 16...p
-electrode, 17... n-electrode, 18... antireflection coating, 21, 61... donut-shaped recess, 22...
Au-plated layer, 23...Si heat sink, 24...
...Naughty stop layer.
Claims (1)
とを順次成長させてなる発光ダイオードにおい
て、上記の表面側から上記活性層とバツフア層と
の境界面までを除去して発光領域とすべき部分の
周囲にドーナツ状の凹部を形成し、該ドーナツ状
凹部に囲まれ中央に残つた部分と上記基板の他の
表面上とに電極を設けたことを特徴する発光ダイ
オード。 ２ 上記半導体基板はｎ型半導体基板よりなり、
上記バツフア層はｐ型半導体層よりなることを特
徴とする特許請求の範囲第１項記載の発光ダイオ
ード。[Claims] 1. A light emitting diode in which an active layer and a buffer layer are sequentially grown on one surface of a semiconductor substrate, in which a portion from the surface side to the interface between the active layer and the buffer layer is removed. A light-emitting diode characterized in that a donut-shaped recess is formed around a portion to be a light-emitting region, and electrodes are provided on the portion surrounded by the donut-shaped recess and remaining in the center and on the other surface of the substrate. 2. The semiconductor substrate is an n-type semiconductor substrate,
2. The light emitting diode according to claim 1, wherein said buffer layer is made of a p-type semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62129504A JPS63292684A (en) | 1987-05-25 | 1987-05-25 | Light emitting diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62129504A JPS63292684A (en) | 1987-05-25 | 1987-05-25 | Light emitting diode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63292684A JPS63292684A (en) | 1988-11-29 |
| JPH0556029B2 true JPH0556029B2 (en) | 1993-08-18 |
Family
ID=15011120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62129504A Granted JPS63292684A (en) | 1987-05-25 | 1987-05-25 | Light emitting diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63292684A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100734374B1 (en) * | 2006-03-21 | 2007-07-03 | 엘지전자 주식회사 | Led having vertical structure and method for manufacturing the same |
-
1987
- 1987-05-25 JP JP62129504A patent/JPS63292684A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63292684A (en) | 1988-11-29 |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |