JPH02238687A - Groove structure semiconductor device - Google Patents
Groove structure semiconductor deviceInfo
- Publication number
- JPH02238687A JPH02238687A JP5782489A JP5782489A JPH02238687A JP H02238687 A JPH02238687 A JP H02238687A JP 5782489 A JP5782489 A JP 5782489A JP 5782489 A JP5782489 A JP 5782489A JP H02238687 A JPH02238687 A JP H02238687A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- groove
- type inp
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005253 cladding Methods 0.000 claims description 12
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 2
- 230000002517 constrictor effect Effects 0.000 abstract 1
- 230000002265 prevention Effects 0.000 abstract 1
- 230000000903 blocking effect Effects 0.000 description 11
- 238000000034 method Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 101150110330 CRAT gene Proteins 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/223—Buried stripe structure
- H01S5/2237—Buried stripe structure with a non-planar active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/24—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a grooved structure, e.g. V-grooved, crescent active layer in groove, VSIS laser
Landscapes
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
[発明の1」的]
(産業」二の利用分野)
本発明はp型半導体基板上に形成されたp−n逆接合を
含む半導体層にストライプ状の溝を有し、この溝の内部
に少なくとも活性層を含む半導体層を形成した溝+74
造半導体レーザ装置に関する。Detailed Description of the Invention [Invention 1] (Industry) 2) Field of Application The present invention provides a semiconductor layer including a p-n reverse junction formed on a p-type semiconductor substrate having stripe-shaped grooves. A groove +74 in which a semiconductor layer including at least an active layer is formed inside the groove.
The present invention relates to a manufactured semiconductor laser device.
(従来の技術)
半導体レーザ装置は光通信や情報処理用の光源として広
く用いられている。特にp−n逆接合を利用し、注入さ
れた電流を効率良く活性層に流す構造かよく採用されて
いる。中でもp−n逆接合を形成した後に活性層を形成
する溝構造の半導体レーザ装置は、活性層側面の熱損傷
か少ないため信頼性に優れる。(Prior Art) Semiconductor laser devices are widely used as light sources for optical communications and information processing. In particular, a structure that utilizes a pn reverse junction and allows the injected current to flow efficiently through the active layer is often adopted. Among them, a semiconductor laser device having a groove structure in which an active layer is formed after forming a pn reverse junction has excellent reliability because there is little thermal damage to the sides of the active layer.
この溝構造半導体レーザ装置は、例えば第3図に示すよ
うに、p型1nP基板1」−に約1μn]厚のn型In
P電流阻止層2、約]65μm厚のp型InP層3を積
層し、次に基板1に達するようにストライプ状のV溝4
を形成した後、p型InPクラット層5、InGaAs
P活性層6、n型InPクラッド層7を積層し、さらに
n側電極8p側電極9を付けることにより寄られる。こ
こで、活性層6の両端部は、n型1nP電流阻止層2と
p型1nP層3の間に形成されるp−n逆接合12とほ
ぼ一致するか、これより上に位11tするように形成す
る。For example, as shown in FIG. 3, this groove structure semiconductor laser device includes an n-type In board having a thickness of approximately 1 μm on a p-type 1 nP substrate 1''.
A P current blocking layer 2, a p-type InP layer 3 with a thickness of approximately 65 μm is laminated, and then a striped V groove 4 is formed so as to reach the substrate 1.
After forming p-type InP crat layer 5, InGaAs
This is accomplished by stacking a P active layer 6, an n-type InP cladding layer 7, and further attaching an n-side electrode 8 and a p-side electrode 9. Here, both ends of the active layer 6 are arranged so that they almost coincide with the p-n inverse junction 12 formed between the n-type 1nP current blocking layer 2 and the p-type 1nP layer 3, or are positioned 11t above this. to form.
この溝構造半導体レーザ装置は、p−n逆接合12によ
り、電極から注入された電流が活性層6に狭窄され、効
率良く発光に寄与するので低しきい値電流、高効率の動
作か可能である。In this groove structure semiconductor laser device, the current injected from the electrode is constricted in the active layer 6 by the p-n reverse junction 12, and contributes to light emission efficiently, so it is possible to operate with a low threshold current and high efficiency. be.
(発明が解決しようとする課題)
しかしこの溝構造半導体レーザ装置は、活性層6とp−
n逆接合12の位置関係によりしきい値電流が大きく変
化する。即ち、例えば第4図に示1ように、n型InP
電流阻止層2の厚さが2μm1p型InP層3の厚さが
0.5μmとなり、p−n逆接合12に対して活性層6
か下に位置すると、しきい値電流か上がってしまう。こ
れは第4図の場合、抵抗の低いn−1nPクラッド層7
とn型InP電流阻止層2が繋がってしまい逆接合12
による電流狭窄効果が小さくなるためである。(Problem to be Solved by the Invention) However, in this groove structure semiconductor laser device, the active layer 6 and the p-
The threshold current changes greatly depending on the positional relationship of the n-inverse junction 12. That is, for example, as shown in FIG. 4, n-type InP
The thickness of the current blocking layer 2 is 2 μm, the thickness of the p-type InP layer 3 is 0.5 μm, and the active layer 6 is
If it is located below the threshold current, the threshold current will rise. In the case of Fig. 4, this is the n-1nP cladding layer 7 with low resistance.
and n-type InP current blocking layer 2 are connected, resulting in a reverse junction 12
This is because the current confinement effect caused by
一般に各半導体層の成長には、液相結晶成長(L P
E)法か用いられるが、LPE法は結晶性に優れるもの
のMOCVD法や気相成長(VG)法に比べ層厚の制御
性か劣る。このため、LPE法で成長されるn型1nP
電流阻止層2、p型InP層3、p−クラッ1ぐ層5、
活性層6の層厚の制御性かあまり良くなく、活性層6の
位置の制御も困難である。Generally, each semiconductor layer is grown using liquid phase crystal growth (L P
Method E) is used, but although the LPE method has excellent crystallinity, it is inferior in controllability of layer thickness compared to the MOCVD method and the vapor phase growth (VG) method. For this reason, n-type 1nP grown by LPE method
current blocking layer 2, p-type InP layer 3, p-clamping layer 5,
Controllability of the layer thickness of the active layer 6 is not very good, and control of the position of the active layer 6 is also difficult.
本発明はこのような問題点を解決するもので、活性層6
とp−n逆接合12の位置関係にかかわらず、低しきい
値電流の溝構造半導体レーザ装置を得ることを目的とす
る。The present invention solves these problems, and the active layer 6
It is an object of the present invention to obtain a groove structure semiconductor laser device with a low threshold current regardless of the positional relationship between the pn inverse junction 12 and the pn inverse junction 12.
[発明の構成コ
(課題を解決するための手段)
本発明は、p型の半導体基板と、この上に形成されたn
型の半導体層と、このn型の半導体層を貫通し半導体基
板に達するストライプ状の溝と、n型の半導体層の上に
形成されたp型の半導体層と、ストライプ状の溝の表面
に形成されたp型の半導体層と、ストライプ状のli’
/iの内部に形成されたp型クラッド層、活性層、n型
クラット層とを含むことを特徴とする溝構造半導体レー
ザ装置である。[Configuration of the Invention (Means for Solving the Problems) The present invention provides a p-type semiconductor substrate and an n-type semiconductor substrate formed on the p-type semiconductor substrate.
A type semiconductor layer, a striped groove that penetrates the n-type semiconductor layer and reaches the semiconductor substrate, a p-type semiconductor layer formed on the n-type semiconductor layer, and a striped groove on the surface of the striped groove. The formed p-type semiconductor layer and the striped li'
This is a groove structure semiconductor laser device characterized by including a p-type cladding layer, an active layer, and an n-type cladding layer formed inside the groove structure.
(作 用)
本発明の溝構造半導体レーザ装置においては、ストライ
プ状の溝の表面に形成したp型の半導体層により、n型
クラッド層とn型1nP電流阻止層が分離される。この
ため、逆接合による電流狭窄効果は、活性層の位置にか
かわらず低減することがない。またこれにより、溝構造
半導体レーザ装置を容昌に得ることかできる。(Function) In the groove structure semiconductor laser device of the present invention, the n-type cladding layer and the n-type 1nP current blocking layer are separated by the p-type semiconductor layer formed on the surface of the striped groove. Therefore, the current confinement effect due to the reverse junction is not reduced regardless of the position of the active layer. Moreover, this makes it possible to easily obtain a groove structure semiconductor laser device.
(実施例)
以下、本発明の実施例を図面に基づいて詳細に説明する
。(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.
第1図は本発明の第1の実施例のGaInAsP /
I n P系の溝構造半導体レーザ装置の断面模式図で
ある。FIG. 1 shows GaInAsP/
FIG. 1 is a schematic cross-sectional view of an InP-based groove structure semiconductor laser device.
まず、LPE法、■G法、MOCVD法などによりp型
1nP基板1上にn型InP電流阻止層2, I)型
1nP層3を積層する。次いで、エッチングにより基板
1に達するようにストライプ状のV溝4を形成する。こ
の後、溝形状に対しても均一に成長するように、VG法
またはMOCVD法により薄い約0.3μm程度のp型
1. n P層10を全面に成長させる。続いて、LP
E法によりp型■nPクラッド層5,InGaAsP活
性層6,n型1nPクラッド層7を満4内に積層し、活
性層6を溝4中にたれ込ませる。この後、更に0型In
Pクラッド層7上にn側電極8を、またp型InP基板
1の裏面にp側電極9を付けることにより、本発明の溝
構造半導体レーザ装置が得られる。First, an n-type InP current blocking layer 2 and an I)-type 1nP layer 3 are laminated on a p-type 1nP substrate 1 by an LPE method, a G method, an MOCVD method, or the like. Next, striped V-grooves 4 are formed by etching to reach the substrate 1. Thereafter, in order to uniformly grow the groove shape, a thin p-type layer of approximately 0.3 μm is formed using the VG method or MOCVD method. An nP layer 10 is grown over the entire surface. Next, LP
A p-type ■nP cladding layer 5, an InGaAsP active layer 6, and an n-type 1nP cladding layer 7 are laminated in a full layer 4 by the E method, and the active layer 6 is allowed to sag into the groove 4. After this, further type 0 In
By attaching an n-side electrode 8 on the P cladding layer 7 and a p-side electrode 9 on the back surface of the p-type InP substrate 1, the groove structure semiconductor laser device of the present invention can be obtained.
このようにして得られた半導体レーザ装置は、薄いp型
InP層10によりn型1nP電流阻止層2とn型1n
Pクラッド層7か分離されているため、活性層6の位置
にかかわらず電流狭窄が効果的に行なわれる。即ち、本
発明によれば、活性層6の正確な位置の制御は必要なく
、容易にしきい値電流の低い溝構造半導体レーザ装置を
得ることができる。The semiconductor laser device thus obtained has an n-type 1nP current blocking layer 2 and an n-type 1nP current blocking layer 2 formed by a thin p-type InP layer 10.
Since the P cladding layer 7 is separated, current confinement is effectively performed regardless of the position of the active layer 6. That is, according to the present invention, there is no need to precisely control the position of the active layer 6, and a groove structure semiconductor laser device with a low threshold current can be easily obtained.
この実施例では、薄いp型1nP層10を結晶成長によ
り形成したか、拡散によって形成しても良い。In this embodiment, the thin p-type 1nP layer 10 is formed by crystal growth or may be formed by diffusion.
第2図は本発明の第2の実施例を示す断面模式図である
。この実施例はストライプ状のV溝4を形成したn型1
nP電流阻止層2上に、直接薄いp型1nP層10を形
成したものであり、薄いp型InP層10か第1の実施
例のp型1nP層3の役割を兼ねたものである。この実
施例は、第1の実施例よりも構造が簡単になる利点を有
する。FIG. 2 is a schematic cross-sectional view showing a second embodiment of the present invention. In this embodiment, an n-type 1 with a striped V-groove 4 is formed.
A thin p-type 1nP layer 10 is formed directly on the nP current blocking layer 2, and also serves as the thin p-type InP layer 10 or the p-type 1nP layer 3 of the first embodiment. This embodiment has the advantage of being simpler in structure than the first embodiment.
なお、n型半導体層は抵抗が低いため、本発明は基板が
p型の場合のみ脊効である。即ち、上記実施例と導電型
か逆であるn型1nP基板を用いた場合は、溝4の表面
に形成される抵抗の低い薄い口型1nP層10により、
溝4内部のn型1nPクラソド層5とn型InP層3が
繋がってしまい、第4図の場合と同様に電流狭窄が効果
的に行われなくなってしまう。Note that since the n-type semiconductor layer has low resistance, the present invention is effective only when the substrate is p-type. That is, when an n-type 1nP substrate having a conductivity type opposite to that of the above embodiment is used, the thin mouth-type 1nP layer 10 with low resistance formed on the surface of the groove 4 causes
The n-type 1nP clathodic layer 5 inside the groove 4 and the n-type InP layer 3 are connected, and current confinement cannot be effectively performed as in the case of FIG. 4.
し発明の効果]
本発明によれば低しきい値電流を容易に実現でき、量産
性に優れた溝}IM造半導体レーザ装置を得ることがで
きる。Effects of the Invention] According to the present invention, it is possible to easily realize a low threshold current and obtain a groove IM semiconductor laser device which is excellent in mass productivity.
第1図は本発明の第1の実施例を示す1折面図、第2図
は本発明の第2の実施例を示す断面図、第3図は従来例
の断面図、第4図は従来例の問題点を示す説明図である
。
1・・・p型InP基板、
2・・n型InP電流阻止層、
3・・・p型1nP層、
4・・・ストライプ状のV溝、
5・p型1nPクラッ1・層、
6・活性層、
7・・n型1nPクラッド層、
10・・薄いp型1nP層。
代理人 弁理士 則 近 憲 佑
同 竹 花 喜久男Fig. 1 is a cross-sectional view showing the first embodiment of the present invention, Fig. 2 is a sectional view showing the second embodiment of the invention, Fig. 3 is a sectional view of the conventional example, and Fig. 4 is a sectional view showing the second embodiment of the invention. FIG. 2 is an explanatory diagram showing problems in the conventional example. DESCRIPTION OF SYMBOLS 1...p-type InP substrate, 2...n-type InP current blocking layer, 3...p-type 1nP layer, 4...stripe-shaped V groove, 5.p-type 1nP crack 1 layer, 6. Active layer, 7... n-type 1nP cladding layer, 10... thin p-type 1nP layer. Agent Patent Attorney Nori Chika Yudo Kikuo Takehana
Claims (1)
層と、このn型の半導体層を貫通し前記半導体基板に達
するストライプ状の溝と、前記n型の半導体層の上に形
成されたp型の半導体層と、前記ストライプ状の溝の表
面に形成されたp型の半導体層と、前記ストライプ状の
溝の内部に形成されたp型クラッド層、活性層、n型ク
ラッド層とを含むことを特徴とする溝構造半導体レーザ
装置。a p-type semiconductor substrate, an n-type semiconductor layer formed thereon, a striped groove penetrating the n-type semiconductor layer and reaching the semiconductor substrate, and formed on the n-type semiconductor layer. a p-type semiconductor layer formed on the surface of the striped groove, a p-type cladding layer, an active layer, and an n-type cladding layer formed inside the striped groove. A groove structure semiconductor laser device comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5782489A JPH02238687A (en) | 1989-03-13 | 1989-03-13 | Groove structure semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5782489A JPH02238687A (en) | 1989-03-13 | 1989-03-13 | Groove structure semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02238687A true JPH02238687A (en) | 1990-09-20 |
Family
ID=13066673
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5782489A Pending JPH02238687A (en) | 1989-03-13 | 1989-03-13 | Groove structure semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02238687A (en) |
-
1989
- 1989-03-13 JP JP5782489A patent/JPH02238687A/en active Pending
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