JPS63287079A - Manufacture of semiconductor laser - Google Patents

Abstract

PURPOSE:To enable high output operation of the title laser, by forming an n-type InP current block layer on the under side of an outer waveguide path region of a distributed reflection type element of a buried BIG (Bundle Integrat ed Guide) structure. CONSTITUTION:An n-type InP current block layer 23 is formed on the part except a stripe 22 of a p-type InP substrate 21 forming a mesa type stripe 22 and thereon a p-type InP clad layer 24 is made to grow by turns so as to make the whole substrate flat. Next, a grading 25 is fixed to the side having the layer 23 underneath the surface of the layer 24. Subsequently, an active layer 27, a protective layer 28, an outer waveguide path layer 29 and a clad layer 30 are made to grow by turns. Later, an inverse mesa type stripe is formed by etching for being buried in a current constriction layer. Thereby, an inverse bias is produced on the pn junction surface of the layers 23 and 24 so that the current efficiently flows to the layer 27 solely without flowing to the layer 29. Accordingly, oscillation is made efficiently so as to obtain high output.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention is an embedded type BIG (Bundle-
The present invention relates to a method of manufacturing a distributed reflection type semiconductor laser (integrated-Quide) structure.

(Prior art) Conventionally, as a semiconductor laser capable of longitudinal single mode oscillation, distributed reflection N (DBR) is used.
A Bragg Reflector type) semiconductor laser has been proposed.

Figure 2 shows the conventional embedded BIG (Bundle
1 is a structural diagram of a distributed reflection type (hereinafter referred to as BH-BIG-DBR) semiconductor laser; Moreover, FIGS. 3(a) to 3(d) are manufacturing process diagrams of the semiconductor laser.

First, a p-InP cladding layer 2 is placed on a p-InP substrate l.
, G, InA8P active layer 3 and n-InP protective layer 4 are sequentially formed by liquid phase epitaxial growth (LPE) (FIG. 3(a)).

Next, the n-InP protective layer 4 and the GaInA, P active layer 3
Remove unnecessary parts of p-InP by etching and
The next surface of the cladding layer 2 is exposed, and a grating 5 (also called waveform or corrugation) with an appropriate pitch and depth is formed in this part using the usual 7-orography technique. (Figure 3(b)
)). The portion with the grating 5 serves as an external waveguide region 6.

In the second LPE, an n-GaInAaP external waveguide layer 7 and an n-1np cladding layer 8 are sequentially formed on the entire surface (FIG. 3(c)).

Next, due to the transverse mode side leg and current constriction, the photorin
The layers 2 to 4,7°8 are etched by chemical etching to form inverted mesa-shaped stripes 9'k (
011) direction (I!3 (d)). At that time,
@W of the active layer 3 has an appropriate width so as to achieve stable transverse mode oscillation. Here, it is 2 to 3 μm.

Next, in the third LPE, the inverted mesa stripe 9 was
- Filling with InP current confinement layer 10 and p-InP current confinement layer 1'1 (21st).

Next, an insulating film 12 such as 5to2 is formed on different surfaces of the n-(np cladding layer 8 and the p-InPm flow constriction layer 11), and the insulating film 12 has an upper part of the active region 13 where the active layer 3 is located. Open the window 14 for the electrode (FIG. 2).

After that, although not shown in the figure, n is formed at the window 14.
- A negative electrode in contact with the InP cladding layer 8 is formed on the insulating film 12, and a positive electrode is further formed on the back surface of the substrate 1 to obtain an element.

Apply bias. Then, as mentioned above, although the substrate 1 side has an electrode on the entire surface, on the n-InP cladding layer 8 side, the electrode is in contact only on the active region 13, so the current flows to the active region 13 rich in the active layer 3. There is a concentrated flow n, but a narrow flow n does not exist in the outer waveguide region 6. In addition, the current confinement layer 10.
Since the portion 11 is reverse biased, no current flows. Therefore, the light generated in the active layer 3 is guided to the external waveguide region 6, Bragg-reflected by the grating 5, oscillates as a laser in a single longitudinal mode, and is extracted in the direction of arrow A in FIG.

At this time, in the external waveguide region 6, the smaller the light absorption loss, the better the oscillation efficiency, and it is better not to allow current to flow.

(Problems to be Solved by the Invention) In the above-described conventional manufacturing method, by limiting the contact of the electrode on the n-Inp cladding layer 8 side only to the active region 13, the outer waveguide region 6 is coated with current gold. I try not to.

However, since the current spreads in the n-Inp clad JJ 8, a small current inevitably flows into the external waveguide region 6, resulting in large losses and low oscillation efficiency, making it difficult to obtain a low threshold current and high output. There was a problem.

This invention eliminates the problem of low oscillation efficiency due to large optical loss in the external waveguide region due to the current flowing in the external waveguide region, and enables highly efficient oscillation, low threshold current, and high output operation. An object of the present invention is to provide a method for manufacturing a BH-BIG-DBR semiconductor laser.

(Means for Solving the Problems) The present invention introduces a step of forming a current blocking layer under the external waveguide region where the grating is located in a method of manufacturing a BH-BIG-DBR semiconductor laser. . Specifically, after forming a mesa stripe on a part of the thorny surface of a pill InP substrate, an n-InP current blocking layer and a zn-doped p-InP cladding are formed on the entire surface of the substrate having the mesa stripe. The layers are sequentially formed so that the thorny surfaces are flat, and the n-inp current blocking layer is formed by non-growth of n-InP on the top of the mesa-shaped stabilized layer or by solid-phase diffusion of zn from the p-InP cladding layer. (by inversion to p-type), so that it is formed in a region other than the knob-shaped stripe portion. Thereafter, the surface of the p-InP cladding layer is removed from the surface of the p-InP cladding layer. The n-Jnp below corresponds to the side of the W stripe end.
A grating is attached to the part that has the current blocking layer and will become the external waveguide region.

(Function) In the device manufactured using the above process, n-InPtn is placed below the external waveguide region where the grating is located.
Because of the Pt block layer, current does not flow to the external waveguide region, but efficiently flows only to the active layer portion.

(Example) Examples of the present invention will be described below with reference to the drawings. 1st
Figures (fL) to Φ) are manufacturing process diagrams showing examples of the present invention. As shown in FIG. 1(a), first, p
- Long mesa temperature stripes 22 in the (011) direction are formed on a part of the surface of the InP substrate 21 using ordinary photolithography and etching techniques. Here, the mesa shape of the mesa stripe 22 changes depending on the etchant (etching liquid), but for example, if a mixed solution of hydrochloric acid and phosphoric acid is used,
A forward mesa shape as shown is obtained. In addition, the height h of the mesa can be set to a sufficient thickness for the current blocking layer to be grown next.
1 to make the entire surface flat with the next cladding layer.
μm to 1.54m. Although the width W1 can be the same as the element width, it is set to about 1 to 5 .mu.m in order to simplify manufacturing and to avoid growth on the top of the regular stripe 22 in order to form the next current blocking layer. moreover,
The length L is the same as the length of the active region, and here it is 150μ.
m to 200 μm.

In addition, in FIG. 1(a), arrow A indicates the emission direction of the laser beam.

Next, the p-InP with type stripes 22 is
The 11th W (b) is applied to the entire surface of the substrate 21.
) As shown in B-Bi cross-sectional view of ), n
-inp Current blocking layer 23%Zfl Dawg p
- The imp cladding layer 24 is sequentially grown. In this ζ,
For normal LPE, n-InP'mfi block layer 2
If the thickness of 3 is about 1 #m and the mesa dimensions mentioned above,
The n-1np current blocking layer 23 does not grow on the top of the metm stripe 22 at all, or it can be made very thin ((about 0-1am). In particular, when the mesa width W1 is set to 4 #m or less, the n-Inp The current blocking layer 23 has good reproducibility.
It is possible to prevent the growth on the upper part of the Metm stripe 22. In an embodiment of the present invention, one method is to use the above method to
It is formed in a portion other than the mesa-shaped stripe 22 portion. In that case, the height h of the mesa-shaped stripe 22 and the thickness of the n-InP current blocking layer 23 are taken into consideration, n, so that the entire surface of the four substrates on the next two p-InP cladding layers is flat. ．． ! Mm, in the case of 1 μm, 1 ~
Make the thickness 1.5 μm.

However, in FIG. 1(b), the n-inp current blocking layer 23 is grown to a height higher than the height h of the t-meb temperature stripe 22, and the n-inp current also flows on the upper part of the mesa stripe 22.
The case where the lock layer 23 is growing is shown.

In this case, when the Keyaki carrier concentration of the n-InPIt flow blocking layer 23 is lower than the carrier concentration on the second p-InP cladding layer and the length is increased on the second p-InP cladding layer, from the second time onwards. During the growth process, n of 4 of the two p-InP cladding layers diffuses into the n-InPt flow blocking layer 23 in a solid phase, and the upper layer (hatched area) is inverted from n-type to p-type. , n-7np current blocking layer 23
is made to exist in a portion other than the mesa-shaped stripe 22 portion.

Next, among the upper four surfaces of the two p -InP cladding layers, the part where the mesa stripe 22 is located and the part that will become the external waveguide region in the (011) direction (underneath is the n -InP current blocking layer) 23 exists), a 25ft grating is attached as shown in Fig. 1(c).

The method of forming this grating 25 is the same as the conventional one.
, 7 Orography, etc. to obtain the proper pitch and depth.

Next, on the surface of the grating 25, as shown in FIG.
lIIIi@1 Figure (a) OA-A line direction 11eO cutli
As shown in the cross-sectional view taken along the line B--B in FIG. Then, using the selective growth mask 26 as a mask,
As shown in FIG. 1(d), a GaInABP active layer 27 and an n-InP protective layer 28 are sequentially grown on the surface of the p-InP cladding layer 24 where the mask 26 is not present.

Next, after removing the selective growth mask 26, the n-InP
A third L is applied to the entire surface of the protective layer 28 and grating 25.
As shown in Figures 1(e) and 1(f) (Figure 1(f) is a sectional view taken along line CC in Figure 1(e)), n-Ga
Zero-order growth is performed on the InAl5P external waveguide layer 29 and the three n-inp cladding layers.

Thereafter, in order to obtain a buried structure, an etching mask is formed on the surface of the n-1np cladding layer 30 in a stripe shape in the (011) direction, using the upper part of the mesa stripe 22 as a part. Then, using the striped etching mask as a mask, the unnecessary portions of the laminated portion from the n-InP cladding layer 30 to the mesa-shaped stripe 22 are removed by etching (particularly, the I !Strive 3 the reverse mesa as shown in Figure 1 (2).
form 1.

Finally, after removing the etching mask, a first layer is etched on both sides of the reverse mesh stripe 31 in the fourth LPE.
As shown in FIG.

Although not shown in the figure, a positive electrode is formed on the back surface of the p-InP substrate 21, and a negative electrode is formed on the n-InP cladding layer 30.

In the device manufactured in this way, when a normal bias is applied, a current flows in a certain part of the active layer 27.
Light is generated. However, in the portion of the grating 25 (external waveguide region), there is an n-InP current blocking layer 23 on the lower side, and the n-1np current blocking layer 23 and the p
- pn junction surface with InP cladding layer 24 (Fig. 1 (f)
) outside the X-marked area), the rounding becomes reverse bias,
do not have. Therefore, when the light generated in the active layer 27 is guided to the external waveguide layer 29 above the grating 25 and undergoes Bragg reflection at the grating 25, loss is reduced.

(Effects of the Invention) As explained in detail above, the manufacturing method of the present invention
For example, there is a current under the external waveguide region with the grating! Since the lock layer is formed, in the manufactured device, current efficiently flows only in the active layer portion and does not flow in the external waveguide region. Therefore, the loss of light in the external waveguide region is reduced by 74%, oscillation is efficient, and low threshold current and high output operation are possible, making it possible to obtain an H-BIG-DBR semiconductor laser device.

[Brief explanation of the drawing]

FIG. 1 is a manufacturing process diagram showing an embodiment of the semiconductor laser manufacturing method of the present invention, and FIG. 2 is a conventional BH-BIG-DBR.
A structural diagram of a semiconductor laser, FIG. 3 is a manufacturing process diagram of the above-mentioned conventional semiconductor laser. 21...p-InP substrate, 22...Methi-type stripe, 23-n-InPt flow layer, 24.p
-InP cladding layer, 25... grating, 2
7...GaInAsP active layer, 28 ・n-InP
Protective layer, 29...n-GBIHABP external waveguide layer, 3Q/n-InP cladding layer, 31...inverted mesa stripe, 32...n-InPtfi constriction layer, 33-p-InP NK constriction layer. Part 1 Figure 2 Figure 312Q Figure 3

Claims (1)

[Claims] Embedded BIG (Bundle-Integrate)
d-Guide) A method for manufacturing a distributed reflection type semiconductor laser, which includes (a) forming a mesa stripe on a part of the surface of a p-type InP substrate; (b) forming a mesa stripe on the substrate having the mesa stripe; N-InP current blocking layer on the entire surface, Zn-doped p-InP
The cladding layers are sequentially formed so that the surface is flat, and the n-
The InP current blocking layer is formed by non-growth on the top of n-InP mesa stripes or Z from the p-InP cladding layer.
(c) forming the mesa stripe end on the surface of the p-InP cladding layer by inverting the upper layer to p type by solid-phase diffusion of n; (d) forming a grating on the surface of the p-InP cladding layer excluding the grating portion; (e) After that, after sequentially growing an external waveguide layer and a cladding layer on the entire surface, the laminated portion from the cladding layer to the mesa stripe portion is formed into an inverted mesa shape. A method for manufacturing a semiconductor laser, comprising the steps of forming a stripe and further burying the inverted mesa stripe with a current confinement layer.