JPS596588A - Semiconductor laser - Google Patents

Semiconductor laser

Info

Publication number
JPS596588A
JPS596588A JP11652182A JP11652182A JPS596588A JP S596588 A JPS596588 A JP S596588A JP 11652182 A JP11652182 A JP 11652182A JP 11652182 A JP11652182 A JP 11652182A JP S596588 A JPS596588 A JP S596588A
Authority
JP
Japan
Prior art keywords
layer
inp
mesa stripe
semiconductor
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11652182A
Other languages
Japanese (ja)
Inventor
Mitsuhiro Kitamura
北村 光弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11652182A priority Critical patent/JPS596588A/en
Publication of JPS596588A publication Critical patent/JPS596588A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • H01S5/2275Buried mesa structure ; Striped active layer mesa created by etching
    • H01S5/2277Buried mesa structure ; Striped active layer mesa created by etching double channel planar buried heterostructure [DCPBH] laser

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  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To offer a BH-LD of high manufacturing yield with less dispersion of characteristics by a method wherein the height of a mesa stripe is constituted higher than that of multilayer films on both sides of grooves by forming a fixed semiconductor layer only on the upper side of the mesa stripe. CONSTITUTION:An N-InP buffer layer 2, a non doped active layer 3, a melt back prevention layer 4 as a second semiconductor layer and a P-InP clad layer 5 as a first semiconductor layer are successively laminated on an N-InP substrate 1. The mesa stripe 9 is first formed at a part wherein the P-InP clad layer 5 which is previously covered with an etching mask 6 remains, and the etching grooves 7 and 8 are so formed that the P-InP clad layer 5 does not remain on both side distant from the mesa stripe. In burying growth, both of a P-InP current block layer 10 and an N-InP current block layer 11 are so laminted as not to cover the upper surface of the mesa stripe 9, and further a P-InP buried layer 12 and an electrode layer 13 are laminated over the entire surface. Next, the BH-LD is obtained by forming a P type ohmic electrode 14 and an N type ohmic electrode 15.

Description

【発明の詳細な説明】 本発明は活性層の周囲をエネルギーギヤ、プが大きく、
屈折率が小さな半導体材料で埋め込んだ埋め込みへチル
構造の半導体レーザ、特に製造歩留りが改善された半導
体レーザに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a structure in which the active layer is surrounded by a large energy gear.
The present invention relates to a semiconductor laser having a buried-chill structure filled with a semiconductor material having a small refractive index, and particularly to a semiconductor laser with improved manufacturing yield.

一般に、埋め込みへテロ構造半導体レーザ(以下BH−
LDという)は、低い発振しき〜・値電流安定化された
発振横モード、高温動作可能などの優れた特性を有して
いるため、光7アイパ通信用光源とし【注目を集め【い
る。本願の発明者らは特願昭56−166666により
、2本のほぼ平行な溝に挾まれて形成され発光再結合す
る活性層を含むメサストライプの周囲で確実に電流ブロ
ック層が形成できるBH−LDを出願した。このBH−
LDは、温度特性に優れ、種々の基板処理過程でのダメ
ージを受けることが少なく製造歩留りの向上したもので
ある。しかし、この構造BH−LDは、メサストライプ
を挾んでいる溝の両脇の部分でn−InP電流ブ四ツク
層が滑らかに成長せずに途切れてしまい、特性のバラツ
キを招くという欠点があった。またこの欠点を防ぐため
にp−InP電流電流クロッ2層−InP電流電流クロ
ッ2層に厚く成長させようとすると、n−InP電流プ
ロック層が発光再結合する活性層を含むメサストライプ
の上部を覆ってしまうという欠点があった。
Generally, a buried heterostructure semiconductor laser (hereinafter referred to as BH-
The LD (LD) has attracted attention as a light source for optical 7-IPA communication because it has excellent characteristics such as a low oscillation threshold, a stabilized oscillation transverse mode, and the ability to operate at high temperatures. The inventors of the present application have disclosed in Japanese Patent Application No. 56-166666 that a BH- I applied for LD. This BH-
LDs have excellent temperature characteristics, are less susceptible to damage during various substrate processing processes, and have improved manufacturing yields. However, this BH-LD structure has the disadvantage that the n-InP current block layer does not grow smoothly and is interrupted on both sides of the trench between the mesa stripes, leading to variations in characteristics. Ta. In addition, in order to prevent this drawback, if you try to grow a thick layer of p-InP current block two layers and two InP current block layers, the n-InP current block layer will cover the top of the mesa stripe containing the active layer that undergoes luminescent recombination. There was a drawback that

本発明の目的は、これらの欠点を除去し、特性のバラツ
キが少なく、製造歩留りの高いBH−LDを提供するこ
とにある。
An object of the present invention is to eliminate these drawbacks, provide a BH-LD with less variation in characteristics, and a high manufacturing yield.

本発明の構成は、半導体基板上に活性層を含む半導体多
層膜を積層させた多層膜構造半導体ウェファに、前記活
性層よりも深く形成された2本の平行な溝によって挾ま
れたメサストライプを形成しこのメサストライプを埋め
込み成長してなる埋め込みへテロ構造の半導体レーザに
おいて、前記メサストライプの前記活性層上側にのみ所
定半導体層を形成して前記メサストライプの高さを前記
溝の画側の多層膜よりも高く構成したことを特徴として
いる。
The structure of the present invention is to provide a multilayer structure semiconductor wafer in which a semiconductor multilayer film including an active layer is laminated on a semiconductor substrate, and a mesa stripe sandwiched between two parallel grooves formed deeper than the active layer. In a buried heterostructure semiconductor laser formed by forming a mesa stripe and growing the mesa stripe, a predetermined semiconductor layer is formed only on the upper side of the active layer of the mesa stripe, and the height of the mesa stripe is adjusted to the image side of the groove. It is characterized by being constructed higher than a multilayer film.

以下図面を参照して本発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.

第1図(alt (b+、 (clは本発明の第1の実
施例の製造工程順に示した断面図である。まず、第1図
(a)に示した様に、(100) n−InP基板1上
に、n−InPバッファ層2、発光波長1.55μmに
相10活性N3、第2の半導体層である発光波長1、3
 ti mに相当するp−Ino、yz  Gao、z
s Aso、alpo、s*メルトバック防止層4、第
1の半導体層であるp−InPクラ、ド層5を順次積層
させる。
FIG. 1 (alt (b+, (cl) is a cross-sectional view shown in the order of manufacturing steps of the first embodiment of the present invention. First, as shown in FIG. 1(a), (100) n-InP On the substrate 1, an n-InP buffer layer 2, a phase 10 active N3 with an emission wavelength of 1.55 μm, and a second semiconductor layer with emission wavelengths 1 and 3.
p-Ino, yz Gao, z corresponding to ti m
The sAso, alpo, s* meltback prevention layers 4 and the p-InP layer 5, which is the first semiconductor layer, are laminated in this order.

ここでIno、se  Qaa4t  Asaso  
P(LIO活性層3は厚さ0.15μm、p−111o
、y2Qaα211 Aso、alpo、ssメルトバ
ック防止層4は厚さ 0.3μm%p−InPクラッド
層5は厚さ1μm程度とする。 このように積層された
多層膜構造半導体ウェファに〈011〉方向に平行に幅
15μm程度のエツチングマスク6を形成し、このエツ
チングマスク6で覆った部分以外のp−InPクラッド
層5を選択エツチングにより除去する。この選択エツチ
ングとし℃はInPをエツチングできるHCJ系のエラ
チン少液を用いればよい。例えば、 4H(J+H,0
の混合エツチング液を用いて、3C,19間エツチング
することによりエツチングマスク6のない個所のp−I
nPクラッド層5を工、チオフできる。
Here Ino, se Qaa4t Asaso
P (LIO active layer 3 has a thickness of 0.15 μm, p-111o
, y2Qaα211 Aso, alpo, ss The meltback prevention layer 4 has a thickness of 0.3 μm% The p-InP cladding layer 5 has a thickness of about 1 μm. An etching mask 6 having a width of about 15 μm is formed in parallel to the <011> direction on the multilayer structure semiconductor wafer laminated in this manner, and the p-InP cladding layer 5 other than the portion covered by this etching mask 6 is selectively etched. Remove. For this selective etching, a small solution of HCJ-based elatin, which can etch InP, may be used. For example, 4H(J+H,0
By etching between 3C and 19 using a mixed etching solution of
The nP cladding layer 5 can be processed and removed.

この際、p−Inayz  Gaazs  Aso、a
t  Po、seメルトバ、り防止層4は全くエツチン
グされず、この2つの半導体層の界面でエツチングを停
止させることができる。
At this time, p-Inayz Gaazs Aso, a
The anti-etching layer 4 is not etched at all, and the etching can be stopped at the interface between these two semiconductor layers.

次に、第1図伽)に示した様に、通常のフヤトレジスト
の技術を用いてエツチング溝およびメサストライプの形
成を行なう。まず、幅2μmのメサストライプ9は、先
にエツチングマスク6で覆ったp−InPクラッド層5
の残っている部分に形成され、またエツチング溝7,8
は幅10μm程度とし、メサストライプ9かも離れた両
側にはp−InPクラ、ド層5が残らない様にする。こ
れは活性層3よりも深くエツチングする必要があるが、
Brメタノール系のエツチング液を用いて容易に再現性
よくエツチングできる。例えば50ccのメチルアルコ
ールにBrO,1ccを混合した混合エツチング液を用
(・て、3C3分間でエツチングできる。
Next, as shown in FIG. 1, etching grooves and mesa stripes are formed using a conventional photoresist technique. First, the mesa stripe 9 with a width of 2 μm is formed by forming the p-InP cladding layer 5 which was previously covered with the etching mask 6.
are formed in the remaining portions of the etching grooves 7 and 8.
The width of the mesa stripe 9 is approximately 10 .mu.m, and the p-InP layer 5 is not left on either side of the mesa stripe 9. This needs to be etched deeper than active layer 3, but
Etching can be easily performed with good reproducibility using a Br methanol-based etching solution. For example, etching can be carried out in 3 minutes at 3C using a mixed etching solution consisting of 50 cc of methyl alcohol and 1 cc of BrO.

最後に、第1図(C)に示した様に、埋め込み成長電極
形成を行う。埋め込み成長においてはp−InP電流プ
ロ、りHA 10.  n−InP電流電流シロ22層
11いずれもメサストライプ9の上面を徨わない様にし
積層させ、さらにp−InP  埋め込み層12発光波
長1.3μmに相当するp−Ino、t 2 Qao、
zs−Asae !Po、m * 91極r@ 13 
ヲ全面ニ  わター)”Cff層させる。この様にp−
InP電流ブロック層10およびn−InP電流電流シ
ロ22層11サストライプ9の上面のみを除いて積層さ
せる(これは特願昭56−166666に、詳述してい
る)。Inメルト中にInPソースが浮かんでいる2相
溶液法を用いることにより容易にかつ再現性よくできる
。次に、p形オーミック性電極14およびn形オーミッ
ク性電極15を形成してBH−LDを得ることが出来る
Finally, as shown in FIG. 1(C), a buried growth electrode is formed. In buried growth, p-InP current pro, reHA 10. The n-InP current shield layer 11 is laminated so as not to cross the upper surface of the mesa stripe 9, and the p-InP buried layer 12 has p-Ino, t 2 Qao, which corresponds to the emission wavelength of 1.3 μm,
zs-Asae! Po, m * 91 pole r @ 13
Make a p-Cff layer on the entire surface.
The InP current blocking layer 10 and the n-InP current shielding layer 22 layer 11 are laminated except for only the upper surface of the stripe 9 (this is detailed in Japanese Patent Application No. 166666/1983). This can be done easily and with good reproducibility by using a two-phase solution method in which an InP source is floating in an In melt. Next, a BH-LD can be obtained by forming a p-type ohmic electrode 14 and an n-type ohmic electrode 15.

この第1の実施例においては、メサストライプ9のみが
厚さ1μmのp−InPクラッド層5を含んでおり、エ
ツチング溝7,8の両側の部分に比べてメサストライプ
9が1μmだけ高く形成されている。このメサストライ
プ9がその周囲よりも1μmだけ高く形成されるように
、第3の半導体層のp−Ino、yzGao、zsAs
cLatPo、ss  メルトバツク防止層4が形成さ
れており、そのため選択エツチングが大きな役割を果し
ている。このために埋め込み成長においては、2つの電
流プ四、り層がメサストライプ9の上面を覆わず、しか
もエツチング溝7.ぎの両側で途切れずなめらかに成長
させることができる。すなわち、選択エツチングを用い
てメサストライプ9のみをその周囲よりもlltmだけ
高く形成させることにより、埋め込み成長時の電流ブロ
ック層形成におけるトレランスが大幅に向上し、BH−
LDの特性の再現性を良くシ、その製造歩留りを大幅に
向上できる。
In this first embodiment, only the mesa stripe 9 includes the p-InP cladding layer 5 with a thickness of 1 μm, and the mesa stripe 9 is formed 1 μm higher than the portions on both sides of the etching grooves 7 and 8. ing. p-Ino, yzGao, zsAs of the third semiconductor layer is formed so that this mesa stripe 9 is formed 1 μm higher than its surroundings.
cLatPo,ss A meltback prevention layer 4 is formed, and therefore selective etching plays a major role. For this reason, in the buried growth, the two current conductor layers do not cover the upper surface of the mesa stripe 9, and moreover, the etched groove 7. It can be grown smoothly without interruption on both sides of the tree. That is, by forming only the mesa stripe 9 to be higher than its surroundings by lltm using selective etching, the tolerance in forming the current block layer during buried growth is greatly improved, and the BH-
The reproducibility of the LD characteristics can be improved and the manufacturing yield can be greatly improved.

第2図(al、 (blは本発明の第2の実施例である
分布帰還型埋め込みへテロレーザ(DFB−BHLD)
の共振軸に垂直な方向での断面図およびその共振軸に平
行な方向の断面図である。このDFB−BHLDを得る
Kは、まず(Zoo)n−InP 基板1に回折格子2
2を形成する。この回折格子22は、DFBモードの共
振軸方向が(011)と平行にくり返されるものとし、
活性層中の発振波長のイの整数倍のピッチであればよい
。例えば、He −Cdガスレーザのレーザ干渉法と通
常の化学エツチング法とを用いて、ピッチ 0.40μ
m、深さ0.12μmの回折格子を作成できる。この様
な回折格子22を形成したn−InP基板1上に、発光
波長1.05μmに相当するH−IHo、s oGao
、1IA80.24P0.76光ガイド層23を厚さ0
.3μm1発光波長1゜3μmに相当するノンドープI
no、yzGao、zsAs aatpast活性層2
4を厚さ0.1μm、第2の半導体層であるp−InP
クラッド層25を厚さ0.8μm発光波長1.2μmに
相当する第1の半導体層p−InaysQaci、zz
Aso、n5Po、sz層26を厚さ0.8μmで順次
積層させる。このようにして得た多層膜構造半導体ウェ
ファに、第1の実施例と同様にメサストライプとなる部
分の周辺の@15μmのストライプのみを残してp−I
no、ys  C3Bo2zAso、aspo、sz層
26をエッチオフする。こオLも選択エツチングにより
p−InP クラット°層25の上面でエツチングを止
めることができる。例えば硫酸系の混合エラチャン) 
5H,80,+H10,+H1Oを用いて4001分間
のエツチングを行う。
Figure 2 (al, (bl) is a distributed feedback buried heterolaser (DFB-BHLD) which is the second embodiment of the present invention.
FIG. 2 is a cross-sectional view in a direction perpendicular to the resonance axis of the semiconductor device and a cross-sectional view in a direction parallel to the resonance axis of the semiconductor device. K to obtain this DFB-BHLD is first a (Zoo)n-InP substrate 1 and a diffraction grating 2.
form 2. In this diffraction grating 22, the resonance axis direction of the DFB mode is repeated parallel to (011),
The pitch may be an integral multiple of A of the oscillation wavelength in the active layer. For example, using the laser interferometry of He-Cd gas laser and the ordinary chemical etching method, the pitch is 0.40μ.
m, a diffraction grating with a depth of 0.12 μm can be created. On the n-InP substrate 1 on which such a diffraction grating 22 is formed, H-IHo and soGao corresponding to an emission wavelength of 1.05 μm are placed.
, 1IA80.24P0.76 light guide layer 23 with thickness 0
.. Non-doped I corresponding to 3 μm 1 emission wavelength 1°3 μm
no, yzGao, zsAs aatpast active layer 2
4 has a thickness of 0.1 μm, and p-InP is the second semiconductor layer.
The cladding layer 25 has a thickness of 0.8 μm and a first semiconductor layer corresponding to an emission wavelength of 1.2 μm.
Aso, n5Po, and sz layers 26 are sequentially laminated to a thickness of 0.8 μm. In the multilayer structure semiconductor wafer obtained in this way, p-I was applied, leaving only the stripes of @15 μm around the part that would become the mesa stripe, as in the first example.
no, ys C3Bo2zAso, aspo, sz layer 26 is etched off. Etching can also be stopped on the upper surface of the p-InP crat layer 25 by selective etching. For example, sulfuric acid-based mixed Elachan)
Etching is performed for 4001 minutes using 5H, 80, +H10, +H1O.

次に同様に<011>方向に平行な2本のエツチング溝
7,8およびメサストライプ9を形成する。
Next, two etched grooves 7 and 8 and a mesa stripe 9 parallel to the <011> direction are formed in the same manner.

この際第1の実施例と同様にメサストライプ9のみがp
−In(L78Gao、z 2AS0.48PO,lI
 2層26を含んでいる様にエツチングを行う。最後に
埋め込み成長を行ないp−InP電流電流クロッ2層1
0tnnP電流電流クロッ2層11ずれもメサストライ
プ9上面のみを除いて、さらにp−InP埋め込み層1
21発光波長1.3μmに相当する p−Ino、yz
Qao、zsAso、aIPo、as 電極層13を全
面にわたって順次積層させる。
At this time, as in the first embodiment, only the mesa stripe 9 is p
-In(L78Gao, z 2AS0.48PO, lI
Etching is performed to include two layers 26. Finally, buried growth is performed and p-InP current current clock 2 layer 1
0tnnP current current clock 2 layer 11 is also shifted except for the top surface of mesa stripe 9, and further p-InP buried layer 1
21 corresponding to emission wavelength 1.3 μm p-Ino, yz
Qao, zsAso, aIPo, and as electrode layers 13 are sequentially laminated over the entire surface.

この第2の実施例においても、メサストライプ 9のみ
が工、チング溝7,8の両脇の部分に比べてp−Ino
、ysGao、z2AS0.48PO,!12の厚み分
(0,8μm)だけ高く形成されているので電流ブロッ
ク層の形成が容易になり、製造歩留りが大幅に改善され
る。さらに、ファプリ・ベロー共振モードが現われない
様にするために少なくとも一方の端面からの反射を防ぐ
ために、一部非注入領域を形成するか、端面の反射を着
るしく低下させている。この実施例では9図示の様に片
方の端面27を傾斜させてエツチングすることにより、
片端面からのレーザ光の反射を無くしている。
In this second embodiment as well, only the mesa stripe 9 has a p-Ino material, compared to the parts on both sides of the grooves 7 and 8.
,ysGao,z2AS0.48PO,! Since the current blocking layer is formed as high as 12 mm (0.8 μm), it is easy to form the current blocking layer, and the manufacturing yield is greatly improved. Furthermore, in order to prevent the appearance of the Fabry-Bello resonance mode, a non-injected region is partially formed or the reflection at the end face is appropriately reduced in order to prevent reflection from at least one end face. In this embodiment, as shown in Figure 9, one end surface 27 is etched with an incline.
Eliminates reflection of laser light from one end face.

このように作られたDFB−BHLDは、室温における
CW発振しきい値電流40mA、微分量子効率40%、
DFBモードの波長温度依存性が、0.8X/d e 
gと小さく、再現性よく得られる。この第2の実施例に
おいても、メサストライプ9のみが第1の半導体層であ
る厚さ0.8μmのp−Ina、ysGao、zzAs
o、4sPo、s2F@26を有しているので、埋め込
み成長のトレランスが大きくなり、2つの電流フ頴ツク
層がメサストライプ9の上面を覆うことなり、シかもエ
ツチング溝7.8の両脇で途切れるように成長させるこ
とが容易となり、製造の歩留りが大幅に向上する。
The DFB-BHLD made in this way has a CW oscillation threshold current of 40 mA at room temperature, a differential quantum efficiency of 40%,
The wavelength temperature dependence of DFB mode is 0.8X/d e
g, and can be obtained with good reproducibility. In this second embodiment as well, only the mesa stripe 9 is made of p-Ina, ysGao, zzAs with a thickness of 0.8 μm as the first semiconductor layer.
o, 4sPo, s2F@26, the tolerance for buried growth is increased, and the two current hook layers cover the upper surface of the mesa stripe 9, which may cause the etching grooves 7. This makes it easy to grow the crystals in a discontinuous manner, greatly improving manufacturing yields.

なお1本実施例は、InP基板と工旧−xGaxAsy
P1−y活性層とによる波長1μm帯の光半導体素子を
示したが、用いる半導体材料はこれに限定するものでは
ない、また、第2の実施例において、ファブリペローモ
ードを除くために1片方の端面を斜めにエツチングした
が、n型電極層に注入領域のみp型不純物の拡散を行な
う方法や、片方の端面付近のみエツチング溝の幅を狭く
して、この部分でのみ電流ブロック層がメサストライプ
をおおうように成長させて非注入領域を形成する等の方
法も利用できる。また、実施例にお(・てはp−InP
、n−InPの2つの電流ブロック層を積層させたが、
メサエッチング後の半導体ウェファにあらかじめ、メサ
ストライプ以外に不純物拡散を行なりて一層だけの電流
ブロック層を積層させてもよ(・。さらに、実施例にお
(・ては、BH−LD、DFB−。
Note that this embodiment uses an InP substrate and an old-xGaxAsy
Although an optical semiconductor device with a wavelength band of 1 μm using a P1-y active layer has been shown, the semiconductor material used is not limited to this. Although the end face was etched diagonally, there are methods in which the p-type impurity is diffused only in the injection region of the n-type electrode layer, or the width of the etching groove is narrowed only near one end face, so that the current blocking layer forms a mesa stripe only in this part. It is also possible to use methods such as growing the material so as to cover it to form a non-implanted region. In addition, in Examples (・te is p-InP
, two current blocking layers of n-InP were laminated, but
In addition to the mesa stripe, impurity diffusion may be performed in advance on the semiconductor wafer after mesa etching to laminate a single current blocking layer. −.

BHLDの2種類の半導体レーザな示したが、この様な
りH−LDを基本素子とした光双安定素子等の光轡能素
子、あるいはBH−LDとPD、FET等をモノリシッ
クに組み合わせた複合型光半導体素子にも当然速用可能
である。
We have shown two types of BHLD semiconductor lasers, but these include optical performance devices such as optical bistable devices that use H-LD as a basic device, or composite types that monolithically combine BH-LDs, PDs, FETs, etc. Of course, it can also be quickly applied to optical semiconductor devices.

本発明の特徴は、埋め込み成長前の半導体ウェファにお
いて、メサストライプのみが第1の半導体層を有してお
り、エツチング溝の両わきの部分と比べて、その第1の
半導体層の厚さ分だけ、メサストライプが高く形成され
ているために、埋め込み成長時に、電流ブロック層がメ
サ上面を覆うことなく、シかも同時に2つのエツチング
溝の両脇の部分で途切れて成長するどい仕とがなくなり
、電流ブ四ツク層成長のトレランスが大幅に向上し、B
H−LDにおける特性の再現性、製造歩留りが大きく改
善される。
A feature of the present invention is that in the semiconductor wafer before buried growth, only the mesa stripe has the first semiconductor layer, and the thickness of the first semiconductor layer is larger than the thickness of the mesa stripe on both sides of the etching groove. However, because the mesa stripes are formed high, during buried growth, the current blocking layer does not cover the top surface of the mesa, and at the same time, there is no possibility that the current blocking layer will grow at both sides of the two etched grooves. The tolerance of current block layer growth is greatly improved, and B
The reproducibility of characteristics and manufacturing yield in H-LD are greatly improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)、 (b)、 (clは本発明の第1の実
施例の製造工程順に示した断面図、第2図(al、 (
blは本発明の第2の実施例の横断面図およびそのメサ
ストライプ内での共振軸方向の断面図である。図におい
て 1・・・・・・n−■nP基板、2・・・・・・n−I
nPバッファ層、3−−・・−・Ino、5sGaα4
1ASO,1lopolo活性層、4 ・−・・・・p
−In0.y zQao、z 5Aso、a tPo、
s *メルト、(ツク防止層、5・・・・・・p−工n
Pクラッド層、6・・・エツチングマスク、7.8・・
・・・・エツチング溝、9メサストライプ、10・・・
・・・p−InP電流電流クロッ2層1・・・・・・n
−InP電流電流クロッ2層12・・・・・・p−In
P埋め込み層、13−=−p−In O,72GaO,
2!l A S 0.6 l p a 39電極層、1
4・拳・・・・p形オーミック電極、15・・・・・・
n形オーミ、り電極、22・・・回折格子、23 ・−
−−−−n−Ino、a *Gao、t xAso、z
 4Pθ76光ガイド層、24−−−−InoフzQa
o、zs  AsO,1lIP0.39活性層、25 
・−・・・−p−InP  クラッド層、26−−−−
・−p−Ino、tsQBo、zzAso4g  Po
、82層、27・・・・・・エツチング面 である。
Figure 1 (a), (b), (cl is a cross-sectional view shown in the order of manufacturing steps of the first embodiment of the present invention, Figure 2 (al, (
bl is a cross-sectional view of the second embodiment of the present invention and a cross-sectional view of the mesa stripe in the direction of the resonance axis. In the figure, 1...n-■nP substrate, 2...n-I
nP buffer layer, 3--...-Ino, 5sGaα4
1ASO, 1lopolo active layer, 4...p
-In0. y zQao, z 5Aso, a tPo,
s *Melt, (slip prevention layer, 5...p-techn
P cladding layer, 6... Etching mask, 7.8...
...Etching groove, 9 mesa stripes, 10...
...p-InP current current clock 2 layers 1......n
-InP current current clock 2 layers 12...p-In
P buried layer, 13-=-p-In O, 72GaO,
2! l A S 0.6 l p a 39 electrode layers, 1
4. Fist...p-type ohmic electrode, 15...
N-type ohmic electrode, 22...diffraction grating, 23 ・-
----n-Ino, a *Gao, t xAso, z
4Pθ76 light guide layer, 24----InoFzQa
o, zs AsO, 1lIP0.39 active layer, 25
・----p-InP cladding layer, 26---
・-p-Ino, tsQBo, zzAso4g Po
, 82 layers, 27... are etched surfaces.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に活性層を含む半導体多層膜を積層させた
多1M構造半導体ウェファに、前記活性層よりも深く形
成された2本の平行な溝によってはさまれたメサストラ
イプを形成し、このメサストライプを埋め込み成長して
構成される埋め込みヘテ四構造の半導体レーザにおいて
、前記メサストライプの前記活性層上側にのみ所定中導
体層を形成して前記メサストライプの高さを前記溝の両
側の多層膜よりも高く構成したことを特徴とする半導体
レーザ。
A mesa stripe sandwiched between two parallel grooves formed deeper than the active layer is formed on a multi-1M structure semiconductor wafer in which a semiconductor multilayer film including an active layer is laminated on a semiconductor substrate. In a semiconductor laser with a buried heterostructure formed by growing a stripe in a buried manner, a predetermined intermediate conductor layer is formed only above the active layer of the mesa stripe to adjust the height of the mesa stripe to a multilayer film on both sides of the groove. A semiconductor laser characterized by having a structure higher than that of the semiconductor laser.
JP11652182A 1982-07-05 1982-07-05 Semiconductor laser Pending JPS596588A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11652182A JPS596588A (en) 1982-07-05 1982-07-05 Semiconductor laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11652182A JPS596588A (en) 1982-07-05 1982-07-05 Semiconductor laser

Publications (1)

Publication Number Publication Date
JPS596588A true JPS596588A (en) 1984-01-13

Family

ID=14689189

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11652182A Pending JPS596588A (en) 1982-07-05 1982-07-05 Semiconductor laser

Country Status (1)

Country Link
JP (1) JPS596588A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62230078A (en) * 1986-03-31 1987-10-08 Nec Corp Buried semiconductor laser
JPH0222880A (en) * 1988-07-11 1990-01-25 Fujitsu Ltd Semiconductor light-emitting element and manufacture
US5805627A (en) * 1995-02-07 1998-09-08 Fujitsu Limited Laser diode and optical communications system using such laser diode

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62230078A (en) * 1986-03-31 1987-10-08 Nec Corp Buried semiconductor laser
JPH0222880A (en) * 1988-07-11 1990-01-25 Fujitsu Ltd Semiconductor light-emitting element and manufacture
US5805627A (en) * 1995-02-07 1998-09-08 Fujitsu Limited Laser diode and optical communications system using such laser diode

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