JPH02181491A - Semiconductor light-emitting device - Google Patents

Semiconductor light-emitting device

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Publication number
JPH02181491A
JPH02181491A JP157689A JP157689A JPH02181491A JP H02181491 A JPH02181491 A JP H02181491A JP 157689 A JP157689 A JP 157689A JP 157689 A JP157689 A JP 157689A JP H02181491 A JPH02181491 A JP H02181491A
Authority
JP
Japan
Prior art keywords
layer
conductivity type
contact
leakage current
semiconductor light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP157689A
Other languages
Japanese (ja)
Inventor
Osamu Obara
治 小原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP157689A priority Critical patent/JPH02181491A/en
Publication of JPH02181491A publication Critical patent/JPH02181491A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain large optical output even under a high temperature by a method wherein the generation of a leakage current is inhibited and an injection current is concentrated on an active layer by a structure, in which a P-N junction to be used as a leakage current path is eliminated. CONSTITUTION:A semiconductor light-emitting device has a mesa stripe 20 formed by laminating a one conductivity type buffer layer 12, an active layer 13 and an opposite conductivity type clad layer 14 on a semiconductor substrate 11 and opposite conductivity type and one conductivity type buried layers 15 and 16, which are laminated coming into contact to both side surfaces of the stripe 20, and is constituted into a structure in which the layer 15 comes into contact to the layer 12 and does not come into contact to the layer 14 and the layer 16 comes into contact to the layer 14 and does not come into contact to the layer 12. Thereby, a leakage current in a buried semiconductor element is reduced and a current can be concentrated on the active layer. Accordingly, the high-temperature characteristic of the element is improved.

Description

【発明の詳細な説明】 〔概要〕 埋込型半導体発光装置の構造に関し。[Detailed description of the invention] 〔overview〕 Regarding the structure of an embedded semiconductor light emitting device.

埋込型半導体発光素子のリーク電流を低減し。Reduces leakage current of embedded semiconductor light emitting devices.

活性層に電流を集中させることを目的とし。The purpose is to concentrate the current in the active layer.

半導体基板(11)上に一導電型バッファ層(12)と
活性層(13)と反対導電型クラッド層(14)が積層
されたメサストライプ(20)と、該メサストライプの
両側面に接して積層された反対導電型埋込iJ (15
)と一導電型埋込層(16)とを有し。
A mesa stripe (20) in which a buffer layer (12) of one conductivity type, an active layer (13), and a cladding layer (14) of an opposite conductivity type are laminated on a semiconductor substrate (11), and a mesa stripe (20) in contact with both sides of the mesa stripe. Laminated opposite conductivity type embedded iJ (15
) and a buried layer (16) of one conductivity type.

該反対導電型埋込層(15)は一導電型バッファ層(1
2)に接し且つ反対導電型クラッド層(14)に接せず
、該一導電型埋込層(16)は反対導電型クラッド層(
14)に接し且つ一導電型バッファ層(12)に接しな
いで構成する。
The opposite conductivity type buried layer (15) is one conductivity type buffer layer (1
2) and not in contact with the opposite conductivity type cladding layer (14), the one conductivity type buried layer (16) is in contact with the opposite conductivity type cladding layer (14).
14) and not in contact with one conductivity type buffer layer (12).

〔産業上の利用分野〕[Industrial application field]

本発明は埋込型の半導体発光装置の構造に関する。 The present invention relates to the structure of an embedded semiconductor light emitting device.

近年の光通信システムの進展に伴い、 InGaAsP
活性層を有する埋込型半導体発光素子は、長波長帯の光
通信用光源として用いられるようになり。
With the recent progress in optical communication systems, InGaAsP
Embedded semiconductor light emitting devices with active layers have come to be used as light sources for long wavelength optical communications.

又、この発光素子が使用°される環境も多種多様となり
つつある。
Furthermore, the environments in which these light emitting elements are used are becoming increasingly diverse.

そのため、素子に要求される特性も耐環境性が重視され
るようになり1例えば、高温下での安定動作、大出力発
振等が望まれてきている。
For this reason, environmental resistance has become more important in the characteristics required of devices. For example, stable operation under high temperatures, high output oscillation, etc. have become desirable.

この発光素子は、従来n型tnP基板を用いたものが一
般的であったが、p型InP基板を用いたものが前記の
高温特性に優れているという特徴を見いだされ着目され
てきた(埋込層は、p型基板の場合はpnp構造となり
、n型基板のnpn構造よりトランジスタ作用によるリ
ーク電流が低減されるため)ので1本発明ではp型基板
の場合を例にとり説明する。
Conventionally, this light-emitting element used an n-type tnP substrate, but one using a p-type InP substrate has been attracting attention since it was discovered that it has the above-mentioned excellent high-temperature characteristics. In the case of a p-type substrate, the embedded layer has a pnp structure, which reduces leakage current due to transistor action compared to the npn structure of an n-type substrate. Therefore, in the present invention, the case of a p-type substrate will be explained as an example.

(従来の技術) 第2図はp型InP基板を用いた半導体発光素子の従来
例を説明する要部断面図である。
(Prior Art) FIG. 2 is a sectional view of a main part illustrating a conventional example of a semiconductor light emitting device using a p-type InP substrate.

この素子は特願昭63−130810に開示されたもの
である。
This device is disclosed in Japanese Patent Application No. 130810/1983.

図において、1はp型(p−) InP基板。In the figure, 1 is a p-type (p-) InP substrate.

2はp−InPバッファ層、3はInGaAsP活性層
2 is a p-InP buffer layer, and 3 is an InGaAsP active layer.

4はn型(n−) InPnチク5フ、5はp−1nP
埋込層。
4 is n-type (n-) InPn type 5, 5 is p-1nP
Embedded layer.

6はn−1nP埋込層、7はp−1nP埋込層。6 is an n-1nP buried layer, and 7 is a p-1nP buried layer.

8はn−InPnチク5フ、9はn−1nGaAsPコ
ンタクト層である。
8 is an n-InPn layer, and 9 is an n-1nGaAsP contact layer.

又、クラッド層4と活性層3とバッファ層2がメサスト
ライプlOを構成している。
Further, the cladding layer 4, the active layer 3, and the buffer layer 2 constitute a mesa stripe IO.

この従来例では+ n−InPnチク9フ4の側面にp
”−1nP埋込層5Aを設けることにより+9”−1n
P埋込層5AからのZnの固相拡散によりn−1nPク
ラッド層4の側面にp−型反転層5Bを形成し、ここが
高抵抗層となることによってメサストライプ10の側面
のリーク電流へ1を低減させ、低しきい値電流と高発光
効率を実現させたものである。
In this conventional example, p is placed on the side of + n-InPn pixel 9
By providing the ``-1nP buried layer 5A, +9''-1n
A p-type inversion layer 5B is formed on the side surface of the n-1nP cladding layer 4 by solid-phase diffusion of Zn from the P buried layer 5A, and this becomes a high-resistance layer to cause leakage current on the side surface of the mesa stripe 10. 1, thereby realizing a low threshold current and high luminous efficiency.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、上記の従来例による素子は、リーク電流
A1を低減させるためのρ−型反転層5Bを有するとは
いえ、p−型反転層5Bとn−InPクラッド層4間で
pn接合を形成しているため、光出力を増すべく通電電
流を大き°くしだ際はリーク電流A1が増大する。
However, although the device according to the above conventional example has the ρ-type inversion layer 5B for reducing the leakage current A1, a pn junction is not formed between the p-type inversion layer 5B and the n-InP cladding layer 4. Therefore, when the applied current is increased to increase the optical output, the leakage current A1 increases.

又、メサストライプ10の上部のn−InPクラッド層
8とp” −1nP埋込層5A間にもpn接合を形成し
ているため、リーク電流A2も増大する。
Further, since a pn junction is also formed between the n-InP cladding layer 8 and the p''-1nP buried layer 5A above the mesa stripe 10, the leakage current A2 also increases.

そのため、注入電流は活性層に集中しないで。Therefore, the injected current should not be concentrated in the active layer.

結果として発光効率が低下し、光出力が制約されてしま
う。そしてこの発光効率が低下する時点の光出力は、リ
ーク電流の低減度合が大きくなるに従い大きくなる。
As a result, luminous efficiency decreases and light output is restricted. The optical output at the time when the luminous efficiency decreases increases as the degree of reduction in leakage current increases.

本発明は9例えばp−InP基板上にInGaAsP活
性層を有する埋込型半導体発光素子のリーク電流を低減
し、活性層に電流を集中させることを目的とする。
An object of the present invention is to reduce the leakage current of a buried semiconductor light emitting device having an InGaAsP active layer on a p-InP substrate, for example, and to concentrate the current in the active layer.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題の解決は、半導体基板(11)上に一導電型バ
ッファ層(12)と活性層(13)と反対導電型クラッ
ド層(14)が積層されたメサストライプ(20)と。
The solution to the above problem is to create a mesa stripe (20) in which a buffer layer (12) of one conductivity type, an active layer (13), and a cladding layer (14) of the opposite conductivity type are laminated on a semiconductor substrate (11).

該メサストライプの両側面に接して積層された反対導電
型埋込層(15)と一導電型埋込層(16)とを有し、
該反対導電型埋込層(15)は一導電型バッファ層(1
2)に接し且つ反対導電型クラッド層(14)に接せず
、該一導電型埋込Ji! (16)は反対導電型クラッ
ド層(14)に接し且つ一導電型バッファ層(12)に
接しないで構成されていることを特徴とする半導体発光
装置により達成される。
A buried layer (15) of opposite conductivity type and a buried layer (16) of one conductivity type are laminated in contact with both sides of the mesa stripe,
The opposite conductivity type buried layer (15) is one conductivity type buffer layer (1
2) and not in contact with the opposite conductivity type cladding layer (14), the one conductivity type buried Ji! (16) is achieved by a semiconductor light emitting device characterized in that it is configured to be in contact with the opposite conductivity type cladding layer (14) and not in contact with the one conductivity type buffer layer (12).

〔作用〕[Effect]

本発明はリーク電流の経路となるpn接合をなくした構
造により、リーク電流の発生を抑制して活性層に注入電
流を注入を集中するようにしたものである。
The present invention uses a structure that eliminates the pn junction that serves as a path for leakage current, thereby suppressing the generation of leakage current and concentrating the injection current into the active layer.

〔実施例〕〔Example〕

第1図はp型InP基板を用いた半導体発光素子の一実
施例を説明する要部断面図である。
FIG. 1 is a sectional view of a main part of an embodiment of a semiconductor light emitting device using a p-type InP substrate.

図を用いて製法の概略とともにその構造を説明する。An outline of the manufacturing method and its structure will be explained using figures.

図において、まず2液相エピタキシヤル成長(LPE)
法により2面指数χ100)のp−1nP基板ll上に
In the figure, first two liquid phase epitaxial growth (LPE)
on a p-1nP substrate 11 with a dihedral index χ100).

p−1nPバッファ層12 (Cdドープ、キャリア濃度6X10”c+e−’厚さ
〜0.5 μm)+ InGaAsP活性層13 (アンドープ、組成は波長表示で1.3μm。
p-1nP buffer layer 12 (Cd doped, carrier concentration 6×10"c+e-' thickness ~0.5 μm) + InGaAsP active layer 13 (undoped, composition is 1.3 μm in wavelength.

厚さ〜0.12μm)+ n−InPクラッド層14 (Snドープ、キャリア濃度lXl0”cm−’厚さ〜
0.5 μm)。
Thickness ~ 0.12 μm) + n-InP cladding layer 14 (Sn-doped, carrier concentration lXl0''cm-' thickness ~
0.5 μm).

InGaAsPキャップN(図示せず)(アンドープ、
組成は波長表示で1.2μm。
InGaAsP cap N (not shown) (undoped,
The composition is 1.2 μm in wavelength.

厚さ〜0.05μm)。thickness ~0.05 μm).

を順次成長する。grow sequentially.

ライで、 <011>方向に幅3μmのSiO□ストラ
イプマスクを形成し、これをマスクにしてまずInGa
AsPキャップ層を硝酸でウェットエツチングし1次に
n−1nPクラッド層14を臭化水素酸でウェットエツ
チングし、 InGaAsP活性113を硝酸でウェッ
トエツチングする。
A SiO □ stripe mask with a width of 3 μm is formed in the <011> direction in a lie, and using this as a mask, the InGa
The AsP cap layer is wet-etched with nitric acid, the n-1nP cladding layer 14 is first wet-etched with hydrobromic acid, and the InGaAsP active layer 113 is wet-etched with nitric acid.

その後、臭素系のエッチャントを用いてp−1nPバッ
ファ層12をエツチングして、 InGaAsP活性層
13の下のp−1nPバッファ層12の側面に(111
)A面を出しl)、メサストライプ20を形成する。
Thereafter, the p-1nP buffer layer 12 is etched using a bromine-based etchant, so that (111
) Expose side A and form mesa stripes 20.

1) FUJITSU Sci、 Tech、 J。1) FUJITSU Sci, Tech, J.

24、2.p140 (June 1988)。24, 2. p140 (June 1988).

なお、ストライプマスクは、プラズマCvD法によりS
iO2膜を被着し、これを通常のりソグラフィ技術でパ
ターニングして形成する。
Note that the stripe mask is made of S by plasma CVD method.
An iO2 film is deposited and patterned using conventional gluing lithography techniques.

次いで再びLPB法により。Then again by the LPB method.

n−1nP第1埋込層15 (Teドープ、キャリア濃度2X1018cm−’厚さ
〜0.7 μm)+ p−1nP第2埋込層16 (Znドープ、キャリア濃度2X10Il1cm−’厚
さ〜0.6 μm) を順次成長する。
n-1nP first buried layer 15 (Te doped, carrier concentration 2X1018 cm-'thickness ~ 0.7 μm) + p-1nP second buried layer 16 (Zn doped, carrier concentration 2X10Il1 cm-' thickness ~0.7 μm). 6 μm) were grown sequentially.

この際、臭素系のエッチャントのウェットエツチングで
形成されたInGaAsP活性層13の下のp−1nP
バッファ層12の側面に出た(111)A面は濡れにく
いので、 n−InP第1埋込層15はInGaAsP
活性層13より上には這い上がらず、 n−InPクラ
ッド層14と分離できる。
At this time, p-1nP under the InGaAsP active layer 13 formed by wet etching with a bromine-based etchant.
Since the (111) A surface exposed on the side surface of the buffer layer 12 is difficult to wet, the n-InP first buried layer 15 is made of InGaAsP.
It does not rise above the active layer 13 and can be separated from the n-InP cladding layer 14.

更に、ストライプマスクとキャップ層を除去した後。Further, after removing the stripe mask and cap layer.

n−InPクラッド層17 (Teドープ、キャリア濃度lXl0”c+m−’厚さ
〜0.3 μm)+ n−1nGaAsPコンタクト層18 (Teドープ、キャリア濃度2.4X10”cm−’厚
さ〜0.2 μm) を成長する。
n-InP cladding layer 17 (Te doped, carrier concentration lXl0''c+m-' thickness ~0.3 μm) + n-1nGaAsP contact layer 18 (Te doped, carrier concentration 2.4X10''cm-' thickness ~0.3 μm) 2 μm).

この後は1図示しないが基板11の下面及びコンタクト
層18の上面にオーミックコンタクトの電極を形成し、
共振器長(メサストライプ方向)で基板側面をへき関し
てレーザを完成する。
After this, although not shown, ohmic contact electrodes are formed on the lower surface of the substrate 11 and the upper surface of the contact layer 18,
Separate the sides of the substrate along the cavity length (in the mesa stripe direction) to complete the laser.

このようにして素子を作製すると、リーク電流の経路と
なるメサ側面のpn接合は無(なり、リーク電流の発生
が抑制される。
When the device is manufactured in this manner, there is no pn junction on the side surface of the mesa, which serves as a path for leakage current, and the generation of leakage current is suppressed.

更に、メサ側面でn−InP第1埋込層15(電流遮断
層)を従来例構造のものより厚くすることができるので
5層16.15.12で形成されるpnp  トランジ
スタの作用によるリーク電流も抑制できる。
Furthermore, since the n-InP first buried layer 15 (current blocking layer) on the mesa side surface can be made thicker than that of the conventional structure, leakage current due to the action of the pnp transistor formed of five layers 16, 15, 12 is reduced. can also be suppressed.

又、従来例のような固相拡散のための埋込層を必要とし
ないので、素子形成が容易である。
Further, since a buried layer for solid-phase diffusion unlike the conventional example is not required, device formation is easy.

実施例では、高温特性のよいP型基板を使用した例につ
いて説明したが、n型基板の場合も同様の効果が得られ
ることは明らかである。
In the embodiment, an example using a P-type substrate with good high-temperature characteristics has been described, but it is clear that similar effects can be obtained with an N-type substrate.

又、実施例ではInGaAsP/InP系のレーザにつ
いて説明したが9本発明はその他の化合物半導体。
Furthermore, although the InGaAsP/InP-based laser has been described in the embodiments, the present invention also applies to other compound semiconductors.

例えばAlGaAs/GaAs系のレーザについても適
用できる。
For example, it can also be applied to AlGaAs/GaAs lasers.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、埋込型半導体発光
素子のリーク電流を低減し、活性層に電流を集中させる
ことができる。
As described above, according to the present invention, leakage current of a buried semiconductor light emitting device can be reduced and current can be concentrated in the active layer.

従って、素子の高温特性の向上、即ち高温下においても
大きな光出力が得・られるようになる。
Therefore, the high temperature characteristics of the element are improved, that is, a large optical output can be obtained even at high temperatures.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はp型InP基板を用いた半導体発光素子の一実
施例を説明する要部断面図。 第2図はp型1nP基板を用いた半導体発光素子の従来
例を説明する要部断面図である。 図において。 11はp−1nP基板。 12はp−TnPバッファ層。 13はTnGaAsP活性層。 14はn−nPツク9フ層。 15はn−nP第1埋込層。 16はp−nP第2埋込層。 17はn−nPツク9フ層。 18はn−nGaAsPコンタクト層。 20はメサストライプ
FIG. 1 is a sectional view of a main part of an embodiment of a semiconductor light emitting device using a p-type InP substrate. FIG. 2 is a sectional view of a main part explaining a conventional example of a semiconductor light emitting device using a p-type 1nP substrate. In fig. 11 is a p-1nP substrate. 12 is a p-TnP buffer layer. 13 is a TnGaAsP active layer. 14 is the n-nP 9th layer. 15 is an n-nP first buried layer. 16 is a p-nP second buried layer. 17 is the n-nP 9th layer. 18 is an n-nGaAsP contact layer. 20 is mesa stripe

Claims (1)

【特許請求の範囲】 半導体基板(11)上に一導電型バッファ層(12)と
活性層(13)と反対導電型クラッド層(14)が積層
されたメサストライプ(20)と、該メサストライプの
両側面に接して積層された反対導電型埋込層(15)と
一導電型埋込層(16)とを有し、 該反対導電型埋込層(15)は一導電型バッファ層(1
2)に接し且つ反対導電型クラッド層(14)に接せず
、該一導電型埋込層(16)は反対導電型クラッド層(
14)に接し且つ一導電型バッファ層(12)に接しな
いで構成されていることを特徴とする半導体発光装置。
[Claims] A mesa stripe (20) in which a buffer layer (12) of one conductivity type, an active layer (13), and a cladding layer (14) of an opposite conductivity type are laminated on a semiconductor substrate (11), and the mesa stripe. has an opposite conductivity type buried layer (15) and a one conductivity type buried layer (16) laminated in contact with both side surfaces of the one conductivity type buffer layer ( 1
2) and not in contact with the opposite conductivity type cladding layer (14), the one conductivity type buried layer (16) is in contact with the opposite conductivity type cladding layer (14).
14) and not in contact with a one-conductivity type buffer layer (12).
JP157689A 1989-01-06 1989-01-06 Semiconductor light-emitting device Pending JPH02181491A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP157689A JPH02181491A (en) 1989-01-06 1989-01-06 Semiconductor light-emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP157689A JPH02181491A (en) 1989-01-06 1989-01-06 Semiconductor light-emitting device

Publications (1)

Publication Number Publication Date
JPH02181491A true JPH02181491A (en) 1990-07-16

Family

ID=11505345

Family Applications (1)

Application Number Title Priority Date Filing Date
JP157689A Pending JPH02181491A (en) 1989-01-06 1989-01-06 Semiconductor light-emitting device

Country Status (1)

Country Link
JP (1) JPH02181491A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04280493A (en) * 1991-03-07 1992-10-06 Sumitomo Electric Ind Ltd Semiconductor laser
JP2009266891A (en) * 2008-04-22 2009-11-12 Sumitomo Electric Ind Ltd Semiconductor laser and method of manufacturing same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04280493A (en) * 1991-03-07 1992-10-06 Sumitomo Electric Ind Ltd Semiconductor laser
JP2009266891A (en) * 2008-04-22 2009-11-12 Sumitomo Electric Ind Ltd Semiconductor laser and method of manufacturing same

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