JPH0555951B2 - - Google Patents

Description

[Detailed Description of the Invention] Detailed Description of the Invention When recording and reproducing an information signal, for example, an audio signal, high-quality recording and reproducing can be achieved by converting the audio signal into PCM.

There are fixed head methods and rotating head methods for converting information signals into PCM and recording and reproducing them on magnetic tape, but the rotating head method is preferred because the relative speed of the head to the tape is faster and the recording density can be easily increased. is advantageous. In this rotary head system, for example, when a plurality of rotary heads, for example two, are used, the number of rotary heads is usually about 36.
The magnetic tape is attached at an angular interval of 0°/2 = 180°, and the magnetic tape is wound around the guide drum in the same angular range (180°), and each track is formed alternately by two rotating heads. and record PCM data.

By the way, when recording this PCM data, a unit time worth of data (one segment of data), which is conventionally recorded as one track each, is recorded as one track on the tape. Therefore, if one track's worth of reproduced data is lost due to dropout or the like, a state will occur in which no data exists for a period of time corresponding to this one track. Even if this happens, it is possible to correct it using an error correction method such as so-called pre-hold, which interpolates using the previous one track's worth of data in a so-called error correction circuit, but it is possible to correct the error by using an error correction method such as a so-called pre-hold, which interpolates using the previous one track's worth of data. This method has the disadvantage that signal deterioration is inevitable because the received data is interpolated with previous data.

In view of the above points, this invention is designed so that even if one track's worth of data is lost during playback, when the original time series data is restored during playback, the data can be obtained continuously without almost any loss. The purpose of the present invention is to provide a system that can be strengthened against bust errors, can easily use advanced methods for error correction, and can make signal deterioration almost inconspicuous after correction. be.

An example of this invention will be described below when an audio signal is
Let's explain with reference to the figure, taking as an example the case of recording in PCM format.

By the way, when a PCM signal is recorded by a rotary head device, as in the case of conventional rotary head devices, for example, there are two rotary heads with an angular spacing of 180 degrees, and the tape is wound around the guide drum. If the corners are also the same 180°, the two heads scan the tape continuously alternately, forming a continuous track in time, and the audio There is no longer enough time to add redundant data such as parity for error correction to the PCM signal. Therefore, a large amount of buffer memory for signal delay must be used, and signal processing tends to become complicated.

Therefore, in this example, a new rotary head type recording and reproducing apparatus is used which is designed to avoid the above-mentioned drawbacks.

FIG. 1 shows an example of a rotary head device used in this new device, in which there are two rotary magnetic heads. In this case, the two rotating heads 1A and 1B are arranged with an angular spacing of 360°/2=180°. On the other hand, the magnetic tape 2 is wound along the circumferential surface of the tape guide drum 3 in an angular range of, for example, 90°, which is smaller than the 180° angular range. Then, the rotating heads 1A and 1B rotate in one second.
The tape 2 is rotated at a rate of 30 rotations in the direction shown by the arrow 5H in the figure, and at the same time is run at a predetermined speed in the direction shown by the arrow 5T.
Therefore, in the 1/4 rotation section, the magnetic tape 2
As shown in FIG. 2, magnetic tracks 4A and 4B, each diagonal, are alternately formed so that signals can be recorded thereon. In this case, the width directions of the gaps of the heads 1A and 1B are different from each other with respect to the direction orthogonal to the scanning direction. In other words, the so-called azimuth angles are different.

According to the above rotary head device, there is a period (in this example, a period corresponding to an angular range of 90°) in which the two rotary heads 1A and 1B do not come into contact with the magnetic tape 2. Take advantage of this period
By adding redundant data such as parity to PCM data, the number of buffer circuits in the recording device can be reduced and the configuration can be simplified.

Next, an embodiment of a recording apparatus and a reproducing apparatus thereof according to the present invention using this rotary head device will be described.

FIG. 3 shows an example of a recording system.

The example shown in FIG. 3 is an example in which an audio signal is recorded as a two-channel signal, a right channel and a left channel.

In this case, the rotating magnetic heads 1A and 1B are rotated at 30 Hz as described above, and the rotational phase is controlled as follows.

That is, in the control signal generation circuit 10, the clock signal 30 is generated based on the master clock signal from the master clock generation circuit 9.
The Hz reference signal CT is supplied to the phase comparator circuit 8.
Also, 1 rotation per rotation of rotary heads 1A and 1B.
A signal from the pulse generator 6 that generates pulses
PG is supplied to this phase comparator circuit 8, and from this a voltage corresponding to the phase error between the signal CT and the signal PG is supplied to the rotary head drive drum motor 7. The rotation phase is controlled to have a predetermined relationship.

The control signal generating circuit 10 also generates a signal CT based on this master clock signal.
Generates various control signals as described below. Therefore, the phases of the various control signals are the same as the phase of the signal CT, that is, heads 1A and 1.
Synchronize with the rotational phase of B.

The left channel and right channel audio signals S _L and S _R are supplied to one and the other input ends of a switch circuit 23 through input terminals 21 and 22, respectively. This switch circuit 23 is alternately switched to one and the other input terminal by a switching signal SW of, for example, 44.1 kHz (FIG. 4A) from the control signal generating circuit 10. Therefore, as shown in FIGS. 4A and 4B, this switch circuit 23 outputs a left channel signal when the switching signal SW is at a high level, and a right channel signal when the signal SW is at a low level. The signals are respectively taken out and supplied to the A/D converter 24. This A/D converter 24
In this case, each channel is sampled at a sampling frequency of 44.1kHz. The signal SP from the control signal generation circuit 10 is this sampling signal, and the audio signals of the left and right channels are each sampled by this signal SP, and this sampled data is converted into, for example, 16-bit PCM per sample. signal
converted to S ₀ . FIG. 4B shows the output signal S ₀ of this A/D converter, L ₀ , L ₁ , L ₂ . . . represent one data word of the audio PCM signal of the left channel, and R ₀ , R ₁ , R ₂ . . . each indicate one data word of the audio PCM signal of the right channel.

The output signal _S0 of the A/D converter 24 is sent to three RAMs 31, 32, 33 through a switch circuit 25.
However, as explained later, 2 out of 3
Two RAMs are not in the write state, and redundant data is added or data to which the redundant data is added is read in the two RAMs that are not in the write state.

Three signals from the control signal generation circuit 10
A control signal RW for controlling writing to the RAMs 31, 32, and 33 is transmitted through a switch circuit 26 to
It is supplied to the control terminals of RAMs 31, 32, and 33. The switch circuits 25 and 26 receive switching signals from the control signal generation circuit 10.
SWW sequentially switches the three RAMs 31, 32, and 33 every 1/60 seconds in the switching order shown in FIG. 4F. In other words, the three RAMs 31 to 33 are switched at a cycle of 1/20 seconds.

Therefore, PCM audio data for a unit time of 1/60 seconds is sequentially written into the three RAMs 31, 32, and 33 as shown in FIG. 4, C, D, and E. That is, the data group [1] for a unit time is stored in RAM31, the data group [2] for the next unit time is stored in RAM32, the data group [3] for the next unit time is stored in RAM33, and so on. A data group for a period of 1/60 seconds is sequentially written into the three RAMs 31, 32, and 33.

Here, the number of samples included within the period of 1/60 second is 1470, which is the number of samples included in the left channel audio signal words L ₀ to L ₇₃₄ as shown in FIG. 4B.
This corresponds to a total of 1470 words, including 735 words and 735 words of words L ₀ to L ₇₃₄ of the right channel audio signal. In this example, the data equivalent to this 1/60 second period is assumed to be data for a unit time, and the RAM 31
-33 are each said to have a capacity that can store 1470 words.

In this way, 3 pieces per unit time every 1/60 seconds
Parity P and Q for error correction are added to all data written to RAM31, 32, and 33, and the data is divided into odd and even data. Parity EP and EQ, parity OP and OQ, and a CRC code for error detection are added to the data, and each added odd number data and even number data is compressed on the time axis.
Reading is performed from RAM.

Here, the odd data refers to the odd data words of the left channel and the right channel among the multiple data words for the unit period of 1/60 seconds, and as shown in FIG. 4B, the data of the left channel Word L ₁ , data word R ₁ in the right channel, data word L ₃ in the left channel, data word R ₃ in the right channel, and so on, for a total of 734 word pairs in the left and right channels with suffixes 1, 3, 5...733. data words.
On the other hand, even data refers to the even-numbered data words of the left channel and the right channel among the plurality of data words for this unit period, and as shown in FIG. 4B, the word L of the left and right channels is ₀ , R ₀ , L ₂ , R ₂ , . . . , the left and right channel word pairs with suffixes of 0, 2, 4, 6, . . . 734 are a total of 736 data words.

Parity is added to and read from data written in each RAM as follows.

That is, in order to control whether the control signal generating circuit 10 generates and adds parity to all data for a unit period, or generates parity only to odd data among them and adds it to the odd data. A control signal RAO is obtained, which is supplied to the control terminals of the three RAMs 31, 32, and 33 through the switch circuit 27. In addition, it is possible to generate parity for even data of data for a unit period and add it.
A signal RER for controlling whether to sweep data from RAM 3 is obtained from the generation circuit 10, and this signal is sent to the three RAMs 3 through a switch circuit 28.
It is supplied to control terminals 1, 32, and 33. On the other hand, the output data of these three RAMs 31, 32, and 33 is supplied through a switch circuit 29 to a parity adding circuit 37 for all data for a unit period, and also a parity and CRC code for odd data of the data for a unit period. additional circuit 38
and three RAMs 31, 32, 33
The output data is supplied to a parity and CRC code addition circuit 39 for even data using the switch circuit 30. The output data of the additional circuits 37 and 38 are supplied to the input terminals of the three RAMs 31, 32, and 33 via the switch circuits 34 and 35, and the output data of the additional circuit 39 is supplied to the input terminals of the three RAMs 31, 32, and 33 via the switch circuit 36. RAM31,3
It is supplied to input terminals 2 and 33.

The switch circuits 27, 29 and 35 receive switching signals from the control signal generation circuit 10.
3 in the order shown in Figure 4G by SWPO.
RAMs 31, 32, 33 are switched, and switch circuits 28, 30, and 36 are switched.
is the switching signal from the control signal generation circuit 10
3 in the order shown in Figure 4H by SWER.
Switching is performed for the RAMs 31, 32, and 33.

In this case, the three RAMs 31, 32, and 33 are in a readable state when they are not in a write state, and data is output.

In addition, the control signal AP of the additional circuit 37 (I in FIG. 4)
is obtained from the control signal generating circuit 10, and is supplied to the additional circuit 37, so that the additional circuit 37 is activated during the period of 1/120 seconds when the signal is at a high level. Also, this signal AP
A signal OPC of opposite polarity is obtained from the control signal generation circuit 10, and this signal OPC is sent to the additional circuit 3.
8, and the additional circuit 38 is activated during the period when the signal AP is at the high level, that is, during the period of 1/120 seconds when the signal AP is at the low level.
Furthermore, a signal EPC (FIG. 4 J) with a phase shift of 90 degrees with respect to the signal AP is obtained from the control signal generation circuit 10, and is supplied to the additional circuit 39, and during the high level period, this additional circuit 39 is activated. Becomes operational.

The signal AP is a signal that exactly matches the switching timing of the three RAMs 31, 32, and 33 for one period.
Writing to RAM31, 32, 33 1/
A period of 1/120 seconds in the first half of each period of 60 seconds T ₁ T ₂ T ₃ ,
The signal is at a high level and remains at a low level for a period of 1/120 seconds in the second half.

The signal EPC is a signal whose phase is delayed by 90 degrees with respect to the signal AP, and is at a high level for a 1/120 second period approximately at the center of each 1/60 second period T ₁ T, ₂ T ₃ .
1/240 at the beginning of a period of 1/240 seconds at the end of T ₁ T ₂ T ₃
This is a signal that is at a low level for a total of 1/120 seconds.

The phase of this signal EPC is synchronized with the rotational phase of heads 1A and 1B controlled by the phase servo, and during the period when this signal EP is at a high level, one of heads 1A and 1B is placed on tape 2. is scanned, and during the period in which it is at a low level, both heads 1A and 1B do not come into contact with tape 2.

From the above, for example, for the unit period of data written to the RAM 31 in period T ₁ , in periods T ₂ and T ₃ , parity is generated and read out for all data, and parity is generated and added to each of odd and even data. etc. and reading is performed.

That is, in period T ₂ , the switching signal
Switch circuits 27, 29, 35 by SWPO
is switched to select the RAM 31, and this RAM 31 is set to a mode of generating and adding parity P and Q to all data, generating and adding parity OP and OQ to odd data, and generating and adding a CRC code. That is, in the first half of this period _T2 , when the signal AP becomes high level, the additional circuit 37 becomes operational, and the RAM 31
Parity P and Q for all data for a unit period are generated in an additional circuit 37,
It is added to all the data. This parity P, Q
The switch circuit 3 is added to that data.
4 and 35, the data is returned to a predetermined address in the RAM 31 and written therein. The switch circuit 34 is configured to be switched to the state shown in the figure during the high level period by a signal similar to the signal AP, and to the state opposite to the state shown in the figure during the low level period.

Next, in the latter half of period _T2 , the signal AP becomes low level, and therefore the signal OPC becomes high level, and the odd data parity and CRC code generation/addition circuit 38 becomes operational, and the switch circuit 34 is switched to the state opposite to that shown in the figure, and parity OP and OQ are generated and a CRC code is added to only the odd data out of the unit time data written in the RAM 31 and added to the data. , the data in the added state is written to a predetermined address in the RAM 31 through the switch circuits 34 and 35.

Next, in period _T3 , the switch circuits 28, 30, and 36 are switched to the RAM 3 by the switching signal SWER.
The RAM 31 is switched to the 1 side, and the RAM 31 is placed in a read mode or a mode for generating and adding parity and CRC codes to even data. And the signal
Since EPC is at a low level for 1/240 seconds at the beginning of this period _T3 , the additional circuit 39 is in an inactive state, and the control signal RER sends the parity P, Q, and the parity data for all data from the RAM 31. Odd data to which parity OP, OQ, and CRC codes are added is read out during this 1/240 second period.

After that, when the signal EPC becomes high level, the additional circuit 39 becomes operational and even data is read from the RAM 31, and the parity data for this is read out.
EP and EQ as well as CRC codes are generated in the addition circuit 39 and added to the even data, and the added data is sent to the switch circuit 36.
The data is written again to a predetermined address in the RAM 31 via the . And this even data is this period T ₃
Since the signal EP becomes low level during the 1/240 second period at the end of the period, it is read out.

Similarly, in the period T ₂ , for the data written in the RAM 32 for a unit time, in the first half of the period T ₃ , parity P and Q are generated and added to all the data, and in the second half, parity OP is added to the odd data among them. , OQ and CRC codes are added. and the next period
In the period of 1/240 seconds at the beginning of T ₁ , the odd data to which the parity P, E, OP, OE and CRC code are added is read, and in the middle of this period T ₁ , the parity for the even data is read.
Generation of EP, EQ and CRC codes is added, and the even data with parity P, Q, EP, EQ and CRC codes is read out in a period of 1/240 seconds at the end of this period _T1 . .

Parity and CRC codes are generated and added to the data read out to _the RAM 33 in period T ₃ in the same way, and parity P, Q, Odd data with parity OP, OQ and CRC code added to the odd data is read out, and in the last 1/240 second period, the parity P, OQ and CRC code are added.
Even data to which Q, EP, EQ, and CRC codes are added is read.

The above modes of RAM31, 32, and 33 are the 4th mode.
As shown in Figures C, D, and E. Further, the timing of the read data is as shown in FIG. As can be seen from this figure, a data group for a unit time, for example, odd number data (1
O) is read out during a period of 1/240 seconds at the beginning of period T ₃ , and even data (1E) is read out during a period of 1/240 seconds at the end of period T ₃ , and the next data group [1] is read out. Odd number data (2) of data group [2] is generated in the first 1/240 second period of period T ₁ following period T ₃ , and even number data (2E) is generated in the last 1/240 second period, respectively. Read out. Similarly, odd data (3) (4) of data group [3, 4, 5]...
(5) ... and odd number data (3E) (4E) (5E) ... are each divided into periods of 1/240 seconds at the beginning and end of any of the 1/60 second periods T ₁ T ₂ T ₃ . It will be read out. Then, when viewed as a continuous data flow, 1/1 at the end of each period T ₁ , T ₂ , T ₃
240 seconds period to the beginning of the next period T ₂ , T ₃ , T ₁
A series of data includes up to a 40 second period. Therefore, the first half of the data in this example is even data, and the second half is odd data, and the even data and odd data are data from data groups for different unit periods.

Here, the read odd number data and even number data have the following configuration. That is, in the process of generating and adding parity and CRC codes, PCM audio data is divided into blocks of 8 data words as shown in FIG. Parity words P and Q are added,
When the data word is even data, further parity words EP, EQ and CRC code are added, while when the data word is odd data, parity words OP, OQ and CRC code are added.

In this case, the eight data words that constitute one block are interleaved so that the read addresses of the RAMs 31 to 33 are controlled and the data words are distributed. In this case, one block consists of 8 data words, so
As shown in the figure, it consists of 92 blocks consisting of even data blocks and odd data blocks _B0 to _B91 .

In this way, the odd number data and even number data read from each RAM 31 to 33 are sent to the recording processor 4.
0 to two rotating heads 1A and 1B. The rotating heads 1A and 1B receive the signal CT from the control signal generating circuit 10 as described above.
are phase servoed by the respective signal EPC
The tape 2 is scanned during a certain period when the signal is at a low level. Therefore, each 1/120 read out at the timing shown in Figure 4 K
Data for a period of seconds is recorded on the tape 2 by the heads 1A and 1B, alternately forming one track 4A and one track 4B, respectively, during the interval in which the heads 1A and 1B scan the tape 2. That is, as shown in FIG. 2, in the first half of tracks 4A and 4B, even data entries 0E) (1E) (2E) (3E), etc. of data for a certain unit period are recorded.
In the second half of the track, odd number data (1) of the data for the next unit period for that unit period is used.
(2) (3) (4)... will be recorded. Therefore, data recorded on one track spans two unit sections in terms of time. However, since the amount of data recorded on one track is made up of odd number data and even number data, this is exactly equal to the amount of data for a unit section.

In this case, the odd and even data of the PCM data written to each RAM in a period of 1/60 seconds will be recorded in a period of 1/240 seconds, and the time axis of the data will be compressed to approximately 1/4. has been done.

In addition, in the recording processor 40, FIG.
As shown in the figure, the block synchronization signal SYNC and block address data are transmitted for one block of data.
ADS is added. Also, block B ₀ is recorded as even data and odd data, respectively.
From there, a preamble signal and a postamble signal are added to _B91 . The preamble signal is a signal for generating a clock for extracting data during reproduction, and the postamble signal is a signal indicating the end of even or odd data.

In the recording processor 40, further:
A process is also performed in which the PCM data is modulated into a signal suitable for recording, for example, a signal in which the DC component is as small as possible.

Next, we will explain how to play audio PCM data recorded in this way.

What follows is an example of the reproduction system, and FIG. 6 shows its timing chart.

In the reproduction system of FIG. 5, a 30 Hz signal SH (FIG. 6B) generated in the control signal generation circuit 11 based on the output of the master clock generation circuit 9 is used to control the rotary heads 1A and 1B. Phase servo is applied. Control signals during playback obtained from this control signal generation circuit 11, that is, control signals such as a switching signal for the playback output of the head, and write and read signals for this playback output, are at a constant level with this standard 30Hz signal SH. They are designed to have a phase relationship.

The playback output from heads 1A and 1B is from amplifier 4.
It is supplied to the switch circuit 42 through 1A and 41B. This switch circuit 42 is for phase servo.
The amplifier 41A side and the amplifier 41B side are alternately switched by the 30Hz signal SH. Therefore,
From this switch circuit 42, a data string as shown in FIG. 6C is obtained in which the outputs of the head 1A and the outputs of the head 1B are alternately successive.

The data obtained by this switch circuit 42 is supplied to a digital signal restoring circuit 43 where it is restored into a digital signal, and then supplied to an error detection and RAM write control signal generating circuit 44. The error detection and RAM write control signal generation circuit 44 obtains error-detected data S _D , as well as write addresses and write timing signals R _P to the three RAMs 51, 52, and 53.

The switch circuit 45 includes RAMs 51, 52, 53
The error-detected data S _D from the circuit 44
This is a switch for controlling whether to write the error-corrected data from the error correction circuit 46 or to write the error-corrected data for the odd-numbered data from the error correction circuit 46.
First, the import of data _SD will be explained.

The switch circuit 45 is a switching signal from the control signal generation circuit 11 for switching the write and correction modes in the RAMs 51 to 53.
Switched by WO. In other words, this switching signal WO is a 60Hz signal as shown in Figure 6J, but during the high level period _PW of 1/120 seconds in the first half of one cycle, the reproduction output is not obtained from the head 1A or 1B. The second half low level period of 1/120 seconds P _C is for heads 1A and 1B.
In other words, this is a period in which neither of the two heads 1A and 1B is in contact with the tape 2. During the period P _W when the signal WO is at a high level, the switch circuit 45 is switched to the state shown in the figure, and during the period P _C when the signal WO is at a low level, the switch circuit 45 is switched to the state opposite to the state shown in the figure. is being used.

In addition, the write address and write timing signal _RWP from the circuit 44 are sent to the switch circuit 49.
and 50 to the control terminals of RAMs 51, 52, and 53. Also, data for which error detection is output from the circuit 44 through the switch circuit 45
_SD is connected to three RAMs 5 through a switch circuit 54.
The signals are supplied to input terminals 1, 52, and 53, respectively. And RAM51,5
The data read from the circuits 2 and 53 is supplied to the input end of the odd data error correction circuit 46 via the switch circuit 55. The output signal of the odd data error correction circuit 46 is supplied to the other input terminal of the switch circuit 45.

The switch circuits 50, 54, and 55 receive the control signal SWWO from the control signal generation circuit 11.
The three RAMs 51, 52, and 53 are sequentially switched every 1/60 seconds in the order shown in FIG. 6G.

In this case, the three RAM5s by the signal SWWO
The switching timing of 1, 52, 53 is the signal
This is approximately the middle of period P _W when WO is at a high level.

Further, a signal _C0 for controlling the correction mode for odd data is obtained from the control signal generation circuit 11, and this is supplied to the other input terminal of the switch circuit 49, and is sent to the three RAMs 51 through the switch circuit 50. , 52, 53 control terminals. Then, the switch circuit 49 receives the signal WO
is switched in synchronization with the switch circuit 45.

Therefore, the period during which signal WO is at high level
The three RAMs 51 to 53 are in write mode, but during this period P _W is controlled _by the switching signal SWWO.
The switch circuits 50, 54, and 55 are switched to select RAM51, RAM52, and RAM53, respectively, by 1/60 seconds T _A , T _B ,
It corresponds to a period P _O of 1/240 seconds at the beginning of T _C and a period P _E of 1/240 seconds at the end.

Period P _O of 1/240 seconds at the beginning of each period T _A , T _B , T _C
is the second half of the period P _W (corresponding to the second half of the scanning period on tape 2 of the head), and this period
In P _O , as is clear from Figure 6 C and J, the playback head output is odd data (1).
(2)(3)... are obtained. Therefore, during this period P _O , odd number data (1) (2) (3)... are stored in the circuit 44 in each RAM 51, 52, 53.
Write address and timing signals from
Written to the specified address by _RWP .

On the other hand, the period P _E of 1/240 seconds at the end of each period T _A , T _B , T _C is the first half period of the period P _W (corresponding to the first half of the running period on the tape 2 of the head), During this period P _E, as is clear from Figure 6 C and J, even data (1E) is output as the playback head.
(2E) (3E)... is obtained. Therefore, during this period _PE , even data (1E) (2E) (3E) . . . is written into each RAM 51, 52, 53 under the control of the signal RW _P from the circuit 44.

Each period T _A , T _B , during which the signal WO is at low level
During the 1/120 second period P _C at the center of T _C , the switch circuits 45 and 49 are switched to the opposite state to the state shown in the figure, so that the corrected data from the correction circuit 46 is transferred to each RAM 51, 52, 53. In other words, it becomes an odd data correction mode. The control signal generation circuit 11 sends the control signal to the odd data correction circuit 46.
OC is supplied. This signal OC is a signal with a polarity opposite to that of the signal WO, and the correction circuit 46 is enabled to operate during its high level period (this is the period P _C ).

Therefore, the switch circuits 50, 54, and 55 are switched by the signal SWWO, and each RAM
Period when 51, 52, 53 are selected respectively
In period P _C of T _A , T _B , and T _C , the control signal
By C ₀ , the odd data read from each RAM 51, 52, 53 is parity-coded by the correction circuit 46.
OP and OQ are used to correct the error-detected data, and the corrected data is transferred to the original RAM 5 via switch circuits 45 and 54.
1, 52, 53.

and 1/240 at the end of each of the following periods T _A , T _B , T _C
Error correction for even-numbered data written in a period of seconds and error correction for all data are performed as follows.

That is, the control signal _CEA for this purpose is supplied from the control signal generation circuit 11 to the control terminals of the three RAMs 51, 52, and 53 through the switch circuit 56. Further, output data from the three RAMs 51, 52, and 53 is supplied through a switch circuit 56 to an even data correction circuit 47, and is also supplied to a correction circuit 48 for all data for a unit time. The output signal of the correction circuit 47 for even number data and the output signal of the correction circuit 48 for all data are sent to the switch circuit 5.
8, and its output is supplied to the input terminals of three RAMs 51, 52, and 53 through a switch circuit 59. And switch circuit 5
6, 57, and 59 are connected to three RAMs 51, 52, and 59 in the order shown in FIG.
53.

The even data correction circuit 47 also receives the control signal EC (sixth signal) from the control signal generation circuit 11.
K) is supplied, and the correction circuit 47 is operated during the period when it is at a high level.
Further, the correction circuit 48 is supplied with a signal AC having a polarity opposite to that of the signal EC, and the correction circuit 48 is enabled to operate during the period when the signal AC is at a high level. This signal EC has a period T _A ,
This is a signal that is high level in the first half of T _B and T _C and low level in the second half. Therefore, the correction circuit 47 corrects 1/12 of the first half of the period T _A , T _B , T _C
The correction circuit 48 is enabled to operate during a period of 0 seconds, while the correction circuit 48 is enabled for a period of 1/120 seconds in the latter half of the periods T _A , T _B , and T _C . The switch circuit 58 is switched by a signal having the same phase as the signal EC, and is switched to the state shown in the figure during the high level period, and to the opposite state to the state shown in the figure during the low level period.

Therefore, as is clear from Figure 6, the signal
During the period T _B in which the RAM 51 is selected by SWEA, in the first half of this period T _B ,
RAM51 by control signal _CEA from circuit 11
The even number data read from the switch circuit 57
The signal is supplied to an even number data correction circuit 47 and a total data correction circuit 48 through the signal. During this first half period, the even data correction circuit 47 becomes operational, so the parity EP and EQ for the even data are used to perform error correction on the even data, and the corrected data is transferred to the switch circuit. RAM through 58 and 59
It is written to the original predetermined addresses of 51, 52, and 53. Then, in the latter half of this period T _B , the correction circuit 48 for all data becomes operational, so parities P and Q are used to correct data errors for all data corresponding to a unit period. The error-corrected data is then written to a predetermined address in the RAM 51 via switch circuits 58 and 59.

Similarly, during period T _C , even data among the data written in the RAM 52 is corrected using parity EP and EQ, and all data are corrected using parity P and Q, respectively. 47 and 48 and written into RAM 52 at the original address. Furthermore, in period T _A , corrections are made by parity EP and EQ for even data written in the RAM 53 and corrections by parity P and Q for all data are made in circuits 47 and 48, respectively, and the corrected data is
It is written in RAM53.

From the above, in periods T _A , T _B , T _C
After 1/30 second has elapsed after each write period, the data written to RAM51, 52, 53 is within the error correction capacity. All correctable data has been corrected.
This means that PCM data has been written.

The data written and corrected in this manner is read out in a period of 1/60 second after 1/60 second has elapsed from the end of writing.
That is, the read control signal RR from the control signal generation circuit 11 is transmitted through the switch circuit 60.
It is supplied to the control terminals of RAMs 51, 52, and 53. Further, output signals of the RAMs 51, 52, and 53 are supplied to a modification circuit 62 through a switch circuit 61. These switch circuits 60 and 61 receive switching signals from the control signal generation circuit 11.
The SWR switches the three RAMs in the order shown in FIG. 6I. That is, the even data and odd data written to the RAM 51 in the period T _A are read out in the period T _C , and the data written in the RAM 52 in the period T _B are read out in the period T _A , and in the period T _C.
The data written to the RAM 53 is read out during the period T _B. In this case, the even-numbered and odd-numbered data for each unit interval are read out alternately through address processing, and the data for the unit time, which is made into the original time series, is the original time axis of 1/60 second. The data is decompressed and read out as shown in FIG. 6L. The thus read signal is supplied to a correction circuit 62 through a switch circuit 61, and error correction is performed on the data that could not be completely corrected. The output of the error correction circuit 62 is supplied to a D/A converter 63. D/A converter 6
Each sample of the PCM signal converted back to an analog signal in step 3 is converted into a signal at the time of recording by a switch circuit 64.
By being switched by a signal (44.1kHz) with the same frequency as SW, the left channel audio signal S _L passes through amplifier 65L to amplifier 65R.
The right channel audio signal S _R is taken out to output terminals 66L and 66R, respectively.

According to the device of this invention as described above, audio data for a unit time equivalent to one track can be
The data is divided into even-numbered data and odd-numbered data and is recorded across two tracks. Therefore, data for a unit time of the PCM signal is scattered over two tracks. According to this invention, even if one track's worth of data is missing and cannot be obtained during playback, if the preceding and following tracks are being played back, the even or odd number of the missing one segment's worth of data can be retrieved. Since the data of one of the two tracks is always recorded on the previous or next track, there is no possibility that the data will be completely lost even though the data is 1/2 in terms of information. Therefore, for example, in the error correction circuit 62, this 1/2 missing data is used to interpolate the data in between, that is, the even or odd numbered data is used to calculate the odd or odd numbered data by means of average value interpolation. Since even-numbered data words can be interpolated, data with a very good S/N ratio can be obtained as reproduced data after signal processing. Moreover, there is an effect that the configuration for this purpose can be made very easily.

Also, when you start recording continuously from an already recorded part, only the even or odd numbered data of both the old and new data will remain at the joint. Interpolation processing can be performed for signal processing at joints using the same method as the error correction described above, and it is possible to realize a highly effective method such as being able to connect the signal joints smoothly. There is also the advantage of having one.

Furthermore, in this invention, even number (odd number) data is recorded in the first half of one track, and odd number (even number) data is recorded in the second half, so the interleave length is 1/2 that of the conventional one. ,that is,
It will be divided into two parts. However, as is clear from Figures 4 and 6, the time required for error correction is very long, and the correction process can be performed for each even or odd data as well as for the entire data. It has the effect of greatly increasing your abilities.

Furthermore, as mentioned above, by making the winding angle of the tape around the guide drum smaller than the installation angle interval of the heads, that is, 360°/N, where N is the number of rotating heads, the tape can be wrapped around the guide drum at a distance of 360°/N. There is a period during which the
Redundant data can be easily added to the CRC code name, and errors can be corrected during playback, so redundant data during recording can be easily added, as in the conventional case where the tape winding angle is selected to be equal to the head mounting angle interval. This has the advantage that there is no need to perform complex signal processing to create time margin for error correction during reproduction and addition of data, or to use a large amount of delay buffer. However, according to this invention, error correction includes correction for all data, correction for even number data,
Correction for odd number data and correction time can be very long. This does not need to be corrected, and there is plenty of time for correction, not only when the tape winding angle is made smaller with respect to the head mounting angle spacing, but also when the head mounting angle spacing and the tape winding angle spacing are made the same. This provides correction time.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining an example of a rotary head device used in this invention, FIG. 2 is a diagram showing its recording track pattern, FIG. 3 is a system diagram of an example of this invention device, and FIG. 4 is its diagram. FIG. 5 is a diagram showing a timing chart for explanation, FIG. 5 is a system diagram of an example of a reproduction system, and FIG. 6 is a diagram showing a timing chart for explanation. 1A and 1B are rotating heads, 2 is a magnetic tape,
3 is the guide drum, 31, 32, 33 are RAM3
7, 38, and 39 are parity or CRC addition circuits.

Claims (1)

[Claims] 1. Recording PCM data by forming diagonal tracks on a tape-shaped recording medium using a rotating head.
A PCM data recording device includes a memory in which the PCM data is written every unit time, and a memory that divides the written data into even-numbered data and odd-numbered data, means for independently adding redundant data for error correction to each of the odd-numbered data; The even-numbered data and the odd-numbered data are read out from the memory by the rotating head on different tracks of the diagonal tracks formed on the tape-shaped recording medium, and are separated from each other in the first half and the second half in the tape width direction. A PCM data recording device that records at the location. 2. The data is divided into even-numbered data and odd-numbered data for each unit time, and a signal with redundant data for error correction added to the even-numbered data, and a signal with redundant data for error correction added to the above-mentioned odd-numbered data. Reproducing PCM data in which signals to which redundant data have been added are recorded on different tracks of diagonal tracks formed on a tape-shaped recording medium and at separate positions in the first half and the second half in the tape width direction.
A PCM data reproducing device includes a rotary head for reproducing PCM data and redundant data for error correction recorded on the above-mentioned track, and a rotary head for reproducing the PCM data and redundant data for error correction recorded on the above-mentioned track; a memory for writing into each of the first and second halves of the data; and means for error-correcting the written data independently for each of the even-numbered data and the odd-numbered data using the redundant data for error correction; The above even-numbered data and odd-numbered data written in the above are read out alternately.
A PCM data playback device designed to play PCM data.