JPS58188314A - Recorder of pcm data - Google Patents

Abstract

PURPOSE:To add redundant data such as codes easily, by dividing data into an even number order and an odd number order at each unit time of an azimuth recording PCM data, adding the redundant data to each respectively and recording it on the other track. CONSTITUTION:Two rotary magnetic heads 1A, 1B are arranged with a 180 deg. of angular interval and rotated in the rate of 30 revolutions per second. A parity for error correction is added to all data written in three RAMs 31-33 at each 1/60sec, the data is divided into odd number data and even number data, a CRC code for the error detection and the parity are added to each of them, they are compressed for the time axis and read out from each RAM. The output data of parity addition circuits 37, 38 are applied to the input terminals of the three RAMs 31-33 via switch circuits 34, 35. Thus, at recording the addition of the redundant data such as the parity is provided easily to the data of each channel and the error correction is performed at the reproduction.

Description

[Detailed Description of the Invention] When recording and reproducing information signals, for example audio signals,
By converting this audio signal into PCM, high-quality recording and playback can be achieved.

There are two types of methods for converting information signals into PCM and recording and reproducing them on magnetic tape: a fixed head method and a single rotation head method.
The rotating head method is advantageous in that the relative speed of the head to the tape is fast and the recording density can be easily increased.

In this rotary head system, for example, when a plurality of rotary heads, for example two rotary heads, are used, the rotary heads are usually mounted at angular intervals of approximately 180 degrees, and the magnetic tape is placed at the same angle with respect to the guide dowel 5. range <180'), and each one is wound alternately by two rotating heads.
Each track is formed to record PCM data.

By the way, when recording PCM data, conventionally, data for a unit time (l segment data), which is normally recorded as one track, is recorded directly on the tape.
Since it is recorded as a track, part 1
[If a track's worth of playback data is lost due to dropout, etc., there will be a state where there is no data at all for a period of time equivalent to this one track.
4 hours.

In a so-called error correction circuit, it is possible to correct the error by using the so-called pre-hold type 19 correction method, which interpolates using the data for one previous error correction circuit, but it is possible to correct the error by using the 19 correction method of the so-called pre-hold type, which interpolates using the data for one previous error correction circuit. Since interpolation is performed, signal deterioration is inevitable.

In view of the above points, this invention is designed so that even if one track's worth of data is lost during playback, when the original time-series data is restored during playback, the data can be obtained continuously without any data loss. We would like to provide a system that is strengthened against burst errors, allows advanced methods to be easily used for error correction, and can be modified so that signal deterioration is almost inconspicuous in Modification II/U. That is.

An example of this invention will be described below by converting an audio signal into PCM [
Let's take the case of recording as an example and explain it with reference to Figure V#.

By the way, when a PCM signal is recorded by a rotary head device, as in the case of a conventional rotary head device, for example, there are two rotary heads and the angular interval between them is 180°.
The 4I cut on the tape guide drum is the same 180 on the corners.
, the heads of the 2111 alternately and continuously scan the tape to form tracks continuously without any gaps in time, so the audio P
There is no longer enough time to add redundant data such as parity for CM (l-IK-reduction) correction.5 For this reason, we must use a large amount of buffer memory for signal delay. Furthermore, there is a drawback that signal processing tends to become complicated.

Therefore, in this example, a new rotary head type recording/reproducing apparatus is used, which has been carefully considered to avoid the above-mentioned drawbacks.

Figure #L1 is an example of a rotary head device used in this new device, and this is a case where there are two rotary magnetic heads. In this case, these 2 @ rotating heads (IA) and (IB) are 3
Maintain an angular spacing of 60',=180°.

On the other hand, the magnetic tape (2) lies on the circumferential surface of the tape guide drum (3), and the magnetic tape (2) is smaller than the 180' angle range, for example,
It is made to wrap around the 0° angular range section.

Then, the rotating heads (IA) and (IB) rotate at 3 times per second.
The tape (2) is rotated in the direction shown by the arrow (IsH) in the figure at a rate of 0 rotations, and the tape (2) is run at a predetermined speed in the direction shown by the arrow (5T), and the rotating head (IA) and (I
B), in that one rotation section, the magnetic tape (2)
As shown in FIG. 2, magnetic tracks (4A) and (4B), each diagonal, are alternately formed 5 to record signals. In this case, the head (IA)
The width directions of the caps (IB) and (IB) are different from each other with respect to the direction perpendicular to the scanning direction. In other words, the so-called azimuth angles are made different.

According to the above single-turn head device, two single-turn heads, do (
There is a period (in this example, a period corresponding to an angular range of 9f) in which IA) and (IB) are not in contact with the magnetic tape (2)K. (If redundant data is added to the data in the recording process, the number of buffer circuits can be reduced and the configuration can be simplified.)

Next, this W! using this rotating head device! An example of an i4 recording device and its reproducing device will be described.

FIG. 3 shows an example of a recording system.

The example shown in FIG. 3 is an example in which an audio signal is recorded as a two-channel signal of a right channel and a left channel.

In this case, the rotary magnetic heads (IA) and (IB) are rotated at 4c 30 Hz as described above, and their rotational phases are controlled as follows.

That is, in the control signal generating circuit (9), a reference signal CT of 30H1 obtained based on the master clock signal from the master clock generating circuit (9) is supplied to the phase comparator circuit (8)K. Further, a signal PG from a pulse generator (6) that generates one pulse per rotation of the rotary heads (IA) and (IB) is supplied to this phase comparator circuit (8), from which signal CT and signal PG A voltage corresponding to which phase error is supplied to the rotary head drive 1 drum motor (7)K, so that the phase of the signal CT and the W7A@phase of the 1st rotation head (IA) and < IB) have a predetermined relationship. controlled as follows.

The control signal generating circuit Ql also generates a signal CTo and various control signals as described below based on this i-star clock signal.

Therefore, the phase of the various control signals is the signal C
It is synchronized with the phase of T, that is, the rotational phase of heads (IA) and (IB).

The left channel and right channel audio signals sL and SR are sent to the switch circuit C2 through input terminals 0υ and Q.
3i and the other input mK is supplied. This switch circuit (c) is a 44.1 kHz switching signal 5W (14
(figure) is switched alternately between its one and the other input terminals. Therefore, from this switch circuit (c), as shown in FIG. 4A and B, the switching signal SW
During the period when S is at high level, the left channel signal is
During the period when W is at a low level, the right channel signals are extracted and supplied to the A/D converter (2).

In this A/D converter, one channel is sampled at a sampling frequency of 44.1 kHz. The signal SP from the control signal generation circuit is a number printer signal, and the left and right channel audio signals are each sampled by this signal 8P, and the sampled data is converted into a PCM of, for example, 1 bit per sample. It is converted into a signal So. Figure 4B shows the output signal S(,
"Ot Ll *L2..." each indicates one data word of the audio PCM signal of the left channel, and R.#a1*R1...... indicates the audio PCM signal of the right channel. Each represents one data word.

The output signal So of the A/D converter is written to three RAJIυ, cum, and CIK through the switch circuit (c), but as will be described later, two of the three RAMs are not in the blue writing state. Redundant data is added to the two RAMs that are not in the writing state, or data to which the redundant data is added is read.

Control signal generation - 3 RAJυ from path a groan.

Control signal R for controlling writing of □□□, □□□
W is connected to the switch circuit) through the three RAMG11. C
(It is supplied to the control terminal of L@.Then, switch circuits 4 and (2) are switched in the switching order as shown in the PK diagram of wc4 by the switching signal SWW from the control signal generating circuit -.In other words, at a cycle of 1 second. 3 RAM 9υ～(
) is switched to 0.

Therefore, the three RAMs @υ, aa, and caK sequentially store PCM audio data for a unit time of °C seconds.
As shown in Figures C, D, and E, it will be written in 5. In other words, data group [1] for unit time is stored in RAMCII).
However, the data group [2] for the first time of the RAM @ Kth order, and the data group [3] for the next unit time of RAM (to) K'8 et al. The data group for the period is stored in three RAMs @υ (To) CIKm Next writing number.

Here, the number of t nozzles included within the 6 second period is 1470.
As shown in Figure 4BK, these are 735 words on the left channel audio No. 18 word L--L axis and the right channel/channel audio II-II word R.
~ Accounting 1470 words El with tSS word of Rmas4
l whiten. In this example, data corresponding to a period of 1 second is taken as data for a unit period, and RAMs D to (to) each have a capacity capable of storing 1470 words.

[Three RAMC IIIs are stopped for a unit period of 1 second]
.

O Oa, (to) K The written data has parity P and Q for error correction added to all the data, and is divided into odd data and even data, and the data is divided into odd data and even data, respectively. PatJ for data? (E
PjLTJEQ, A9 f OP and OQ, further EIK
A CRC code for detection is added to each added odd number data and every even number data K.

The time axis is compressed and read from C4rRAM.

Here, the odd-numbered data refers to the odd-numbered data words of the left channel and the right channel among the plurality of data words for the unit period of the experiment, and as shown in FIG. 4B, the data words of the left channel Lh right channel data word IL1゜left channel data word s, right channel data word Rs, 5?
There are a total of 734 data words of left and right channel/channel word pairs with fittas of 1.3.5...733. On the other hand, even data refers to the even data words of the left channel and the right channel among the plurality of data words for this unit period, and the 4th wJ
BK left and right channel word Lot as shown
R@, L! , R-tomi... -... and the fix for 5 to 5 is 0. ! , 4.6...734 word pairs for the left and right channels for a total of 736 data words.

Parity is added to and read from data written in each RAM as follows.

In other words, the control signal generation circuit a controls whether to generate parity for the data for a unit period and add it to it, or to generate parity only for odd data among them and add it to the odd data. A control signal RAO is obtained, which is supplied to the control terminals of the three RAMs (lυ, @, -) through the switch circuit. A signal RER for controlling whether to generate and add data or to sweep out data from three l'LAMc1υ~ (to)
is obtained from the generation circuit a1, and this is the switch circuit (2)
are supplied to the control terminals of the three RAMs (Ill, Country, (To)) through the three RAMs (1υ, 匈, @
The output data is supplied through the switch circuit (2) to a parity addition circuit (C37)K for unit period eclipse data, and is also supplied to a parity and CRC code addition circuit (to) for odd data of the unit period data. Furthermore, the output data of the S@ RAM @υ, □□□, and the like is supplied to the parity and CRC code addition circuit CIK for even data via a switch path. Then, the output data of the additional path On and the branch is transferred to the switch circuit (
The output data of the additional circuit (to) is supplied to the input terminals of three RAM@l, Oa, (to) through the switch circuit (2) and (c). RAM@υ
, a, &10 input ends, and the switch circuits (c), (2), and (to) switch three in the order of 5 as shown in FIG. 4G by the switching signal 8WPOK from the control signal generation circuit. RAM@υ, C1
3, (to) is made, and the switch paths @l (to) and (to) are switched to the three RAMCs 5υ, □, C (Switching for IK is performed.

In this case, when the three RAMs @υ, ea, and t13 are not in the writing state, they are in the writeable state, and data is being output.

Further, the control signal AP (FIG. 4I) of the additional circuit 0'l) is obtained from the control signal generating circuit tA, and this is supplied to the additional circuit Gη. The additional fence is brought into operation.A signal OPC having a polarity opposite to that of this signal AP is obtained from the control signal generation path a, and this signal OPC
is supplied to the additional circuit (to), and the additional circuit (to) is set to 5 so that the additional circuit (to) becomes operational during the period in which it is at a high level, that is, the period in which the signal AP is at the 6-level. Furthermore, the signal gP is 90° out of phase with the signal AP.
c (411J) is obtained from the control signal generation circuit and is supplied to the additional circuit @, and during the period of its high level, this additional circuit becomes operational.

The signal AP is a signal that exactly matches the three RAM @υ, scolding @f) @ switching timing and its one cycle, and this signal AP is a signal that corresponds to the period trail of RAMH, CIJ, and @ Yamasuna, respectively. It has become something like this.

The signal RPC is at a high level for a period of I seconds in the center with a 9G' phase with respect to the signal APK, and is a 1° signal during the session.

The phase of this signal EPC is synchronized with the rotational phase of the heads (IA) and (IB) controlled by the phase sensor, and during the period when this signal EP is at a high level, the heads (IA) and (IB) During a period in which one of the heads scans the tape (2) and is at the -1 level, neither the head (one head) nor the head (IB) come into contact with the tape (2).

From the above, for example, data for a unit period written in RAM (3m)K in period Tl is generated, added and offset to all data in periods Tm and Ts, and parity is added to each of odd and even data in periods Tm and Ts. Addition of generation, etc. and heaving are performed.

That is, in the period TIK, the switch circuit @@(to) is switched to select RAM@υ by the switching signal 5WPOK, and in this RAM 1υ, generation and addition of parity P and Q for all data I, and parity OP for odd data, The mode is set to OQ generation/addition and CRC code generation/addition mode. That is, this period T
In the first half of 8, when the signal AP becomes high level, the additional circuit Gη becomes active, and the parity P and Q for all the data for the short period of RAMGυ are set to the additional circuit C.
17).

It is added to all the data. The data with the parities P and Q added thereto is returned to a predetermined address in the RAM (13) through switches Omoji and Oji and is stored therein. The switch circuit 1 is configured to be switched to the state shown in the figure during the high level period by a signal similar to the signal AP, and to the state opposite to the state shown in the figure during the 1 level period.

Next, period T! In the latter half of the period, the signal AP goes to the m-level, so the signal OPC goes to the high level, and the odd data parity and CRC code generation/addition circuit (2) becomes operational, and the switch circuit goes into operation. The parity OP and OQ are switched to the opposite state from the - state, and parity OP and OQ are applied only to the 5th odd data of the unit time worth of data written in the RAM@l).

Furthermore, a CRC code is generated and added to the data, and the data in the added state is written to a predetermined address of the RAMG (ro) through the switch circuits (b) and (to).

Next, in the period Ts, the switching signal 8WERK switches the switch circuit @- to the RAM @υ,
The RAM@υ is used as a gate for generating and adding parity and CRC codes for start-up or even data. Since the signal EPC is at a low level during the initial period of this period Ts, the additional time wI1. gJ is in a non-operating state, and the control signal RER sends the parity P*Q for all data from RAJllj - parity OP, OQ and CRC for odd data: 2 - odd data to which codes are added during this fractional second period. Read out.

After that, when the signal EPC becomes high level, the addition-connection terminal becomes operational, and even data is read from RAM0U, and the parity EP, EQ, and KCR for this are read out.
A C code is generated in an additional circuit (to).

These are added to the even data, and the added data is written again to a predetermined address in the RAM 6υ via the switch circuit (to). And this even number data is the sediment at the end of this period Ts! Since the signal EP becomes the m-level in a period of 40 seconds, the signal is ejected.

Similarly, in the period T, the data for a unit time written into the odor-C1RAM Parity O about
F, OQ and CRC: z-code generation additions are made. Then, in the period of mountain seconds at the beginning of the next period TI,
Its parity P, Q, OP.

OQ and CRC: Odd data with I-code added is read out, and in the middle of this period T1, parity EP, IQ and CRC codes are generated and added to the even data, and parity P, Q, E.P.

The even data to which the EQ and CRC codes are added is read out in the sandy period at the end of the period T1.

In the period Ts, the data generated in the RAM Odd data with parity OP, OQ and CRC code added to P, Q and odd data is read out, and even data with parity P, Q, EP, EQ and CRC code added is read during the M second period at the end. The hem is laid out.

The codes of the above RAM Qυ, (to), and (c) are as shown in FIG. 4, C, D, and E. Further, the timing of the read data is as shown in FIG. As can be seen from this figure, the odd number data (10) of a data group for a unit time, for example data group [1], is in the 9 second period at the beginning of the period Ts, and the even number data (Ig) is the peak at the end of the period Ts. The odd number data <2?5] of the data group [2] following the data group (1) is set out in the sand period, and the even number data <2? Data (2E
) are respectively read out during the period of the last second. Similarly, data groups [3], [4], [5]
・・・・・・odd number day) (30)(40)C50)
-... and odd number data (3E) (4E) (5E)
. . . is divided into periods of 10 seconds TI and 2 seconds at the beginning and end of either L12. Then, when viewed as a continuous data flow, Each period”1
* 'r2 + '3 The period from the m second period at the end to the mountain sand period at the beginning of the next period T2. 'r3. 'r is a series of data. Therefore, the first half of this series of data is even data, The vk cow is odd number data, and the even number data and odd number data are data from data groups for different unit periods.

Here, the read odd number data and even number data have the following configuration. -1' That is, in the parity and CRC code generation and addition processing, as shown in FIG. 6A, PCM audio data is converted into blocks in units of 8 data words, and , parity words P, Q for all data are added, and when the data word is even data, parity words mV, BQ and CRCW- are added, while when the data word is odd data, parity word OF , OQ and CRC:l-code are added.

In this case, the eight data words that constitute one plotter are R
The read addresses of AM0υ~(g) are controlled and interleaved processing is performed so that the data words are distributed. In this case, one plotter is made up of 8 data words, so as shown in the figure, it is made up of 92 plotters made up of even data and odd data blocks B.about.Bet.

As a result, the odd and even data read from each RAM C(υ~(to)) is supplied to the 2gA rotary heads (IA) and (IB)K through the memory printer.

The rotating heads (IA) and (IB) are as described above:1
The phase of the signal CTK from the control signal generating circuit Ql is nervomed, and the signal EPCf)wx- level is scanned on the tape (2) in a certain period. Therefore, data for each period of m seconds read by tying as shown in FIG.
A) and (IB) [This is exactly the section where tape (2) is scanned, one track each (
4 persons) and (4B) are formed alternately and recorded on tape (2). That is, as shown in 1I21Kl, tracks (4A) and (4B) K have even data (OE) (IE) (2E) of data for a certain unit section in the first half of 70.
) (3E) ...... is recorded, and in the latter half of the track, odd number data (10) (Jio) (30) (4
0)...-- is recorded. therefore,
Data recorded on one track spans two unit sections in terms of time. However, one track Kle
Since the amount of data to be generated consists of odd number data and even number data, this is exactly equal to the data amount for a unit interval.

In this case 1. ) written to each RAMK during a period of
Odd number data and even number data of M data are each recorded in a period of 9 seconds, and the data is compressed on the time axis to 1.

In addition, recording processor? - In the example shown in l56WAA, booter synchronization signal 5 is generated for one plotter's data.
YNC and plotter address data ^D8 are added. Furthermore, preamble signals and postamble signals are added to the blocks recorded as even and odd data from Bo to Kisl, respectively. The preamble signal is a signal for generating a clock for extracting data during reproduction, and the postamble signal is a signal indicating the end of even data or odd data.

In the recording processor, further processing is carried out in which the PCM data is modulated into a signal suitable for recording, for example, a signal such that the @ stream is as small as possible.

Next, reproduction of audio PCM data recorded in this manner will be explained.

FIG. 5 shows an example of the reproduction system, and FIG. 6 shows its timing chart.

In the reproduction system shown in FIG. 5, the control signal generating circuit aυ
30Bgf) (No. 1 SH (Fig. 6B
), phase nervo is applied to the rotating heads (IA) and (IB) K. Control signals during playback obtained from this control signal generation circuit αυ, that is, control signals such as a switching signal for the playback output of the head, and write and indulgence signals for this playback output, are constant with the reference signal SH of 39Bg. There is a phase relationship of 5Kj.

The playback output from the head (1 person) and (IB) is output from the amplifier (
41A) and (41B) to the switch circuit (2). This switch circuit is 30H1 for phase navigation.
According to the signal 8HK, the amplifier (41A) @ and the amplifier (4
1B) side alternately. Therefore, from this switch circuit, a head (I) as shown in FIG.
Five data strings are obtained in which the output of A) and the output of the head (IB) are alternately consecutive.

The data obtained by this switch circuit (6) is supplied to the digital signal restoration circuit and restored to a digital signal, and the error detection and RAM write control signal generation circuit (4)
41. From this error detection and RAM write control signal generation circuit 2, the error-detected data SD is obtained, and the write address and write tie-building signal RWP to the three RAM C) can get.

The switch circuit (c) writes the error-detected data 8D from the circuit to the RAM 6υ, or writes the error-corrected data 8D from the error correction circuit to the odd-numbered data. This is a switch to control whether data is written. First, the import of data sD will be explained.

Switch (b) path - is control signal generation waste
It is switched by the switching signal WO6c for switching the writing and correction modes in RAM 5υ to fAK. That is, this switching signal w.

As shown in Figure 6JK, 5 is the @OHi signal, and the first half of its cycle, the high level period PW, is the period in which the reproduction output is obtained from the head (IA) or (IB). During the second half of the low-level Yamasuna period, the PC cannot obtain playback output from both heads (IA) and (IB).In other words, both heads (IA) and (IB) cannot output tape (2)K. There is a period of no face-to-face contact. During the period PW when the signal WO is at a high level, the switch circuit (c) is switched to the state shown in the diagram, and during the period PC when the signal WO is at a low level, the switch circuit (-) is switched to the state opposite to the state shown in the diagram. K has been used.

In addition, the write address and write timing signal RWP from the enclosure are sent to the RA via the switch path and -.
M 6υ−1 is supplied to the control terminal. In addition, the data 8D for which error detection has been output from the circuit (goods) through the switch circuit is transferred to three RAMs 5 through the switch circuit.
It is designed to be supplied to the input terminals of the υ wheel. The data extracted from the RAM 6]) is supplied to the input terminal of the odd-numbered data error correction circuit via the switch circuit (3). The output signal of this odd data error correction circuit is supplied to the other input terminal of the switch circuit.

Then, by the control signal swwo from the control signal generating circuit Ql, the switch circuit @64@ controls the three RAMs 5116263 every second in the order of 5 as shown in FIG. 6GK.
are switched sequentially.

In this case, the three RAM6υ linkages by the signal swwo -
The switching timing is approximately at the center of the period PW in which the signal WO is at a high level.

Further, a signal co for controlling the correction peak for odd data is obtained from the control signal generation circuit a1), and this signal is supplied to the other input terminal of the switch circuit. The signal is supplied to the control terminals of three RAM5υ5253 through the control terminal. Then, the switch circuit is switched in synchronization with the switch circuit - by the signal WO)C.

Therefore, the period PW during which the signal WO is at high level is
The three RAMs 6υ~ are at the write peak, and during this period PW, the switching signal ``5WOK'' causes the switch circuits 61 and 61 to write to RAM5υ and RAJtJ, respectively.

Each period TA * "B p "C') The first 100 second period Poha, the second half of the period Pw (the head tape (
2) corresponds to the end of the above scanning period), and this period P
As is clear from Fig. 6C and J at 4h, the endogenous head output is odd data (10)? (2◇)
, ($0)... is obtained. Shitakatsu [,
During this period PO, each RAM61)6a63 has an odd 1
[f-p o5) cz center> (5a) -----A is written to a predetermined address using the write address from the circuit <44) and the tie-in number RWP.

On the other hand, the mountain sand period PE for each period Tle ``l p ``C') H is the first half period of the period PW (corresponding to the first half of the scanning period on the tape (2) of the head), and this period PgK is lK6 As is clear from Figures C and J, the playback head output is even data (IE) and (RK).
.

(3E)... is obtained. Therefore, during this period, even data (IE
) s (2”) ) (3E) --- Signal from furnace circuit RWP K IIIJ m1ll is written.

During each period when the signal WO is at m-level Tm
- and (c) are switched to the opposite state to the state shown in the figure, so the corrected data from the correction circuit - is transferred to each RAM.
It becomes state 11 which is written in 5υ6263. In other words, it becomes an odd data correction mode. Note that the control signal OC is supplied from the control signal generation circuit (11J) to the odd data correction terminal.This signal OC is connected to the signal W.
O is a signal of reverse Ii nature, and the correction circuit (46) is enabled to operate during its high level period (this is the period PC).

Once, the switch circuit 61- was triggered by the signal 5WWOK.
(g) is switched and each fLAM61) 53- is selected in the period PC of the period Tmu e "l e "C, from the control signal cg6c [, each R
AJt9-The odd number data read from 1 is corrected by the circuit-
The parities OP and OQ are used to correct the detected data, and the corrected data is returned to the original RAM 116 via the switch circuits - and -.

Next, error correction for even-numbered data written in the last period of each period Tm*"l*"C and correction for all data are performed in the following 5.

That is, the control signal A for that purpose is sent from the control signal generation circuit I to the three R circuits through the switch circuit.
It is supplied to the control terminals of AM5111... Also 3 R
Output data from AM611Hu is routed to switch r57.
) is supplied to the correction circuit for even-numbered data and also to the correction circuit for unit interval segmented data. Then, the output of one correction circuit for this even data and the output signal of the corrector w1 (41S) for all data are switched by a switch circuit @, and the output is supplied to the input terminal of three uAM61 through the switch circuit 6361. Ru. And the switch times ll6f9571 and (to) are Zunto■-
Switching from the signal generation circuit base (14#8WgA
Therefore, three RAM5υ in the order shown in Figure 6HK.
Switched to 6a61.

Further, the control signal EC (K in Fig. 6) is supplied from the control signal generation circuit Ql to the correction circuit η for even number data, and the correction circuit operates during the period when the control signal EC is at a high level. be done. Further, the correction circuit is supplied with a signal AC which is inversely different from the signal ECK, and is set so that the correction circuit is in an operable state during the period when the signal AC is at a high level. This signal gC has a period Tm, T
Otori, TCf) It is a signal that is high level in the first half and - level in the second half. Therefore, correction-
The connecting terminal η becomes operational during the first 1 second period of the period Tl=TB+''C, while the correction circuit η becomes operational during the period Tl.

Tl, TCf) becomes operational during the latter half of the mountain sand period.

The switch circuit - is switched by a signal having the same phase as the signal EC, and during its high level period, it is switched to the state shown in the figure, and during its low level period, it is switched to the state 11iK, which is the opposite of the state shown in the figure.

Therefore, as is clear from FIG.
In the period TI during which the RAM 51 is selected by
During the first half of this period Ti, the even data extracted from the CRAM6υ by the control signal CEm from the circuit qυ is sent to the 4AII data correction circuit (471 and all data correction circuits) through the switch circuit 67). In the first half of this period, the correction circuit for even data is operational, so the parity EP and EQ for even data are used to correct the even data. The corrected data is sent to the RAM 5 through the switch paths and.
It is written to the original predetermined address of υQ61. Then, when this period Tgf)Wk reaches half, the correction circuit for all data becomes operational, so parity P and Q are used to correct data errors for all data corresponding to a unit period. Then, the error-corrected data is passed through the switch circuits - and - to RA) Jlt3.
) is written to a predetermined address.

Similarly, in period TC, correction using parity EP and EQ is made for even data among the data written to the RAM wheel.
(Correction of all the data using Ritei P and Q.

-paths @η and -sense respectively and are written to the original address of RAMII. Furthermore, period TAK oi”
Ckt RAM (vlc) Correction of the even number data of the written data by parity BP and gQK and correction of the warehouse data by parity P%QK are performed in the circuit and wI, respectively, and the corrected data is transferred to the RAM. It is written.

From the above, the data written to the RAM 6t... during the period "A*"le"C is 'After the audience seconds have passed after the respective writing period,
The data written in RAM5υ-H11K is PCM data in which all the data that can be corrected within the correcting capability has been corrected.

The written and corrected data is read out in a period of 1 second after the end of writing. In other words, the threading control signal RR from the control signal generation circuit aυ is sent to the switch circuit -
It is supplied to the control terminal of the RAM reference 16461 through.

RAJt again! 1 (b) - output signal is switch circuit -
VA is also supplied to the modified wA path. These switch circuits and circuits are switched to the three RAMs 6c in the order shown in FIG. 6IK by the switching signal SWRK from the control signal generating circuit a. That is, even data and odd data written in RAJI during period Tm are read out during period TC, and during period Tm.
The data written to RAM (to) in period TA
The data read out in the period TC and written into the CRAM- in the period TC becomes 5 as it is read out in the period TB. In this case, the even-numbered and odd-numbered data of each unit interval function are alternately extracted by the address # & field to form the original time series, and the data for the unit time is the original time axis of 0 seconds. The data is expanded and read out as shown in Figure LK. The signal generated in this way is repaired through the switch circuit &υ! 1 circuit, and correction ρ1 is applied to the data that cannot be completely corrected. The error correction circuit outputs kt D/A:=r and is supplied to the error correction circuit. Each sample of the PCM signal returned to the analog signal in the D/A converter II is converted into a signal at the time of recording by the switch circuit. A signal with the same frequency as SW (44,1
kHz), the left channel audio signal 8L is output through the amplifier (65L).
However, the right channel audio (ivsl or output terminals (6@L) and (66
R) K is taken out.

According to the apparatus of the present invention as described above, audio data for a unit time corresponding to one track is divided into even-numbered data and odd-numbered data and recorded over two tracks. Therefore, data for a unit time of the PCM signal is scattered over two tracks. According to the present invention, even if one track's worth of data is missing and cannot be obtained during C playback, the preceding and succeeding tracks can be played back. Alternatively, since either odd-numbered data is always recorded on the previous or next track, there will be no such situation where the data is i in terms of information, but it is all missing.Therefore, for example, In the repair circuit, this TK missing data is used to interpolate the data for that cabinet. In other words, the even-numbered or odd-numbered data is used to calculate the odd-numbered or even-numbered H using the average value review method. Since it is possible to interpolate the data word of
Good data can be obtained. Moreover, there is an effect that the configuration for this purpose can be made very easily.

Also, when you start recording continuously from an already recorded part, only the even-numbered or odd-numbered data of the new 1-day data remains at the joint. Therefore, it is possible to perform interpolation processing for signal processing at joints using the same method as the error correction described above, and it is possible to realize a highly effective method that can smoothly connect signal joints. There is also the advantage of gender.

Furthermore, in this invention, C has even number (odd) data recorded in the first half of one track, and the rear #PK is an odd number (even number).
Since the data is recorded, the conventional interleave is 1, and it is divided into two. However, as is clear from Fig. 41EI and Fig. 6, the time required for error correction is extremely long. By doing so, you can greatly improve your correction abilities.

Furthermore, as mentioned above, when winding the tape around the guide driver 5, the angle is taken as the number of rotating heads, and the number of rotating heads is set as N.The installation of the 360° head is performed by making the angular interval smaller than 1" for recording and playback. time, head (l^) and (
There is a period when the IB) is not in contact with the tape (2)K, and by utilizing this period, redundant data such as parity and CRC codes can be easily added to the data of each channel during recording and during playback. Since it is possible to correct errors, it takes less time to add redundant data during recording and to correct art during playback, as in the case of conventional tape winding at the corners and head mounting at corner intervals. This has the advantage that there is no need to perform complex signal processing or use a large amount of delay buffers to create margin.

However, according to the present invention, error correction can take a very long time to correct all data, even data, and odd data. This is not corrected, and with head installation like this, tape wrapping is not limited to the case where the corner is made smaller than the corner spacing, and head type attachment is not limited to the case where the corner spacing and tape wrapping are the same. Even in such cases, ample correction time can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining an example of a rotary head scissors used in the present invention, FIG.
FIG. 5 shows a system diagram of an example of a reproduction system, and FIG. 6 shows a timing chart for explaining the same. (IA) and (IB) are rotating heads, (2) is magnetic tape, (3) is guide drum, C1υ (to) (to) is RAM
, (b) (to) (to) is a parity or CRC addition circuit.

Claims (1)

[Claims] A device for recording PCM data by forming diagonal tracks on a recording medium using a rotating head.
The above-mentioned data is divided into even-numbered data and odd-numbered data for each unit time of data, and redundant data is added to each of the above-mentioned even-numbered data and the above-mentioned odd-numbered data, and this redundant data is added. PCM data in which the even-numbered data and the odd-numbered data are recorded on separate adjacent tracks, and the data in the first half and the data in the second half of the same track are data for the unit time that are different from each other. recording device.