JPH0377562B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION When recording and reproducing audio signals, high-quality recording and reproducing can be achieved by converting the audio signals into PCM.

There are two methods for converting audio signals into PCM and recording and reproducing them on a magnetic tape: methods using a fixed head and methods using a rotating head. In the method using rotating heads, if a plurality of rotating heads, for example two, are used, the rotating heads are installed at an angular interval of approximately 360°/2 = 180°, and the magnetic tape is placed within the same angular range relative to the guide drum. The two rotating heads alternately form one track at a time to record audio PCM signals.

In this case, since tracks are formed continuously without any temporal space, there is no longer enough time to add redundant data such as parity for error correction to the audio PCM signal. For example, a buffer for signal delay is used. And since I don't have the time,
The drawback is that signal processing tends to be complicated.

Therefore, a new device that does not have the above-mentioned drawbacks is being considered as a recording and reproducing device for PCM audio signals using the rotary head method.

FIG. 1 shows an example of a rotary head device used in this new device, in which there are two rotary magnetic heads. In this case, the two rotating heads 1A and 1B are arranged with an angular spacing of 360°/2=180°. On the other hand, the magnetic tape 2 is wound around the circumferential surface of the tape guide drum 3 over an angular range of less than 180°, for example 90°. Then, the rotary heads 1A and 1B are rotated at a rate of 30 revolutions per second in the direction shown by the arrow 5H, and the tape 2 is transferred at a predetermined speed in the direction shown by the arrow 5T. One diagonal magnetic track 4A, 4B as shown in FIG. 2 is formed on the magnetic disk 2, and signals are recorded thereon. In this case, the width directions of the gaps of the heads 1A and 1B are set in different directions with respect to the direction orthogonal to the scanning direction. In other words, the so-called azimuth angles are made different.

According to the above rotary head device, there occurs a period (in this example, a period corresponding to an angular range of 90°) in which the two rotary heads 1A and 1B do not come into contact with the magnetic tape. PCM using
By adding redundant data such as parity to data, the number of buffer circuits in the recording apparatus can be reduced.

Next, some embodiments of a recording device and a reproducing device thereof using this rotary head device will be described.

FIG. 3 shows an example of a recording system.

The example shown in FIG. 3 is an example in which an audio signal is recorded as a two-channel signal, a right channel and a left channel.

That is, in FIG. 3, the left channel audio signal S _L is supplied to one input terminal of the switch circuit 13 through the input terminal 11, and the right channel audio signal S _R is supplied to the other input terminal of the switch circuit 13 through the input terminal 12. Supplied to the terminal. This switch circuit 13 is alternately switched by a switching signal SW from a control signal generating circuit 14, and its output is supplied to an A/D converter 15. The control signal generating circuit 14 generates various control signals as described below in addition to the signal SW based on the master clock signal from the master clock generating circuit 10.

The switching signal SW of the switch circuit 13 has the same frequency as the sampling frequency in the A/D converter, for example 44.1 kHz, and is a rectangular wave signal with a duty factor of 50% as shown in FIG. As shown in FIG. 2, the switch circuit 13 is switched so that when this signal SW is at a high level, the left channel audio signal is selected, and when this signal SW is at a low level, the right channel audio signal is selected.

In the A/D converter 15, each channel is sampled at a sampling frequency of 44.1 kHz. The signal SP from the control signal generation circuit 14 is this sampling signal, and the audio signals of the left channel and the right channel are each sampled by this signal SP, and the sampled data is divided into, for example, 16 bits per word. is converted into a PCM signal _SO . FIG. 4B shows the output signal S _O of this A/D converter, L ₀ , L ₁ , L ₂ . . . indicate one word each of the audio PCM signal of the left channel, and R ₀ , R ₁ , R ₂ ... each indicates one word of the right channel audio PCM signal.

The output signal S _O of the A/D converter 15 is supplied via a switch circuit 16 to the input terminals of RAMs 17 and 18 for redundant data addition and interleaving processing. The switch circuit 16 is switched by a 30 Hz signal RSW (FIG. 4E) from the control signal generating circuit 14 which is synchronized with the rotation of the heads 1A and 1B.

That is, phase servo is applied to the rotating heads 1A and 1B in the following manner.

In other words, 30Hz from the control signal generation circuit 14
A signal S _S is obtained and supplied to the phase comparator circuit 19, and a signal PG from the pulse generator 20 which obtains one pulse per revolution of the heads 1A and 1B is supplied to the phase comparator circuit 19. The phases of both are compared, and the comparison error output is sent to head 1A.
and 1B, and the rotating heads 1A and 1B are servoed so as to be synchronized with the phase of the signal RSW, which has a constant phase relationship with the signal S _S. In this case, the second half of period T _A (corresponding to 180° angular range) is 1/120 s (corresponding to 90° angular range) at 1/60 s when signal RSW is at low level.
The servo is set so that the head 1A scans the tape 2, and the head 1B scans the tape 2 during the 1/120 second period in the latter half of the 1/60 second period _TB when the signal RSW is at high level. It is taking place.

The aforementioned switch circuit 16 is switched between one output terminal and the other output terminal by this signal RSW. That is, during the 1/60 second period T _A when the signal RSW is at a low level, the signal S _O is supplied to the data input terminal of the RAM 18, and during the 1/60 second period T _B when the signal RSW is at a high level, the signal S _O is supplied to the RAM 17.

On the other hand, from the control signal generation circuit 14
Write control signal RW of RAM17 and 18,
The read control signal RR is obtained and these control signals
RW and RR are selectively supplied to control terminals of RAMs 17 and 18 through switch circuits 22 and 23. Since the switch circuits 22 and 23 are also switched by the 30 Hz signal RSW, like the switch circuit 16, they are switched to the state shown in the diagram during the period T _B and to the state opposite to the state shown in the diagram during the period _TA . Therefore, in the period T _A , the signal S _O is written to the RMA 18 by the write control signal RW for a period of 1/60 second, and in the period T _B , the signal S _O is written to the RAM by the write control signal RW.
17 for the period of 1/60 second.

In this way, the right channel and left channel audio signal data for a period of 1/60 seconds are alternately written into the RAMs 17 and 18. Here, the number of samples included within a period of 1/60 seconds is 1470. That is, as shown in FIG. 4B, it is the sum of 735 words from words L ₀ to _{L 734} of the left channel audio signal and 735 words from words R ₀ to R ₇₃₄ of the right channel audio signal.
It is 1470 words.

In this way, it was written to RAM17 and 18.
For PCM data, heads 1A and 1B are on tape 2.
, respectively, periods T _A and
Parity and CRC in the first half of T _B
A (Cyclic Redundancy Check) code is generated and added, and the PCM data with these redundant data added is recorded on the tape 2 by the heads 1A and 1B in the latter half of periods T _A and T _B , respectively.

That is, the output signals of the RAMs 17 and 18 are selectively supplied to the parity and CRC code generation/addition circuit 25 via the switch circuit 24. And this parity and CRC code generation additional circuit 2
The output signal of 5 is sent to the RAM via the switch circuit 26.
17 and 18. Switch circuits 24 and 26 are also switched in synchronization with switch circuits 16, 22 and 23 by a 30 Hz signal RSW. and control signal generation circuit 14
Additional parity and CRC code generation circuit 25
and periods T _A and T _B , respectively, as shown in Figure 4F.
A 60Hz control signal CP that is at a high level is supplied for the first half of 1/120 seconds, and while this signal CP is at a high level, parity data and a CRC code are generated for the input PCM data. ,
It is done in such a way that it is added. In other words, the data written in the RAM 18 during the period T _A is transferred to the switch circuits 23, 24 and 2 during the period T _B.
6 is in the state shown in the figure, data is transferred from the RAM 18 through the switch circuit 24 to parity and
The signal is supplied to the CRC code generation/addition circuit 25. In this circuit 25, since the signal CP is at a high level during the first half of the period T _B , the parity and
A CRC code is generated, its parity and CRC code are added to the input data, and the added data is sent to the RAM via the switch circuit 26.
18 will be stored again at the original address. The same goes for the RAM 17, and the data stored in this RAM 17 in period T _B will be used for parity and CRC in the first half of the next period T _A.
In the code generation addition circuit 25, parity and
A CRC code is generated and appended to the data.
The data is returned to the predetermined address in the RAM 17 and stored again.

In this process of generating and adding parity and CRC codes, the PCM data is divided into blocks of 6 words as shown on the right side of FIG. P, Q and CRC codes are generated and appended. In this case, as is clear from the figure, these 6 words of data are 1/60 second worth of PCM data (1
segment data).

Parity and CRC are applied to the audio PCM data written to RAM17 and RAM18 in this way.
The signal with the code added is read out from the RAM 17 during the 1/120 second period when the head 1A is in contact with the tape 2 in the second half of the period T _A (the fourth
(see Figure G) is supplied to the head 1A through the recording processor 27, where it is recorded on the tape 2 by forming one track 4A. On the other hand, RAM1
From 8 onwards, head 1B in the second half of period T _B is tape 2.
The data is read out during a period of 1/120 second (see FIG. 4H), is supplied to the head 1B through the recording processor 27, and is recorded on the tape 2 forming one track 4B.

In this case, data for two channels of 1/60 seconds are each recorded in a period of 1/120 seconds, and the time axis of the data is compressed to approximately 1/2.

Note that the 1/120 second period in the first half of each period T _A and T _B is also recorded in heads 1A and 1 through the recording processor 27.
RAM17 and 18 data are supplied to B, but
During this period, heads 1A and 1B both have tape 2 on them.
Since this is the period when the circuit 25 is not in contact with the circuit 25, nothing is recorded.
Only the processing of generating and adding a CRC code is performed.

In the recording processor 27, a block synchronization signal SYNC and block address data ADS are added to one block of data as shown on the right side of FIG. 4B. Furthermore, a preamble signal and a postamble signal are added to one segment of data recorded as one track of 1/60 seconds as described later. Here, since one block is 6 words, the number of blocks in the data of one segment is 1470 (words) ÷ 6.
=245. Therefore, the data read in a period of 1/120 seconds is 245 blocks from the first block B ₀ to the last block B ₂₄₄ , as shown in Figure 4, and for these 245 blocks, A preamble signal used to generate a clock for extracting data during playback and a postamble signal indicating the end of one track's worth of data are added to the beginning and end of each of the 245 blocks, respectively, as shown in the figure. has been done.

In the recording processor 27, the PCM
Processing is also carried out in which the data is modulated into a signal suitable for recording, for example a signal with as little direct current as possible.

The operations of the RAMs 17 and 18 described above are shown in FIGS. 4C and 4D, respectively.

Next, let's explain how to play back the PCM audio signal recorded in this way.

FIG. 5 shows an example of the reproduction system. Further, FIGS. 4G to 4M are time charts for use in explaining the reproduction system.

During this reproduction, as well as during recording, the heads 1A and 1B are rotated in synchronization with the 30Hz S _SP obtained based on the signal from the master clock generation circuit 31 from the control signal generation circuit 30. controlled. That is, 1 of the motor 21
Pulse generator 20 that generates one pulse per rotation
The 30 Hz output signal PG from the control signal generating circuit 30 is supplied to the phase comparison circuit 32, and this signal and the 30 Hz signal S _SP from the control signal generation circuit 30 are phase-compared, and the motor 21 is phase-controlled by the phase comparison output. . In this case, for data processing during playback,
RAM40 and 41 30Hz switching signal RSW _P (4th
Figure L) (which is obtained from the control signal generation circuit 30) is at a high level for a period of 1/60 seconds.
During the first 1/120 second period of T _C and the low level 1/60 second period T _D , head 1A is
and 1B are controlled so that they are in contact with tape 2.

That is, the reproduced signal is obtained from the head 1A during the first half of the period T _C as shown in FIG.
A reproduced signal is obtained during the first half of T _D.
The reproduction head outputs thus obtained are supplied to one and the other input terminals of the switch circuit 34 through amplifiers 33A and 33B, respectively. This switch circuit 34 is switched by a 30 Hz signal SH (Fig. 4 I), and during its high level period, it is in the state shown in the figure, that is, the state in which the output signal of the amplifier 33A is selected, and during its low level period, it is in the state shown in the figure. Amplifier 33B
The state is alternately switched to select the output.
The rising and falling points, which are the switching points of the head output switching signal SH, are not limited to the example shown in the figure, but may be any point in time as long as the heads 1A and 1B are not in contact with the tape 2. .

In this way, a signal is obtained from the switch circuit 34 in which the outputs of the heads 1A and 1B are alternately and consecutively arranged, and this signal is transmitted to the digital signal restoration circuit 34.
5, it is returned to a digital signal of "0" and "1", and is supplied to the error detection and RAM write control signal generation circuit 36.

In this circuit 36, parities P, Q and
The CRC code is used to detect errors, and the write address and write timing signal _RWP for the two RAMs 40 and 41 are generated based on address data for each block.

The error-detected PCM data is stored in two RAMs.
At 40 and 41, data is written in the first half of periods T _C and T _D , respectively, and error correction is performed in the second half. That is, the switch circuit 38 is used to switch between the writing period and the error correction period, and the signal from the control signal generating circuit 30 is at a high level for the first half of 1/120 seconds of the periods T _C and T _D.
It is switched by the 60Hz signal WC (M in Figure 4), which is at a low level during the latter half of 1/120 seconds. That is, the switch circuit 38 is switched to the circuit 36 side during the high level period of the signal WC, and to the output end side of the error correction circuit 37 during the low level period. The output of this switch circuit 38 is selectively input to RAMs 40 and 41 via a switch circuit 39.

On the other hand, the write address and write timing signal _RWP from the circuit 36 are selectively supplied to these RAMs 40 and 41 via a switch circuit 42. Also, from the control signal generation circuit 30
A read control signal _RRP for the RAMs 40 and 41 is obtained, and this read control signal _RRP is selectively supplied to the RAMs 40 and 41 by a switch circuit 43. The output signals of the RAMs 40 and 41 are selectively transmitted to the correction circuit 37 by the switch circuit 44.
is supplied to the input terminal of the switch circuit 4.
5 is selectively supplied to a modification circuit 46.
And these switch circuits 39, 42, 43, 4
4 and 45 are switched by the aforementioned 30Hz switching signal RSW _P. That is, in this case, the switch circuits 39, 42, 43, 44, 45
During the period _TC when the signal RSW _P is at a high level, the state shown in the figure is switched, and during the period _TD when the signal RSW _P is at a low level, the state is switched to the state opposite to the state shown in the figure.

Therefore, the output signal of head 1A is output to RAM during the first half of period T _C after error detection.
40 is written to a predetermined address using the write address and write timing signal from the circuit 36. Then, in the second half of period T _C ,
The switch circuit 38 changes to the correction circuit 3 by the signal WC.
The output of step 7 is now written to the RAM 40. At this time, the switch circuit 44 is in a state where the output of the RAM 40 is supplied to the correction circuit 37, and the error-detected data is corrected in the correction circuit 37 using the parity P, Q and CRC codes. The corrected data is then written to the RAM 40 again. Similarly, in the RAM 41, data is written in the first half of the period _TD , and in the second half, the data is corrected and the corrected data is written into the RAM 41 again.

The corrected reproduced data written in the RAMs 40 and 41 is expanded twice by the read control signal from the control signal generating circuit 30 and read out. That is, the switch circuit 43 uses the signal RSW _P to switch the RAM 41 in the period T _C.
On the other hand, during the period T _D , the RAM is switched to the RAM 40 side, so that the RAM which is not in the write state is always in the read state, and in the period T _C , the RAM 4 is switched to the RAM 40 side.
1, data is read from the RAM 40 during the period _TD .

Note that the data words that were dispersed within one segment due to the interleaving process during recording are returned to the original arrangement by controlling, for example, the write address to RAM 40 and 41 during playback. data word. Moreover, the words of the left channel and the words of the right channel are alternately continuous.

The read data is selectively switched by a switch circuit 45 and supplied to a modification circuit 46, and the data that cannot be completely error corrected is corrected in this modification circuit 46. This modification is
For example, a pre-hold technique is used.

The output of the modification circuit 46 is data of the left and right channels appearing alternately for each word, and this is returned to an analog signal by the D/A converter 47. This signal returned to an analog signal is supplied to a switch circuit 48, and this switch circuit 48 generates a switching signal SW similar to the switching signal SW during recording.
The output terminals of the _amplifiers 49A and 4
The left channel audio signal and the right channel audio signal are respectively reproduced to the output ends 50A and 50B through the output terminals 9B and 9B, respectively.

A time chart of the operating states of the RAMs 40 and 41 during the above reproduction is shown in FIGS. 4J and 4K.

As described above, the audio signals for the two left and right channels are converted into PCM, and recording and reproduction are performed with the left and right channels mixed on each track.

In this case, during recording, there is a section where heads 1A and 1B do not come into contact with the tape, and by using this section, redundant data such as parity and CRC codes are added to the data of each channel. Therefore, it has the great advantage of not requiring a large number of delay buffer circuits as in the conventional case.

Furthermore, the above device is a device that converts audio signals into PCM and records them, and the sampling frequency thereof should be 40kHz or higher, assuming that the highest human audible frequency is 20kHz, and one word as in the example above. Even if it is a 16-bit PCM signal, the recording rate will be about 3 Mbits at most for two channels. Therefore, when recording signals on a tape using a rotating head, it is possible to use a tape narrower than the tape used in a VTR, considering the recording wavelength that can be effectively recorded and reproduced. Therefore, it has the advantage that the tape cassette can be made smaller.

Further, as can be easily seen from FIG. 1, in the case of the present invention, the wrapping angle of the tape 2 to the drum 3 is 180° or less, and since the wrapping angle is small, the tape is not rolled from the tape cassette like a VTR. The tape can be easily wound around a drum by a predetermined angle by, for example, providing a recess corresponding to a winding angle in the cassette half and bringing the drum into the recess without loading the tape onto a drawer drum.

In addition, since the tape width can be narrow and the bit rate of the recorded signal is low, when the tape is wound diagonally around the drum, the inclination of the tape with respect to the direction of rotation of the head can be increased, so the diameter of the rotating head drum can be reduced. Can be small. In experiments, the rotating head drum could be made approximately 3 cm.

From the above, the present invention has the remarkable effect that it can be made into a very small device, for example, a portable tape recorder.

By the way, in the above example, the right channel signal and left channel signal are recorded in a mixed state on one track, so when re-recording only the right channel or only the left channel during after-recording, etc. cause inconvenience.

The present invention aims to provide a novel device as described above, which eliminates the above-mentioned drawbacks.

That is, in the present invention, in order to eliminate the above-mentioned drawbacks, signals of a plurality of channels are recorded by forming one track independently for each channel.

An example of this invention will be explained below.

FIG. 6 shows a time chart using an example of the apparatus of the present invention. The recording device and its playback device in this case are almost the same as those shown in Figures 3 and 5, except that the recording system RAM1
The frequency of the switching signal RSW for switching the operating states of 7 and 18 is set to 15 Hz, and switch circuits 39, 42, 43, 44 are used in the reproduction system.
And the switching signal RSW _P that switches between 45 and 45 is also 15
Hz.

Therefore, referring to Figures 3 and 5 below,
The recording operation and reproduction operation will be explained.

That is, even in this case, the left channel signal S _L and right channel signal S _R through the input terminals 11 and 12 are 44.1kHz in the switch circuit 13.
The data stored in the RAMs 17 and 18 is selectively switched by the switching signal SW (FIG. 6A) and supplied to the A/D converter 15. However, the data stored in the RAMs 17 and 18 is controlled by the switch circuit 16 using the 15Hz signal RSW' (FIG. 6A). Figure 6 E)
Since it is switched by , it becomes 1/30 second. In other words, this is twice as large as in the previous example. Therefore
The number of data written to RAM 17 and 18 is 1470 words from left channel words L ₀ to L ₁₄₆₉ ,
The right channel has 1470 words R ₀ to R ₁₄₆₉ , for a total of 2940 words. The data written in RAM17 and RAM18 respectively is transferred to the switch circuit 2.
Control signals 2, 23, 24, and 26 are similarly switched by a 15Hz signal and are also supplied to the parity and CRC code generation additional circuit 25.
Since CP' (FIG. 6F) is a 60Hz signal and is the same as the previous example, during the period T _A ' of 1/30 seconds when the signal RSW' is low level, RAM1
8, during the 1/30 second period T _B ' when the signal RSW' is high level, 1/30 second worth of data is written to the RAM 17, and in each period T _A ' and T _B ' In the RAM that is not in the writing state, the periods T _A ′ and
In the 1/60 second period P _A in the first half of T _B ′, the first half 1/60 second period P A
During a period of 120 seconds (signal CP' is at high level), parity and CRC codes are generated and added only to every other left channel data word; signal
CP' is at a low level), the left channel data to which this parity and CRC code are added is read, and since this read period is equal to the period in which head 1A scans tape 2, this read The left channel data is recorded by head 1A forming track 4A (see FIG. 6G).

Similarly, in the 1/60 second period P _B in the latter half of periods T _A ′ and T _B ′, parity and CRC codes are applied to the remaining right channel data every other word in the first half period. The right channel data is read out in the latter half of the period, and since this period is equal to the period during which head 1B scans the tape 2, the read right channel data is read out from head 1.
B is recorded forming track 4B (see FIG. 6H).

In this way, only the left channel or right channel data is recorded on each of the tracks 4A and 4B. The data of the right channel and the left channel can be stored, for example, in the same way as in the previous example _.
245 blocks from (L) to B ₂₄₄ (L), and the right channel block B ₀ (R) to
There are 245 blocks up to _B244 (R), and in terms of the amount of data, the amount of data recorded on each track is one segment, which is exactly the same as in the previous example.

The data thus recorded is reproduced in the following manner using a device similar to that shown in FIG. In other words, the output from each head 1A and 1B is only the left channel from head 1A, and only the left channel from head 1A.
From B, only the right channel is obtained as shown in FIGS. 6G and H. These signals are then alternately switched by the switch circuit 34 by the switching signal SH (FIG. 6 I), so that the left, right, left, right, and left and right channels are alternately changed into data. The signal is converted into a column signal and supplied to a digital signal restoration circuit 35, where the digital signal is restored.

In this case, switches 39, 42, 43,
44 and 45 are caused by the 15Hz signal RSW _P ' (Fig. 6L), and the period of 1/30 seconds is its high level.
T _C ' is switched to the state shown in the figure, and its low level 1/30 second period T _D ' is switched to the state opposite to the state shown in the figure. Therefore, the left channel data and right channel data are stored in the RAMs 40 and 41 for a period as shown in FIG. 6 J and K.
It is written at T _C ′ and T _D ′, but
In this case, the switch circuit 38 is switched by a signal WC' as shown in _{FIG .} ' During the first half of 1/60 seconds, the left channel data is written to RAM 40 or 41 during the first half of 1/120 seconds, and the left channel data is written to RAM 40 or 41 during the second half of 1/120 seconds. Error correction of channel data is performed, and on the other hand, in the latter 1/60 second period of periods T _C ′ and T _D ′, the right channel data RAM 40 or 4 is corrected in the first 1/120 second period.
1 is written, and in the latter half of the period of 1/120 seconds, error correction of the data of the right channel is performed.

In this way, the data of the left channel and the right channel are taken into the RAMs 40 and 41, and the error-corrected data is stored for the subsequent 1/30 second period.
At T _D ' and T _C ', the signal is read out by the read control signal from the control signal generation circuit 30, error corrected by the correction circuit 46, converted back to an analog signal by the D/A converter 47, and sent to the switch. The circuit 48 separates the right channel signal and the left channel signal, and the amplifier 4
Output ends 50A and 50B via 9A and 49B
The left channel signal S _L and the right channel signal S _R are respectively taken out.

According to the example shown in Fig. 6, the right channel signal and the left channel signal are each recorded on separate tracks, and it is easy to rerecord only the left channel or right channel audio signal. .

In this example, heads 1A and 1B are also used, respectively.
Since the 1/120 second period during which the tape 2 is not in contact with the tape 2 is used to generate and add the CRC code and parity, the number of buffer circuits is reduced and the configuration is simplified.

In this way, according to the example in Figure 6, the left channel and right channel signals can be recorded on separate tracks, but in this example, the RAM
The capacity is twice as large as that in the example shown in FIG. This is because, in the example shown in Figure 6, the data stored in each RAM is for 2 segments, but the 4th
This is because in the case of the example shown in the figure, one segment is enough. Therefore, in the case of the example shown in FIG. 6, the cost increases and there is a disadvantage in terms of power consumption.

In addition, in the case of the example shown in Fig. 6, if data for one track is missing for some reason, correct data is also discarded when the correction circuit uses a pre-hold method to correct it. be. That is, as shown in FIG. 7, the signal obtained from the switch circuit 34 during reproduction is divided into one segment each of left channel data TL ₁ , TL _{2 .} . . and right channel data, as shown in FIG. 7A.
When TR ₁ , TR ₂ ... are signals that appear alternately, one of the right channels shown as TR ₂ in the figure
Consider the case where data for a segment is lost. At this time, the operating modes of the RAMs 40 and 41 are as shown in FIGS. That is, the data TL ₁ of the left channel is written to the RAM 40, and the data TR ₁ of the right channel is written to this RAM 40, and corrections are made in the period of 1/120 seconds after the write period, and then in the 1/30 second period. A readout is made during a period of seconds,
On the other hand, RMA41 has left channel data TL _2.
The right channel data TR ₂ is written and corrected, but since the right channel data TR ₂ is missing at this time, it is determined that it cannot be corrected during that correction period, and this TR _{2 data} is After the data correction period, the read period that should appear as the RAM41 mode does not occur;
40 continues to be in the read state, data TL ₁ and TR ₁ are read once again, and the missing data TR ₂ is compensated for. This is a so-called pre-hold among modification methods.

By the way, in this case, the left and right channel data of one segment each are stored in the same RAM.
As is clear from FIG. 7, the data TR ₂
Correct data even though only one is incorrect
TL ₂ will also be discarded.

An example that overcomes the above drawbacks is shown below.

That is, FIG. 9 shows an example of the recording system, and this example has three RAMs. And this RAM
may each have the capacity to accommodate one segment of data. In other words, it is not necessary to have the capacity to accommodate two segments of data as in the example in Figure 6;
This is the result.

In this example as well, the heads 1A and 1B are rotated in synchronization with the 30 Hz signal S _S obtained from the reference master clock generator 55 from the control signal generating circuit 56.

Then, the left channel audio signal S _L and the right channel audio signal S _R through the input terminals 51 and 52 are sent to the switch circuit 53 by the 44.1 kHz switching signal SW (FIG. 10A) in the same way as in the previous example. Alternately switched, A/D
The data is supplied to the converter 54 and converted into 16-bit data S _O (FIG. B) per word.

The output signal of the A/D converter 54 is sent to three output terminals by switch circuits 57 and 58 having three output terminals.
It is selectively supplied to RAMs 59, 60 and 61.

Furthermore, signals for controlling writing and reading of these three RAMs 59, 60, and 61 are sent from the control signal generation circuit 56 to the RAMs 59, 6, and 61.
It is supplied to control terminals 0 and 61. That is, the write control signal RWL of the left channel signal is sent to the three RAMs 59, 60,
At the same time, a write control signal RWR of the right channel signal is supplied to three RAMs 59, 60, and 61 via a switch circuit 63. Further, a read control signal RRA is supplied to these RAMs 59, 60, and 61 through a switch circuit 64.

The switch circuits 57 and 62 output the left channel data (every other word L ₀ of the output _SO ,
L ₂ ,...) to three RAMs 59, 60, 61 for a predetermined period of time, while the switch circuits 58, 63 are the data words of the right channel.
This is a switch for writing R ₀ , R ₁ , R ₂ . . . into three RAMs 59, 60, 61 for a predetermined period of time.
The switch circuits 57 and 62 are operated by the switching signal SWL from the control signal generation circuit 56.
RAM59 ~ every 1/30 seconds in the order shown in Figure F
The switch circuits 58 and 63 switch the RAMs 59 to 61 every 1/30 seconds in the order shown in FIG. 10G by the switching signal SWR from the control signal generating circuit 56. can be switched.

In this way, the left channel data is in the order shown in Figure 10F, and the right channel data is in the 10th order.
RAM59, respectively, in the order shown in Figure G.
60 and 61 are selected and each 1/30 second worth of data is written to one RAM.

In this case, the data of the left channel and the data of the right channel are not switched and written to each RAM at the same time, but
The data switching point is different between the left channel and the right channel. In other words, the right channel and left channel signals are alternately taken out by the 44.1 kHz signal SW to the switch circuits 57 and 58.
In this case, as shown in FIG. 10B, the word one word before the first data word L ₀ of the data L ₀ to L ₁₄₆₉ for one segment of the left channel is switched to the right channel. of data R ₀ to R ₁₄₆₉ for one segment of
The address is determined to be the 734th data word _R734 . And the left channel data consisting of every other word L ₀ to L ₁₄₆₉
1470 pieces of one segment data are written to the RAM 59. At this time, during the period in which data from L ₀ to L ₁₄₆₉ is taken in, and until the first half of data L ₀ to L ₇₃₅ is taken in, the data from R ₇₃₅ of the right channel is stored in RAM 61.
The last 735 pieces of data of one segment of the right channel up to R ₁₄₆₉ are taken in, and the data from L ₇₃₅ to L ₁₄₆₉ in the latter half is stored in the RAM 59.
During the writing period, data from words R ₀ to R ₇₃₄ in the first half of one segment data of the right channel is taken into the RAM 60 .

The operating mode of RAM59, 60, 61 is the 10th
As shown in Figures C, D, and E, after data for a 1/30 second period for the left channel and right channel, respectively, has been written, a 1/60 second period for each half revolution of heads 1A and 1B is written. Of these, both tape 2
parity and CRC for the data on its left or right channel during a period of 1/120 seconds when it is not connected to
The code is generated and added, and then the head 1A
Alternatively, data is read during a period of 1/120 seconds when 1B is in contact with tape 2.

In this case, Figure 10 C, D, E, F, G and H
As you can see, three RAMs 59, 60, 6
Two of 1 are always in a state where the right channel or left channel signal is written, and the remaining one
The RAM is controlled to be in the read state.

That is, the read control signal RRA from the control signal generation circuit 56 is selectively supplied to the three RAMs 59 to 61 through the switch circuit 64. Further, the output signals of the switch circuits 57 and 58 are connected to the output terminal of a parity and CRC code generation/addition circuit 66 through a three-terminal switch circuit 65. Furthermore, the output signals of RAMs 59, 60, and 61 pass through a switch circuit 67 to parity and
The signal is supplied to the input terminal of the CRC code generation/addition circuit 66. These switch circuits 64, 65 and 67 are sequentially switched to RAMs 59, 60 and 61 every 1/60 seconds in the switching order shown in FIG. 10H by the switching signal SWPR from the control signal generating circuit 56. Can be switched.

In addition, the control signal generation circuit 56 sends a 60Hz control signal CP (10th
Figure I) is provided. Then, there is a period of 1/120 seconds during which this signal CP is at a high level (both heads 1A and 1B do not come into contact with tape 2 during this period).
Then, the circuit 66 generates and adds parity and CRC codes to the data of each channel, and the audio data with the redundant data added is rewritten into the RAM selected by the switches 64, 65, and 67. . Next, the audio data to which the redundant data has been added is read out during a period of 1/120 seconds when the signal CP is at a low level (during this period, the head 1A or 1B is in contact with the tape 2).

In this way, from RAM59, 60, and 61, data of 1 channel for 1/30 seconds is transmitted by 1/4 in a period of 1/120 seconds.
The signal is time-compressed (in terms of data, it is compressed by 1/2 because it is one of two channels) and read out, and is supplied to the recording processor 68 through the switch circuit 67. Then, in this recording processor 68, processing is performed to add a synchronization signal, preamble and postamble for each block as in the above example, and appropriate modulation is added for recording, and the signals are supplied to the heads 1A and 1B. be done. Heads 1A and 1B receive the servo reference signal from the control signal generation circuit 56.
Since the head 1A is synchronized with the _S
Each track 4A is recorded as shown in Figure 0J on tape 2, and one segment worth of audio PCM of the right channel is recorded.
Head 1B with data as shown in Figure 10L.
Accordingly, each track 4B is recorded in the tape contact section.

Next, the reproduction of data recorded in this manner will be explained.

FIG. 11 shows an example of a reproduction system. Moreover, FIG. 12 shows the timing chart.

Heads 1A and 1B each receive a 30Hz signal based on the output signal of master clock generation circuit 76.
As in the previous example, the phase is controlled by S _SP to achieve a predetermined rotational phase.

In this case, the playback output of head 1A is as shown in Figure 12A.
The timing of the playback output from the head 1B is as shown in FIG. 1B. These playback outputs are from amplifiers 71A and 71B.
The switch circuit 72 is alternately switched by the switching signal SW (FIG. 12C) from the control signal generation circuit 75, as shown in FIG. 11D. An output SP is obtained in which data TL for one track and data TR for one track of the right channel are alternately and intermittently continued.

The output SP obtained in this way is restored to a digital signal in the digital signal restoration circuit 73,
Error detection and RAM write control signal generation circuit 7
4. In this circuit 74, error detection of data of each channel is performed by parity and
This is done using a CRC code and three
Generates address and timing signals for writing data into RAMs 77, 78, and 79.

The switch circuit 80 transfers the error-detected data from the circuit 74 to three RAMs 77, 78, 79.
The switch circuit 80 is a switch for switching between loading the data into the data and loading the error-corrected data from the error correction circuit 81. This switch circuit 80 receives the write and correction switching signal _W K).

This signal _WCP is a 60Hz signal that is synchronized with the head output, and its high level period
PA is a period in which head output is obtained, and during this period PA, the switch circuit 80 is switched to the state shown in the figure, and the three RAMs 77, 78, 79
mode for importing data. Meanwhile this signal
The period PB in which the _WCP is at a low level is a period in which no head output is obtained, and during this period PB, the switch circuit 80 is switched to the state opposite to the state shown in the figure, and the correction circuit 81 changes the state of the three RAMs. It is said to be a mode that works advantageously against

Period during which the switch 80 is switched to the state shown in the diagram
In the PA, the error-detected data passed through this switch circuit 80 is passed through a switch circuit 82 and selectively supplied to the input terminals of RAMs 77, 78, and 79. Further, the write address and write timing signal from the circuit 74 are sent to the switch circuit 8.
3 to the control terminals of these RAMs 77, 78, and 79. Furthermore, RAM77,
The outputs of 78 and 79 are selectively supplied to the input terminal of a correction circuit 81 through a switch circuit 84.

It is the switching signal SWC from the control signal generation circuit 75 that controls which of the RAMs 77, 78, and 79 input data is written.
This switching signal SWC is applied to each switch circuit 8 every 1/60 seconds in synchronization with the signal WC as shown in FIG. 12H.
2, 83 and 84, and the order thereof is as shown in FIG. 12H.

Therefore, for example, RAM77 is selected 1/
During the first half of 60 seconds, the left channel data, which is the playback output of head 1A, is stored in RAM 77.
written to a given address in the second half of the period
In the PB, the written data is corrected in the correction circuit 81, and the corrected data is written to the same address in the RAM 77 again through the switch circuit 80. RAM7
The same goes for RAM 8 and 79, resulting in RAM 7
7, 78, and 79 are written with error-corrected data.

The timing for reading from the RAMs 77, 78, and 79 is determined by a signal from the control signal generation circuit 75. That is, the read signal from the timing signal generation circuit 75 is sent to the switch circuit 85.
and 86, the data is selectively supplied to RAMs 77, 78, and 79. Also, RAM77, 78, 79
The output signals of are supplied to modification circuits 89 and 90 through switch circuits 87 and 88. The switch circuit 85 and the switch circuit 87 are switch circuits for switching for reading audio PCM data of the left channel, and the switch circuits 86 and 88
is a switch circuit for switching the right channel audio PCM data readout. The switch circuits 85 and 87 are the control signal generation circuit 7.
switched by the control signal SWL _P from 5,
The switch circuits 86 and 88 are respectively switched by the control signal SWL _P from the control signal generating circuit 75. The timing of switching by the signal SWL _P is in the order shown in FIG. 12I, and the left channel audio PCM data is temporally changed to The signal is expanded twice and read out from the three RAMs 77 to 79 as continuous signals. The timing of switching by the switching signal SWR _P is set in the order shown in FIG. As 3 RAM77~
79.

Therefore, the left channel audio PCM data is obtained from the switch circuit 87, and is supplied to the modification circuit 89, where the data for which error correction could not be performed is modified. Also, the right channel audio is output from the switch circuit 88.
PCM data is obtained and supplied to a modification circuit 90 to modify the data for which error correction has not been completed. The error correction method in the correction circuits 89 and 90 uses, for example, the pre-hold as described above.

The output signals of the correction circuits 89 and 90 are supplied to a switch circuit 91, which corresponds to the signal SW during recording.
By alternately switching this switch circuit 91 with a 44.1 kHz signal, the words of the left channel and right channel are converted back to analog signals in a time-sharing manner in the D/A converter 92, and then converted back to the analog signals. The data is alternately switched to amplifiers 94L and 94R by a 44.1 kHz switching signal in a switch circuit 93, whereby analog audio signals S _L ' and S _R ' of the right channel and left channel are extracted.

As described above, the left channel and right channel can be recorded as separate tracks, and in this example, each of the RAMs 77, 78, and 79 only needs to have a capacity that can store one segment of data. capacity for two segments
It does not require RAM and can be configured at low cost.

Furthermore, unlike the above-mentioned example, according to this example, even if there is data that could not be corrected in the correction circuits 89 and 90, correct data will not be discarded as in the above-mentioned example. There are advantages.

That is, FIG. 8 is a diagram for explaining the same, and FIG. 8A shows the output signal of the switch circuit 72, which shows 1 segment data TL ₁ of the left channel, 1 segment data TR ₂ of the right channel, and data TL ₃ of the left channel. , right channel data TR ₄ , and so on. In this case, when the right channel signal TR ₄ is missing by one track,
Figure 8 shows the operating modes of RAM77, 78, and 79.
The result will be as shown in BCD, and the erroneous data will not be imported into RAM 77, and the next data TL ₃
is fetched, and the previous data is read out from the RAM 78 again. In this case, as is clear from the figure, correct data will never be discarded as in the previous example.

As described above, according to the present invention, the data of the right channel and the left channel can be recorded on separate tracks, which is very convenient for after-recording of audio signals. Further, according to the present invention, since the tape wrapping angle is made smaller than the angular spacing between the heads, there is a period in which none of the heads are in contact with the tape, and by using this period, redundant data for the digital signal can be stored. can be easily added without going through a buffer circuit, and has the effect of greatly simplifying the configuration.

It will be easily understood that the present invention is applicable not only to the case of two heads but also to the cases of three and four heads.

In addition, in the above example, the tape wrapping angle is set to half the head angle spacing, but this is not a limitation.In short, when multiple heads are arranged at equal angular intervals, the tape wrapping angle is smaller than the head angle spacing. All you have to do is wrap the tape around the corner.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an example of a rotary head device used in an example of the apparatus of the present invention, FIG. 2 is a diagram showing a recording track pattern thereby, and FIG. 3 is a system diagram of an example of an audio signal recording device. FIG. 4 is a diagram for explaining the same and shows a regeneration timing chart, FIG. 5 is a system diagram of an example of the regeneration system, FIG. 6 is a diagram showing a time chart of an example of the apparatus according to the present invention, and FIG. is a diagram for explaining error correction in the example of FIG. 6, FIG. 8 is a diagram for explaining the effect of another example of this invention, and FIG. 9 is an example of a recording system of another example of this invention. FIG. 10 is a time chart for explaining the system, FIG. 11 is a system diagram for another example of the reproduction system, and FIG. 12 is a time chart for explaining the same. 1A and 1B are rotating heads, 2 is a magnetic tape,
17, 18, 40, 41 and 77, 78, 79 are RAMs for data storage, and 25 and 66 are parity and CRC generation additional circuits.

Claims (1)

[Claims] It has 1 N (N is an integer of 2 or more) rotating heads, the recording medium is wound around the guide drum over an angular range less than 360°/N, and the N channels of audio signals are PCM. At the same time, the PCM signals of each channel are converted into blocks at predetermined intervals, and the angular intervals during which the N rotary heads are not in contact with the recording medium are used to convert the PCM signals of each channel into blocks. Redundant data is added to the data for each predetermined period, and the PCM signal of the audio signal with this redundant data added is compressed into the contact area of each head to the recording medium, and An audio signal recording device configured to record an audio signal by forming a separate track for each channel on the recording medium in the contact area of the head with the recording medium.