JPH08130711A - Digital information recording and reproducing device - Google Patents

Abstract

PURPOSE: To share the memory of video signals and sound signals and to reduce the number of the memories. CONSTITUTION: This device is provided with signal input means 21 and 22, the storage means 9 of signals inputted to the input means, a compression means 1 for compressing the signals and generating compressed signals, encoding means 3 and 4 for adding error correction codes, the recording means 6 for recording the signals encoded in the encoding means 4 onto a recording medium 11, the reproduction means 13 of the recording medium 11, decoding means 15 and 16 for performing error correction to the signals reproduced in the reproduction means 13, an expansion means 11 for performing an expansion processing to the compressed signals and generating digital signals and signal output means 12 and 24 for outputting the digital signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to recording / reproducing of a digital information signal, and more particularly, to one channel or two channels of both a compressed digital video signal and a digital audio signal.
The present invention relates to a digital information recording / reproducing apparatus suitable for recording / reproducing on a channel.

[0002]

2. Description of the Related Art As a device for recording and reproducing both digital video signals and digital audio signals, digital VTRs for business use, D1-VTR, described in "Digital Video Recording Technology" (Nikkan Kogyo Shimbun), pages 133-154, D2-
There are VTRs and the like.

[0003]

In the above-mentioned prior art, since the processing of the video signal and the processing of the audio signal are performed separately, a memory is used for each. Further, in order to develop the digital VTR for home use, it is necessary to compress the video signal, which further complicates the video processing.

When a home-use digital VTR is constructed with the above conventional technique, for example, as shown in FIG. 4, a storage circuit 150 for video signal processing and a storage circuit 151 for audio signal processing have a signal processing circuit. There is a problem in that the memory circuits 9 for use in each are separately required, and the price increases.

Further, in a home digital VTR,
Recording and reproducing high-definition video using two-channel recording has been considered, but the conventional technique has a problem that a memory is required for each channel.

An object of the present invention is to reduce the number of memories used in a digital information recording / reproducing apparatus and to reduce the cost.

[0007]

In order to achieve the above object, a first digital signal is input in an apparatus for dividing a plurality of kinds of signals into N (N is a natural number) systems and simultaneously recording and reproducing. A first signal input means, a second signal input means for inputting a second digital signal, a first input signal input by the first input means, and a second input signal input by the second input means. Storage means for storing the input signal,
The first input signal stored in the storage means is subjected to processing such as compression to generate a compressed signal, the compression means stores the compressed signal in the storage means, the compressed signal stored in the storage means, and the first compression signal stored in the storage means. Second encoding means for adding a second error correction code to the second input signal, and first encoding for adding a first error correction code to the signal encoded by the second encoding means Means, recording means for dividing the signal encoded by the first encoding means into the N systems and recording on a recording medium, reproducing means for reproducing the recording medium, and the reproducing means. First decoding means for performing first error correction or error detection on the signals of the N systems reproduced by the means using the first error correction code, and storing in the storage means; Error correction or error detection of the stored signal on the storage means The second decoding means for performing the second error correction or error detection using the second error correction code, and the compressed signal among the signal signals on the memory circuit decoded by the second decoding means. Decompression means for performing decompression and the like to generate a third digital signal, first signal output means for outputting the third digital signal, and the memory decoded by the second decoding means. Second signal output means for outputting the second digital signal among the signal signals on the circuit is provided.

Further, during recording / reproducing of N systems, the storage means is operated at a frequency N times that of recording / reproducing of one system.

[0009]

With the above structure, even in the case of N-channel recording, it is possible to share all the memories used for compression / expansion processing, voice processing and encoding / decoding processing, and the number of memories can be reduced.

Further, during recording / reproducing of N channels, the storage means is operated at a frequency N times as high as that of recording / reproducing of one channel so that 1-channel recording and N-channel recording can be easily performed by a common circuit. It is possible to maintain sex.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a home-use digital VTR according to the present invention. This device uses compressed video signals, 48 kHz, 44.1 kHz, 32
It is designed so that digital voices having a sampling frequency such as kHz can be recorded independently.

In the figure, 7 is a recording amplifier, 8 is a switch, 10 is a rotary head, 11 is a magnetic tape, 12 is a reproduction amplifier, 17 is a signal processing circuit, 21 is an audio signal input terminal, and 22 is an image signal input terminal. , 23 is an audio signal output terminal, 24 is an image signal output terminal, and 25 is a data bus connected to the storage circuit 9. The signal processing circuit 17 is, for example, one LSI, and the memory circuit 9 is the signal processing circuit 17.
It is realized by an external RAM or the like.

FIG. 2 shows a recording track format on the magnetic tape 11. Reference numerals 30 and 32 are audio areas, and reference numerals 31 and 33 are video areas. Audio and video are recorded in different areas.

FIG. 3A shows the block format of the audio areas 30 and 32, and FIG. 3B shows the block format of the video areas 31 and 33. The audio area and the video area both have a common block structure, and have a 2-byte sync signal 40 or 46, an ID 41 or 47 having information such as a block address, a 77-byte signal, and an 8-byte C1 parity 43 for error correction. Alternatively, 49 blocks of 90 bytes form one block. The audio area is 9 blocks of audio signal 45 and 5 blocks of C2 parity 42 1
It consists of 4 blocks. Information such as a sampling frequency is recorded in the audio auxiliary signal 44. The video area is composed of video auxiliary signals 50 and 52 of 3 blocks, video signal 51 of 135 blocks, and C2 parity 48 of 11 blocks, for a total of 149 blocks.

The recording / reproducing operation of this apparatus will be described with reference to FIG.

At the time of recording, the video signal input to the image signal input terminal 22 is subjected to processing such as quantization and bit compression by the image compression / expansion circuit 1 and stored in the storage circuit 9 via the data bus 25. . The video signal is read from the storage circuit 9, the C2 encoding circuit 3 adds the C2 parity 42, and the video signal is stored again in the storage circuit 9. The audio signal input from the audio signal input terminal 21 is subjected to processing such as quantization by the audio processing circuit 2, stored in the storage circuit 9 via the data bus 25, and stored in the storage circuit 9 via the C2 encoding circuit 3. 42 is added. After that, since the audio signal and the video signal have the same block structure, common processing is performed, C1 parity 43 and 49 are added by the C1 encoding circuit 4, and the synchronization signal 40 and 46, IDs 41 and 47 are added, modulation processing is performed, and the data is recorded on the magnetic tape 11 via the recording amplifier 7 and the switch 8 in accordance with the track format of FIG.

At the time of reproduction, the recording signal recorded on the magnetic tape 11 is reproduced by the rotary head 10, and the switch 8,
It is sent to the demodulation circuit 13 via the reproduction amplifier 12. The demodulation circuit 13 performs demodulation processing and detection of the synchronization signals 40 and 46, and the signals reproduced in the audio areas 30 and 32 are audio signals, and the signals reproduced in the video areas 31 and 33 are video signals. Are respectively stored in predetermined areas of the storage circuit 9. After that, data is sent from the memory circuit 9 to the C1 decoding circuit 15, C1 error correction in the block direction is performed using the C1 parities 43 and 49, and the corrected signal is stored in the memory circuit 9 again. The audio signal and the video signal are subjected to C2 error correction in the direction orthogonal to the C1 code in the C2 decoding circuit 16 according to the respective formats, and are stored in the storage circuit 9 again. The video signal is expanded by the image compression / expansion circuit 1 so as to restore the compressed signal to the original, and output from the image signal output terminal 24. On the other hand, the voice signal is read from the storage circuit 9 and then sent to the voice processing circuit 2 to interpolate the data for which error correction cannot be performed, and the voice signal output terminal 2
Although not shown in the figure, the digital signal is converted into an analog signal by the D / A converter or is digitally modulated by the D / A converter and output as a digital signal.

In the above description, the C2 encoding circuit 3
The C2 decoding circuit 16 and the C2 decoding circuit 16 perform both the C2 processing of the audio signal and the C2 processing of the video signal, but as shown in FIG. 3, since the audio C2 and the video C2 have different code configurations, they are different from each other. The circuit may be dedicated.

FIG. 5 is a timing chart showing the timing of recording. In this device, 1 in the video signal
The rotary head 10 rotates 5 times during the frame, and the relationship is 10 tracks / 1 frame. In FIG.
Reference numeral 70 is a frame signal indicating one frame in a half cycle, and 71 is a track signal indicating one rotation of the rotary head 10 in one cycle (one track in a half cycle).

The video signal is input and quantized during one frame indicated by 80 and stored in the storage circuit 9. 8
Image compression processing is performed in the next one frame shown by 8, and is stored again in the storage circuit 9.

On the other hand, as shown at 73, the audio signal is input in frame units. FIG. 6 shows an example of interleaving of a 1-frame audio signal over 10 tracks, where Ln is the n-th data of the left channel,
Rn represents the nth data of the right channel.
As shown in the figure, the L data is distributed over the first half of the 5 tracks and the R data is distributed over the latter half of the 5 tracks at a period of 15 samples.

The compressed signal 88 and the input voice signal 81 are C2 encoded and C1 encoded in the next one frame. Here, C2 encoding is performed in the first half of each track, and C1 encoding is performed in the second half of each track. That is, of the C2 encoding shown at 74, 82-
The C2 parity 48 is added to 10 tracks of 83 and stored in the storage circuit 9. Further, C1 parity 49 is added over 10 tracks 84 to 85. After that, the modulation process is performed by the modulation circuit 6 on the next track, and the data is recorded on the magnetic tape.

As described above, the storage circuit 9 must be able to access all of the video input 72, video compression processing 78, audio input 73, C2 coding 74, C1 coding 76, and modulation 77 processing. I have to. 7A and 7B show examples of slot division of the memory circuit 9, where FIG. 7A shows an example of a 5-slot configuration and FIG. 7B shows an example of a 4-slot configuration. In the figure, 72 is a video signal input slot, 73 is an audio signal input slot, 74 is a C2 slot, 76 is a C1 slot, 77 is a modulation slot, and 78 is a video compression slot. As shown in FIG. 5, C1 encoding and C2
Since the encoding is performed at different times, the C2 slot 74 and the C1 slot 76 can be shared. In the case of a 5-slot configuration, letting F be the frequency of the fastest access among 72 to 78, the frequency of each slot is 5F.
Alternatively, it may be slightly higher than 5F.

However, of the five types of slots, the audio input slot 73 is different from the video input slot 72.
The frequency is low, and the C2 slot 74 or the C1 slot 76 can also have a relatively low frequency. Therefore, in the 4-slot configuration, for example, a voice input slot 73, a C2 slot 74, and a C1 slot 7 are provided.
6 is a common slot, and time division processing is performed. In this case, the slot frequency is 4F, and a slower frequency may be used than in the case of the 5-slot configuration.

Further, FIG. 8 shows the reproduction timing, and the processing opposite to that at the time of recording is performed. The signals reproduced and demodulated over 10 tracks of 96 to 97 are C1 corrected at the timings of the following tracks 98 to 99, C2 corrected at the timings of 100 to 101, and expanded at the timing of 104. , 105. On the other hand, the audio signal is output during one frame shown at 106. Therefore, a storage circuit having the same storage capacity as that at the time of recording is required during reproduction.

At the time of reproduction as well as at the time of recording, 5 shown in FIG.
Slot configurations to 4 slot configurations can be used.

In the above description, the case where one channel recording / reproducing is performed by one pair of heads facing each other has been described.
In this recording / reproducing apparatus, a case of 2-channel recording in which recording / reproducing is simultaneously performed by two sets of heads is also considered. For example, it is considered that 1-channel recording is used for recording standard images and 2-channel recording is used for recording high-definition images. In the case of 2-channel recording, in FIG. 2, 30 and 31 are heads of the same set, and 32 and 33 are heads of another set, and recording and reproduction are performed.

FIG. 9 is a block diagram of a recording / reproducing apparatus for 2-channel recording / reproducing. Two
Channel recording doubles the amount of information to be processed, so
The slot frequency of the storage circuit 9 is set to be twice as high as that for recording / reproducing one channel.

That is, at the time of recording, video input, video compression, C2 coding, C1 coding, etc. are performed at double speed at the timing of FIG. 5, and the modulation processing is performed by the modulation circuits 6 and 11.
This is performed for each channel using two sets of 0. In this case, the modulation circuits 6 and 110 may perform processing at the same speed as when recording one channel.

On the other hand, the signal reproduced for each channel at the time of reproduction is processed by the demodulation circuits 13 and 111 at the same speed as that at the time of recording one channel and stored in the memory circuit 9 (however, to the memory circuit 9). Writing is twice as fast). After that, at the timings shown in FIG. 8, processing such as C1 decoding, C2 decoding, video expansion, video output, etc. is performed at a speed twice as fast as that in 1-channel reproduction.

The switching of the operating frequency is performed by the mode switching circuit 120.

By the above operation, it is possible to perform 2-channel recording / reproducing with only one system of storage circuit, encoding circuit and decoding circuit. However, when it is difficult for the encoding circuit and the decoding circuit to operate at double speed, the processing may be performed by using two systems. In this case as well, by setting the slot frequency of the storage circuit to double. The storage circuit 9 may be provided in only one system.

Although FIG. 9 shows the case of 2-channel recording / reproducing, in general, also in N-channel recording / reproducing, the memory circuit 9, the C2 encoding circuit 3, the C1 encoding circuit 4, the C1 decoding circuit 15, It suffices to operate the C2 decoding circuit 16 and the like at N times the frequency and use N modulation circuits 6 and demodulation circuits 13.

In the above description, image compression, audio input processing, C2 coding, C1 coding, modulation processing, demodulation processing at reproduction, C1 decoding, C2 decoding, audio output processing, and image expansion at the time of recording are described. For example, although the signal processing circuit 17 is implemented by one LSI, the image processing and the audio processing may be performed by an LSI different from the other processing. A block diagram at this time is shown in FIG. In the figure, 18 is a recording / reproducing processing circuit, 19 is a video / audio processing circuit.
Recording / reproducing processing circuit 1 for performing audio input processing and output processing
At 8, C1 processing, C2 processing, and modulation / demodulation processing are performed. In this case, the video storage circuit 160 is provided to compress the video,
The video storage circuit 160 may perform video expansion, audio input, and audio output, and the storage circuit 9 may perform C2 processing and C1 processing.

Further, as shown in FIG. 3, since the code sequence of C1 encoding and C1 decoding coincides with the block in recording / reproducing, at the time of recording, it is re-stored in the memory circuit 9 after C1 encoding. Instead, the data may be directly sent to the modulation circuit 6 and recorded. Similarly, at the time of reproduction, after being demodulated by the demodulation circuit 13, the data is not stored in the storage circuit 9 but is directly sent to the C1 decoding circuit 15 to output C
It may be stored in the storage circuit 9 after performing 1 decoding.
As a result, the number of accesses to the memory circuit 9 can be reduced.

[0037]

According to the present invention, in a device for recording and reproducing both a digital video signal and a digital audio signal, the memory for the video signal and the audio signal can be shared, and the number of memories can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital information recording / reproducing apparatus according to the present invention.

FIG. 2 is a track format diagram of a digital information recording / reproducing apparatus.

FIG. 3 is a block format diagram of a digital information recording / reproducing apparatus.

FIG. 4 is a block diagram of a digital information recording / reproducing apparatus in a conventional apparatus.

FIG. 5 is a timing chart showing recording timing of the digital information recording / reproducing apparatus of the present invention.

FIG. 6 is an explanatory diagram of audio interleaving of a digital information recording system.

FIG. 7 is a timing chart showing a slot configuration of a memory circuit of the present invention.

FIG. 8 is a timing chart showing the reproduction timing of the digital information recording / reproducing apparatus of the present invention.

FIG. 9 is a block diagram showing another embodiment of the digital information recording / reproducing apparatus according to the present invention.

FIG. 10 is a block diagram showing another embodiment of the digital information recording / reproducing apparatus according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Image compression / expansion circuit, 2 ... Audio processing circuit, 3 ... C2 encoding circuit, 4 ... C2 encoding circuit, 6 ... Modulation circuit, 9 ... Storage circuit, 10 ... Rotating head, 13 ... Demodulation circuit, 15 ... C1 Decoding circuit, 16 ... C2 decoding, 17 ... Signal processing circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H04N 7/30 H04N 7/133 A

Claims (11)

[Claims] 1. An apparatus for recording / reproducing a plurality of types of digital signals, comprising: first signal input means for inputting a first digital signal; second signal input means for inputting a second digital signal; Storage means for storing the first input signal input by the first signal input means and the second input signal input by the second signal input means, and the first input signal stored in the storage means A compression means for performing compression processing to generate a compressed signal and storing the compressed signal in the storage means, and a second error correction code is added to the compressed signal and the second input signal stored in the storage means. Second encoding means, first encoding means for adding a first error correction code to the signal encoded by the second encoding means,
Recording means for recording the signal encoded by the first encoding means on a recording medium, reproducing means for reproducing the recording medium, and the first error in the signal reproduced by the reproducing means. A first decoding means for performing first error correction or error detection using a correction code and storing it in the storage means, and the first error correction or error detection for the storage signal on the storage means Second decoding means for performing second error correction or error detection using the second error correction code, and expansion of the compressed signal of the signals on the storage means decoded by the second decoding means Decompressing means for generating the third digital signal by performing the processing of 1., first signal outputting means for outputting the third digital signal, and signal on the storage means decoded by the second decoding means. Of the second digital signal Digital information recording and reproducing apparatus characterized by comprising a second signal output means for force. 2. The first coding means according to claim 1, wherein the first error correction code is stored in the storage means, and the recording means is the first coding means. A signal on the storage means to which an error correction code is added is recorded in the recording medium, the reproduction means stores the reproduced reproduction signal in the storage means, and the first decoding means is stored in the storage means. A digital information recording / reproducing apparatus for performing the first error correction or error detection on the reproduced signal. 3. The recording means according to claim 2, wherein said storage means inputs and outputs a signal to and from said first slot for storing a signal from said first signal input means and said compression means. A second slot, a third slot for storing a signal from the second signal input means, and a fourth slot for inputting / outputting a signal to / from the second encoding means and the first encoding means. And a fifth slot for outputting a signal to the recording means, and at the time of reproduction, the storage means outputs a signal to the first slot for outputting a signal to the first signal output means and a signal for the expansion means. A seventh slot for inputting / outputting a signal, an eighth slot for outputting a signal to the second signal output means, a ninth slot for inputting / outputting a signal to / from the first decoding means and the second decoding means. Slot for inputting signals from the reproducing means. In the fourth slot, the input and output of the first encoding means and the input and output of the second encoding means are time-divided within a fixed period, and the ninth slot In the slot, a digital information recording / reproducing apparatus that performs input / output of the first decoding means and input / output of the second decoding means by time division within a fixed period. 4. The recording means according to claim 2, wherein the recording means inputs and outputs signals to and from the first slot for storing the signal from the first signal inputting means and the compressing means during recording. Slot, a third slot for storing a signal from the second signal input means, and inputting / outputting a signal to / from the second encoding means and the first encoding means, and a signal to the recording means. And a fifth slot for outputting a signal to the first signal output means, and a sixth slot for inputting and outputting a signal to and from the decompressing means during reproduction. Slot, a seventh slot for outputting a signal to the second signal output means and inputting / outputting a signal to / from the first decoding means and the second decoding means, and a signal from the reproducing means. Has an eighth slot, and in the third slot Performed by time division input and output of the input and output and the second coding means input and said first encoding means of the signal from said second signal input means within a predetermined time period,
In the seventh slot, output of a signal to the second signal output means, input / output of the first decoding means, and input / output of the second decoding means are time-divided within a fixed period. Digital information recording / reproducing device. 5. An apparatus for dividing a plurality of types of signals into N systems and simultaneously recording and reproducing the signals, wherein first signal input means for inputting a first digital signal and first signal input means for inputting a second digital signal. Second signal input means, storage means for storing the first input signal input by the first signal input means and the second input signal input by the second signal input means, and storage in the storage means Compressing means for performing a process such as compression on the compressed first input signal to store the compressed signal in the storage means, and the compressed signal and the second input signal stored in the storage means. Second encoding means for adding a second error correction code; first encoding means for adding a first error correction code to the signal encoded by the second encoding means; The N number of signals encoded by one encoding means Recording means for dividing the recording medium into a system and recording it on a recording medium, reproducing means for reproducing the recording medium, and reproduction signals of the N systems reproduced by the reproducing means for the first error correction code. First error correction or error detection using the first decoding means for storing in the storage means, and the second error in the storage signal on the storage means in which the first error correction or error detection is performed. Second decoding means for performing second error correction or error detection using an error correction code, and expansion processing for the compressed signal of the signals on the storage means decoded by the second decoding means Out of the signals on the storage means decoded by the second decoding means, the decompressing means for generating a third digital signal, the first signal output means for outputting the third digital signal, Outputs the second digital signal Digital information recording and reproducing apparatus comprising a second signal output means that. 6. The method according to claim 5, wherein the first coding means stores the first error correction code in the storage means, and the recording means uses the first coding means to perform the first error correction code. The signal on the storage means to which the error correction code is added is recorded in the recording medium, the reproduction means stores the reproduced reproduction signal in the storage means, and the first decoding means stores in the storage means. A digital information recording / reproducing apparatus for performing the first error correction or error detection on the reproduced signal thus reproduced. 7. The method according to claim 5 or 6, wherein the second coding means and the first coding means perform coding of the N systems in common, and the recording means respectively The recording means comprises N system recording means for recording the system, the reproducing means comprises N system reproducing means for respectively reproducing one system, and the first decoding means and the second decoding means, A digital information recording / reproducing apparatus for commonly performing decoding of the N systems. 8. The recording means according to claim 5 or 6, wherein the second encoding means and the first encoding means are N system encoding means for respectively performing one system encoding. Is composed of N system recording means for respectively recording one system, and the reproducing means is composed of N system reproducing means for respectively reproducing one system, the first decoding means and the second decoding means. The decoding means is a digital information recording / reproducing apparatus comprising N system decoding means for respectively performing one system decoding. 9. The recording circuit according to claim 5, 6, 7 or 8, wherein when the signal of the first system is recorded or reproduced, the memory circuit operates at a first frequency and the signals of the N systems. A digital information recording / reproducing apparatus in which the storage circuit operates at a frequency N times the first frequency when recording or reproducing. 10. Claims 1, 2, 3, 4, 5, 6, 7, 8
Or 9, in recording, the second encoding is performed in the first half or the second half of the track cycle, the first encoding is performed in the second half or the first half of the track cycle, and in the reproduction, the first half of the track cycle or A digital information recording / reproducing apparatus which performs the first decoding in the latter half and performs the second decoding in the latter half or the first half of the track cycle. 11. Claims 1, 2, 3, 4, 5, 6, 7,
8. The digital information recording / reproducing apparatus according to 8, 9, or 10, wherein the first digital signal is a video signal and the second digital signal is an audio signal.