JPH07176149A - Method of recording data - Google Patents

Abstract

PURPOSE:To record the data requiring a low error rate by using third error correction encoding and further, to shorten the unit of the encoding and to reduce a consumption amount of a memory. CONSTITUTION:For a positive real number (x) and an integer (n) exceeding the (x), the data A provided with an amount capable of recording on (x) line tracks and the data B dependent on the data A are recorded on consecutive (n) line tracks on a recording medium. The data inputted as the data B are used for the error correction encoded data, and a symbol of an error correction code is constituted of plural symbols on the track. Thus, the recording with a lower error rate is realized with less memory consumption amount.

Description

Detailed Description of the Invention

The present invention relates to a recording method for recording digital data.

[0002]

2. Description of the Related Art Currently, video is digitized and compressed,
A digital VTR for recording and reproducing on a magnetic tape has been put into practical use. This digital VTR forms tracks as shown in FIG. 4 by helical scan recording and performs recording / reproduction. Here, 100 is a tape, 101 is a track, 102 is a sync block, and 103 is a sync. In this way, the track is divided into units called sync blocks with the sync 103 added at the beginning.

FIG. 15 is a block diagram of a conventional apparatus for recording and reproducing video. Here, 110 is a video signal processing circuit, 111 is a memory, 112 is an outer error correction coding circuit, 113 is an inner error correction coding circuit, 114 is a recording circuit, 115 is a recording head, 116 is a magnetic tape,
Reference numeral 117 is a reproducing head, 118 is a reproducing circuit, 119 is an inner error correcting circuit, 120 is a memory, 121 is an outer error correcting circuit, and 122 is a video signal processing circuit.

At the time of recording the video signal, the input video signal is digitized by the video signal processing circuit 110,
After processing such as compression, the data is converted into track units and output to the memory 111. The outer error correction coding circuit 112 performs outer error correction coding on the data in the memory 111 and outputs the parity to the memory. After adding the outer code parity, the data in the memory 111 and the parity are sequentially output to the inner error correction coding circuit 113. In the inner error correction coding circuit 113,
The data is subjected to inner error correction coding, added with parity, and output to the recording circuit 114. The recording circuit 114 modulates the error-correction-coded data, and the recording head 115
And is recorded on the magnetic tape 116.

At the time of reproduction, the reproducing head 117 reads the magnetic tape 116 and outputs it to the reproducing circuit 118. The inner error corrector 11 is demodulated by the reproduction circuit 118.
9 and performs inner correction and outputs to the memory 120. The outer error correction circuit 121 performs outer correction on the data in the memory. After that, the data in the memory 120 is output to the video signal processing circuit 122. The video signal processing circuit 122 decodes the data into a video signal and outputs it. As described above, the video signal is recorded and reproduced as digital data.

In the above method, the error correction code is constructed for each track as shown in FIG. Here, 130 is a data area, 131 is an inner parity area, and 132 is an outer parity area. The inner codeword is composed of sync block units, and the outer codeword is composed of the n-th symbol of the sync block. The order of recording on the tracks is as shown by the arrows.

In the digital VTR, since it is recorded as a digital signal, it is possible to record data of a computer or the like and other digital data as it is without being modulated. When data is recorded in such a video signal recording / reproducing apparatus, digital data is output to the memory 111 as shown in FIG. 5, and when reproducing, data in the memory 120 is output to record / reproduce the data. It is possible.

At this time, in order to reduce the error rate, the third
There is known a method of performing error correction coding of. FIG. 7 shows a block diagram of the recording / reproducing apparatus at this time. Where 14
0 is an error correction coding circuit, 141 and 142 are memories, 1
Reference numeral 43 is an error correction circuit, and other configurations are the same as those shown in FIG.

At the time of recording, the data is input to the memory 141, and first, the error correction coding circuit 140 performs error correction coding between tracks. Thereafter, outer error correction coding circuit 112 performs outer error correction coding in the track. Further, at the time of reproduction, the data subjected to inner error correction is input to the memory 142, first outer error correction circuit 121 performs outer error correction, and then error correction circuit performs error correction.

The structure of the code word used in the error correction coding circuit 140 at this time is shown in FIG. Reference numeral 150 denotes a track schematically, 151 denotes a track used as a data area, and 152 denotes a track used as a parity area. When a (m, k, d) code is used as a code word, the unit of error correction is m tracks, k tracks are used as a data area, and (m−k) tracks are used as a parity area. This is realized by using a code word in which the sync block numbers of all tracks in the error correction unit and the numbers in the sync block are the same.

[0011]

In the image compressed in the frame, it is possible to correct even if an error occurs,
In comparison with the fact that error propagation does not occur, computer data often cannot tolerate errors, and recording of video signals compressed between frames causes error propagation, resulting in a lower error rate. It is necessary to.

However, the recording / reproducing apparatus described above is an apparatus for recording / reproducing an image compressed in a frame, and has a high error rate for recording data in a computer or the like.
Further, in FIG. 8, since the error correction code forms one symbol of each track to form the codeword, the correction unit for error correction is a track corresponding to the codeword length of the error correction code. Has become.

In such a configuration, in order to use a code having a long distance for error correction, it is necessary to lengthen the error correction unit, which increases the memory capacity. In a recording / reproducing apparatus that records a video signal, it is difficult to increase the error correction unit because the capacity per track is large.

[0014]

In order to solve the above-mentioned problems, in the data recording method of the present invention, for a positive real number x and an integer n exceeding x, data having an amount recordable in x tracks is recorded. A and data B subordinate to the data A are recorded on continuous n tracks on the recording medium.

[0015]

In the present invention, with the above configuration, data is error-correction coded and recorded / reproduced.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A data recording method of the present invention will be described below with reference to the drawings. Hereinafter, it is assumed that the data A is the input data and the data B is the parity when the error correction coding between tracks of the input data is performed.

FIG. 1 is a block diagram of a recording / reproducing apparatus to which the data recording method of the present invention can be applied. Here, 1 is a formatter, 2 is a memory, 3 is an inter-track error correction coding circuit, 4 is an outer correction coding circuit, 5 is an inner error correction coding circuit, 6 is a recording circuit, 7 is a recording head, and 8 is A magnetic tape, 9 is a reproducing head, 10 is a reproducing circuit, 11 is an inner error correcting circuit, 12 is a memory, 13 is an outer error correcting circuit, 14 is an inter-track error correcting circuit, and 15 is a deformatter.

First, the input data is added with additional information such as the length of the data by the formatter 1 and is input to the memory 2 as data in units of tracks or data in units of error correction between tracks. The error correction coding is performed on the data in the memory 2 by the (a.n, a.x, a (n-x) +1) code, and the inter-track error correction coding circuit 3 is used.
And the parity is output to the memory. Here, a is an arbitrary real number such that an and ax are positive integers. Thereafter, the outer error correction coding circuit 4 performs error correction coding on a track-by-track basis with respect to the data in the memory 2 and the parity by the inter-track error correction coding circuit 3, and outputs the parity to the memory 2. After that, the data in the memory 2 and the added parity are output to the inner error correction coding circuit 5, are error correction coded in sync block units, and are output to the recording circuit 6.
The recording circuit 6 adds a sync to the input sync block, modulates the sync block, and outputs the modulated sync block to the recording head 7. Then, the recording head 7 records the encoded data on the magnetic tape 8.

Here, the inner error correction coding circuit 5 performs error correction coding in sync block units, and the outer error correction coding circuit 4 performs error correction coding in track units, whereas the inter-track error The correction coding circuit 3 performs error correction coding over these tracks in units of n tracks to improve the error correction capability not only for random errors but also for burst errors. The data is recorded on the magnetic tape 8 as described above.

At the time of reproduction, the reproduction head 9 outputs the data recorded on the magnetic tape 8 to the reproduction circuit 10. The reproduction circuit 10 demodulates the sync block and outputs it to the inner error correction circuit 11. The inner error correction circuit 11 performs error correction in sync block units and outputs it to the memory 12. The outer error correction circuit 13 performs outer error correction for the data of the memory 12 in track units. After that, after error correction is performed by the track-to-track error correction circuit 14, the data in the memory 12 is output to the deformatter 15 and is output as data. As described above, the data recorded on the magnetic tape 8 is reproduced.

Next, an example of the arrangement of the parity tracks is shown in FIG. Further, FIG. 3 shows an example of the structure of the code word of the error correction code used in the inter-track error correction coding circuit 3. Here, 20 is a schematic track, 21 is a track composed of a plurality of data areas, 22 is a parity track, and 23 is a certain code word.

In the present embodiment, the (a.n, a.x, a (n-x) +1) code is used for the inter-track error correction coding. Each codeword consists of a symbols of each track and has a (n−x) parity symbols. In this example, a = 4 and x = 9 are shown. For example, n
= 10, the codeword at this time is (40,36,5)
It becomes a sign.

In the past, 40 tracks were used as a unit for constructing this code. On the other hand, in the method of the present embodiment, since 10 tracks are used as a unit, the number of memories for error correction can be reduced as compared with the conventional case.
By doing so, the data can be recorded in the device for recording and reproducing the video, and the circuit can be shared.
Cost reduction is possible.

Further, by constructing a code word from a plurality of symbols on each track, it is possible to construct a code word having a long distance between tracks with a small number of tracks. Further, by setting n to a frame rate for recording video (for example, n = 10 for NTSC recording and n = 12 for PAL recording) and x = 1, it is possible to further share circuits such as a recording circuit. It is possible and convenient.

Although the number x of tracks for recording the data A is 9 in this embodiment, any positive real number that does not exceed n may be used. Although the track for recording the parity is the last track to be recorded, it may be recorded on any track.

Further, although the parity (data B) is continuously recorded in this embodiment, the data A may be mixedly recorded in the track, and the data B is used as the parity. Part of the information may be information such as the size of the input data.

Although the data A is computer data in this embodiment, it may be any digital data such as measuring instrument data and video signals. Further, it is not always necessary to use two memories 2 and 12, and they can be shared unless recording and reproduction are performed simultaneously.

The device configuration for implementing the data recording method of the present invention is not limited to that shown in FIG. 1, and other configurations are also feasible.

[0029]

As described above, according to the data recording method of the present invention, the error rate can be lowered and the circuit scale can be reduced by performing the error correction coding between the tracks to record the data. If it is applied to a device, it will exert a great effect.

[Brief description of drawings]

FIG. 1 is a block diagram of a recording / reproducing apparatus to which a data recording method of the present invention can be applied.

FIG. 2 is a configuration diagram showing an example of a parity track according to the data recording method of the present invention.

FIG. 3 is a configuration diagram showing an example of a codeword according to a data recording method of the present invention.

FIG. 4 is a track pattern diagram according to the data recording method of the present invention.

FIG. 5 is a block diagram of a conventional video recording device.

FIG. 6 is a configuration diagram of an error correction code according to a conventional example.

FIG. 7 is a block diagram of a recording / reproducing apparatus using a third error correction code according to a conventional example.

FIG. 8 is a configuration diagram of a codeword according to a conventional example.

[Explanation of symbols]

 1 Formatter 2 Memory 3 Track-to-track error correction coding circuit 4 Outer correction coding circuit 5 Inner correction coding circuit 6 Recording circuit 7 Recording head 8 Magnetic tape 9 Reproducing head 10 Reproducing circuit 11 Inner error correcting circuit 12 Memory 13 Outer error correcting circuit Circuit 14 Track-to-track error correction circuit 15 Deformer

Claims (9)

[Claims] 1. A data A having a recordable amount on x tracks for a positive real number x and an integer n exceeding the x.
And a data recording method for recording data B, which is dependent on the data A, on continuous n tracks on a recording medium. 2. The data recording method according to claim 1, wherein the data A comprises valid data A ′ and meaningless data A ″. 3. The data recording method according to claim 1, wherein the data B has a recordable amount in (nx) tracks. 4. The x as claimed in claim 1, wherein x is an integer.
Alternatively, the data recording method according to claim 2 or claim 3. 5. The data recording method according to claim 4, wherein the data A and the data B are recorded on different tracks. 6. The data according to claim 5, wherein the tracks for recording the data A are concentrated on a part of the recording medium, and the tracks for recording the data B are concentrated on a part of the recording medium. Recording method. 7. The data recording method according to claim 5, wherein the positions of the tracks for recording the data B in the n tracks are unique. 8. The data recording method according to claim 7, wherein n = 10 and x = 1. 9. The data recording method according to claim 7, wherein n = 12 and x = 1.