JPH07143442A - Digital signal recorder and digital signal reproducing device - Google Patents

Abstract

PURPOSE:To record data while reducing additional information effectively and to reproduce a video signal efficiently by recording frame information of data in a SYNC block to a predetermined location in the SYNC block in a 2nd group track. CONSTITUTION:A memory write control circuit 4 stores data coded in the unit of SYNC blocks SnB to memories 56. Various additional information is recorded at a predetermined position in the SnB and data of each DCT block are recorded in order from a lower frequency component. Thus, the data are sequentially recorded to each track of the memory 5. The additional information of higher frequency data of a 1st frame not written in the memory 5 is written to a predetermined position and the higher frequency data are written respectively to the data recording area of the memory 6 respectively. When a video signal of a 2nd frame is written in succession to the 1st frame, a pointer starting the input of the 2nd frame is recorded to a final byte and written in the remaining space. When the data are written from the start of the data recording area, frame information representing the 2nd frame is written and data of the 2nd frame are written.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a digital VTR,
The present invention relates to a digital signal recording device for recording a digital video signal and a digital signal reproducing device for reproducing a digital video signal.

[0002]

2. Description of the Related Art In a recording apparatus for performing high-efficiency encoding and recording within two frames, a certain number of blocks are used as one unit to indicate an address and what frame of data the data is recorded in. It had been. However, the data of the first frame is important in consideration of editing, special reproduction, etc., and it is necessary to easily read and decode the data and to prevent error propagation. As a measure against this, when recording the data of the first frame, the track to be recorded and the data arrangement in the track are fixed, and the low frequency data which is visually important is recorded. The high frequency data of the first frame and the data of the second frame which could not be recorded at this time are converted into the high frequency data of the first frame and the data of the second frame by using the header information, the address and the pointer to prevent the error propagation. It was mixed and recorded.

[0003]

However, in the above-mentioned conventional recording apparatus, when the high frequency data of the first frame and the second frame are recorded, the header information, the address and the pointer are used for each predetermined unit. Since the additional information to be recorded becomes redundant and the high frequency component of the first frame and the data of the second frame are mixed at the time of reproduction, there is a drawback that it is difficult to output the reproduction data of the first frame.

The present invention solves the above-mentioned conventional problems, and a digital signal recording device for effectively reducing and recording additional information for recording and a digital signal reproducing device for efficiently reproducing a video signal. The purpose is to provide.

[0005]

According to the invention of claim 1 of the present application, each frame in two consecutive first and second frames of a video signal is divided into k blocks constituting a screen, and k is divided into k blocks.
High-efficiency encoding is performed in one encoding unit composed of m blocks (k is an integer multiple of m) in each block, and the high-efficiency encoded coding unit is composed of a predetermined number of bytes in the track. A digital signal recording device for recording in a plurality of sync blocks of a recording medium, in which data of a first frame in two frames is recorded in a sync block of a first group of tracks constituted by a continuous specified number of tracks. The first recording means for recording and the frame information indicating the first frame are recorded at a predetermined position in the sync block, and
Second recording means for recording the data of the first frame, which could not be recorded in the track 1 by the recording means, in the sync block in the second group of tracks, which is a plurality of tracks continuous with the first group of tracks; When recording the data of the second frame in the sync block recorded by the recording means, a pointer indicating the position to start recording in the data recording area is recorded at a predetermined position in the data recording area, or the second recording is performed. When recording the data of the second frame in the sync block not recorded by the means, the frame information indicating that the data to be recorded is that of the second frame is recorded at a predetermined position in the sync block, and the second frame is recorded. When recording the frame data from the beginning of the coding unit, set the pointer that indicates the recording start position in the data recording area in the sync block to the data. A third recording means for recording at a predetermined position in the recording area, recording an address uniquely determined for the coding unit, and then recording the second frame data. To do.

The invention of claim 6 of the present application is a digital signal reproducing apparatus for reproducing and encoding the data recorded by the digital signal recording apparatus according to claim 1 and recorded on the tracks of the first and second groups. And the first and second memories,
A data synthesizing circuit for synthesizing the data of the first frame based on the low frequency component and the high frequency component of the first frame, and a LAC recording the low frequency component of the first frame from the track of the first group
First reproducing means for reproducing the sync block data and writing the low-frequency component of the first frame in the first memory; and reproducing the sync block data in the second group of tracks for the frame information and the pointer. By reading, the HAC sync block in which each sync block records the high frequency component of the first frame, or the high frequency component of the first frame and the second high frequency component
MIX sync block in which all band components of the frame are recorded, or IN in which all band components of the second frame are recorded
In the case of the HAC sync block or the MIX sync block, the information detecting means for determining which sync block of the TER sync block is output, and in the case of the HAC sync block or the MIX sync block, the high frequency component of the reproduced first frame is output to the data synthesizing circuit, and MIX. In the case of a block or an INTER sync block, second reproducing means for writing all band components of the reproduced second frame into the second memory, and output from the data synthesizing circuit and output from the second memory And a high-efficiency decoding circuit for highly-efficiently decoding the first and second frame data.

[0007]

According to another aspect of the digital signal recording apparatus of the present invention, the low frequency component of the first frame is recorded in the sync block of the first group of tracks together with the frame information indicating the first frame. There is. Then, the high frequency component is recorded in the sync block in the second group of tracks, and when the data of the second frame is recorded in the same sync block, the pointer is simultaneously recorded. Further, when recording the data of the second frame that does not coexist with the first frame, the frame information indicating that the recording data is the second frame data and the pointer indicating the start position in the data recording area are recorded, and the unit of encoding is set. On the other hand, a uniquely determined address is recorded and the data of the second frame is recorded in the sync block in the second group of tracks.

According to a sixth aspect of the digital signal reproducing apparatus of the present invention, the reproduction data read from the first group of tracks is recorded in the first group.
, The data of the HAC sync block in which the high frequency component of the first frame is recorded is output to the data synthesizing circuit. The data synthesizing circuit reads the data of the first memory and synthesizes the data of the first frame based on the high band and low band signal components of the first frame. In the sync block of all band components of the second frame, the data is once written in the second memory. The output of the data synthesizing circuit and the data read from the second memory are decoded by the high efficiency decoding circuit.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital signal recording device according to a first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a digital signal recording device. In the figure, a digital image signal is input to the input terminal 1,
It is input to the high efficiency encoding circuit 3 via the shuffling circuit 2. The high-efficiency coding circuit 3 is, for example, a circuit that codes the first frame by intra-frame coding and the second frame by inter-frame differential coding using motion guarantee, and outputs the same to the memory write control circuit 4. Is entered. The memory write control circuit 4 is a control circuit for writing the encoded data in the memories 5 and 6. An additional information generating circuit 7 for simultaneously writing additional information is connected to these memories. The memory 5 is a memory for holding the data to be recorded on the track T1 of the first group for recording the low frequency component of the first frame described later, and the memory 6 records the high frequency component of the first frame and the second frame. Track T of the second group
This is a memory that temporarily holds the data to be written in 2.
The outputs of these memories 5 and 6 are recorded on the magnetic tape 9 via the recording control writing 8.

Next, the operation of the digital signal recording apparatus according to this embodiment will be described. First, the processing of the first frame will be described. The video signal of the first frame input from the input terminal 1 is converted into a coding unit by the shuffling circuit 2, high efficiency coded by the high efficiency coding circuit 3, and output to the memory writing control circuit 4. .

In the memory write control circuit 4, FIG.
As shown in (e), the data encoded in sync block units is recorded in the memories 5 and 6. In the sync block of FIG. 3A, sync for synchronization, ID that is information indicating that data in the sync block is related to data in the sync block, such as what frame of data is high, Qn which is the quantization information of the data in the sync block obtained by the efficiency encoding circuit 3.
o. , STA indicating modification information in the sync block, additional information such as parity which is an error correction code are recorded at a predetermined position, and the data of each DCT block is recorded in the data recording area in order from a visually important low frequency area. R. Thus, FIG.
As shown in (a), data is sequentially recorded in an area having the same size as the sync block of each track of the memory 5. In the memory 5, all sync block areas in the first group of tracks T1 consisting of n tracks in FIG. 2 correspond to the areas of the memory 5. Then, the same processing is repeated until the memory 5 is completely occupied.

Next, the writing of the high frequency data which is the data of the first frame which could not be written in the memory 5 at this time will be described. As shown in FIG. 3 (b) or FIG. 3 (c), the high frequency data is s for synchronizing the sync blocks.
sync, an ID indicating information about data in the sync block, F1 that is frame information indicating that the data is the first frame, PN that indicates the number of pointers in the sync block, and additional information such as parity that is an error correction code. At a predetermined position, the high-frequency data collected in coding units is written in the data recording area, and an area having the same size as the sync block determined for each coding unit in the memory 6 is written as one sync block. Go. FIG. 3B is a sync in which only the high frequency component of the first frame is written, and FIG. 3C is a sync in which the high frequency component of the first frame and a part of the second frame are written in the same sync block. The recording state of the block is shown.

Next, the processing of the second frame will be described. The video signal of the second frame input from the input terminal 1 is input to the memory write control circuit 4 via the shuffling circuit 2 and the high efficiency encoding circuit 3. In the memory write control circuit 4, as shown in FIG. 3 (c), when writing is continued to the data of the first frame, the pointer indicating the position to start the input of the second frame in the data recording area is set to the data recording area. The data of the second frame is written in the remaining space of the recording area. Further, as shown in FIG. 3D, when writing from the beginning of the data recording area, F2 which is frame information indicating that it is the data of the second frame is written, and the data of the second frame is written in the data recording area. I will write it.

Next, the processing when the coding unit of the second frame is changed in the middle of the data recording area will be described below. Figure 3
(D) and FIG. 3 (e) respectively show 1 in the middle of the data recording area.
It is an input example when the encoding unit is changed once or twice.
As shown in the figure, every time the coding unit is changed,
The pointer to be recorded increases by one. In this embodiment,
Data writing of the second frame is performed after writing an address indicating the number of the coding unit at the beginning of each segment in order to prevent error propagation.

In the recording control circuit 8, the data written in the memory as described above is stored in the video signal recording area of the track T1 for recording the first frame in FIG. Data is recorded on the track T2 for recording the first frame high band and the second frame in FIG. At this time, the data recording area on the memory and the sync block on the track have a one-to-one correspondence.

Here, the memory write control circuit 4 of the present embodiment.
The low-frequency data of the first frame of the two frames is written in the memory 5 by the memory write control circuit 4 and the track T is composed of a specified number of continuous tracks via the recording control circuit 8.
A first recording means 4a for recording in a sync block in 1;
When recording the high frequency data of the first frame which could not be recorded on the track T1 by the first recording means, various information such as F1 which is the frame information indicating that the data of the first frame is recorded in the memory 6. The high frequency data of the first frame, which could not be recorded by the first recording means, is stored at a predetermined position in the memory 6
It has a second recording means 4b for recording in the internal data recording area. Further, when the memory writing control circuit 4 writes the data of the second frame in the two frames to the recording area in the memory 6 in which the high frequency data of the first frame is recorded, the position in the data recording area where the recording is started. Is written at a predetermined position in the data recording area, or is written in any other data recording area in the memory 6, the frame information F2 or the like indicating that the data to be written is for the second frame. When various information is recorded in a predetermined position of the data recording area in the memory 6 and the data of the second frame is recorded from the beginning of the coding unit, it indicates the position in the data recording area of the memory 6 where recording is started. The pointer is written at a predetermined position in the data recording area, the address uniquely determined for the coding unit is written, and then the data of the second frame is changed to the data in the memory 6. Writing the recording area, it is provided with a third recording means 3c for recording the sync blocks in a track T2 of the data in the memory 6 via the recording control circuit 8 continues in the same number as the track T1.

By doing so, since the frame information of the data in the sync block is recorded at a predetermined position in the sync block in the track T2, even if a sync block in which the data cannot be read occurs when an error occurs. When the pointer existing in the sync block records both the first frame and the second frame of the data in the sync block, only the address of the recording start position of the second frame and the second frame are recorded. In this case, the recording position of the address recorded to prevent the error propagation of the second frame will be known. Therefore, it is possible to reduce the amount of additional information that has been conventionally required.

Next, a digital signal reproducing apparatus according to a second embodiment of the present invention will be described with reference to the drawings. First, it is assumed that image information as shown in FIG. 2 is written on the magnetic tape 11 by the digital signal recording apparatus of the first embodiment. In FIG. 4, a signal is reproduced from the magnetic tape 11 by the data reproducing circuit 12, and the memory write control circuit 13
Entered in. As will be described later, the memory writing control circuit 13 writes the sync block in which the low frequency component of the first frame is recorded in the first memory 14, and the high frequency component of the first frame to the data synthesis circuit 16 and the second frequency component. The entire band component of the frame is controlled to be written in the second memory 15. The data synthesizing circuit 16 is a circuit for synthesizing the data read from the memory 14 and the high frequency data sent from the memory writing control circuit 13 for each coding unit, and the output thereof is a high efficiency decoding circuit. Given to 17. The high-efficiency decoding circuit 17 decodes the combined data of the data combining circuit 16 and the data output for each decoding unit of the second frame for each decoding unit of each frame. The output is configured to be output from the output terminal 19 via the deshuffling circuit 18.

Next, the operation of this embodiment will be described. The data reproducing circuit 12 sequentially reproduces the data recorded on the tracks of the magnetic tape 11 as shown in FIG. 2, and inputs the data to the memory writing control circuit 13. In the memory writing control circuit 13, the data of the LAC sync block of the low frequency component of the first frame recorded on the n tracks of the track T1 is sequentially written in the memory 14, and the additional information regarding the first frame is efficiently decoded. Output to 17. The data recorded on the next n tracks of the second track T2 is also sequentially reproduced by the data reproducing circuit 12 and input to the memory writing control circuit 13. The memory writing control circuit 13 reads the frame information and the pointer existing at a predetermined position, and when the frame information indicates the first frame and there is no pointer, the high frequency component of the first frame is recorded.
AC sync block, MIX sync block in which the high frequency component of the first frame and the second frame are mixed when the frame information indicates the first frame and there is a pointer,
IN when the frame information indicates the second frame
It is determined to be a TER sync block, and control is performed as follows. Data synthesis circuit 1 in case of HAC sync block
6, the data of the first frame is sent to the data synthesizing circuit 16 in the case of the MIX sync block,
The data of the frame is written in the memory 15, and in the case of the INTER sync block, the data is written in the memory 15.
Here, the writing locations in the memory 14 and the memory 15 are uniquely determined in the encoding unit. The high frequency component of the first frame is recorded for each coding unit in the maximum number of consecutive HAC sync blocks and MIX sync blocks. Therefore, in the data synthesis circuit 16, for each coding unit,
The data from the memory 14 and the high frequency data of the first frame sent from the memory writing control circuit 13 are combined. At this time, the data related to the high-efficiency decoding of the second frame is output to the high-efficiency decoding circuit 17. In the high-efficiency decoding circuit 17, the data output from the data synthesizing circuit 16 or the memory 15 for each decoding unit is enhanced by using the information for decoding sent for each decoding unit of each frame. The data is efficiently decoded and output to the deshuffling circuit 18. The deshuffling circuit 18 restores the high-efficiency decoded data, which is a decoding unit, to the state of a normal television signal and outputs it from the output terminal 19.

Here, the memory write control circuit 13 of the digital signal reproducing apparatus of the present embodiment has the first reproducing means 13a for writing the data of the LAC sync block recorded on the track T1 in the first half into the memory 14, and the latter part. Information detecting means 13b for reading the frame information and the pointer recorded at a predetermined position in the sync block recorded on the track T2.
Then, the type of the sync block is determined from the frame information and the pointer, and the data of the first frame is transferred to the data synthesizing circuit 1
The data of the second frame is output to memory 6 and synthesized, and the data of the second frame is stored in the memory 1
The second reproducing means 13c for writing data into the recording medium 5 is provided. Since the high-frequency data of the first frame is recorded from the sync block that is uniquely determined for each decoding unit, the processing in the data synthesizing circuit 16 can be performed for each decoding unit.
The output control of the frame can be easily performed.

In this embodiment, the high-efficiency coding is optional and motion compensation may be used. The type and arrangement of the additional information provided for each sync block are arbitrary.
Further, although the number of tracks for recording the data of the first frame, the high frequency band of the first frame and the data of the second frame is the same, the number may not be the same. However, in the case of the same number, the output timing is easier and the circuit configuration is easier. Also, by determining the maximum number of sync blocks for recording the high frequency band of the first frame, the circuit configuration becomes easy.

[0022]

As described above, since the digital signal recording apparatus of the present invention records the frame information of the data in the sync block at a predetermined position in the sync block in the second group of tracks, when an error occurs Even if a sync block in which the data cannot be read occurs, the recording position of the data in the sync block can be known by the pointer existing in the sync block. When both the first frame and the second frame are recorded, only the second frame at the recording start position of the second frame is recorded to prevent the error propagation of the second frame. You can see the recording position of the address. Therefore, the amount of additional information required conventionally can be reduced, and the coding efficiency can be improved.

The digital signal reproducing apparatus of the present invention is the first
Since the high band data of the frame is recorded from the sync block that is uniquely determined for each decoding unit, the first frame can be output for each decoding unit, and the output control of the first frame can be performed more easily than before. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital signal recording device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a track arrangement for recording data of 2 frames in the embodiment of the present invention.

FIG. 3 is a diagram showing data recorded in a sync block according to an embodiment of the present invention.

FIG. 4 is a block diagram of a digital signal reproducing device according to a second embodiment of the present invention.

[Explanation of symbols]

 1 Input Terminal 2 Shuffling Circuit 3 High Efficiency Coding Circuit 4, 13 Memory Writing Control Circuit 4a First Recording Means 4b Second Recording Means 4c Third Recording Means 5, 6, 14, 15 Memory 7 Additional Information Generating Circuit 8 Recording control circuit 9, 11 Magnetic tape 12 Data reproducing circuit 13a First reproducing means 13b Information detecting means 13c Second reproducing means 16 Data combining circuit 17 High efficiency decoding circuit 18 Deshuffling circuit 19 Output terminal

Claims (8)

[Claims] 1. A frame in each of first and second continuous two frames of a video signal is divided into k blocks constituting a screen, and m blocks in the k blocks (k is an integer multiple of m) High-efficiency encoding is performed in one encoding unit composed of the blocks, and the high-efficiency-encoding encoding unit is applied to a plurality of sync blocks of a recording medium constituted by a predetermined number of bytes in a track. In a digital signal recording device for recording, a first recording means for recording the data of the first frame in the two frames in a sync block of a first group of tracks constituted by a continuous specified number of tracks; The frame information indicating the presence is recorded at a predetermined position in the sync block, and
Second recording means for recording the data of the first frame, which could not be recorded in the track 1 by the recording means, in a sync block in a second group of tracks having a plurality of tracks continuous with the first group of tracks; , In the sync block recorded by the second recording means,
When recording the data of the second frame, a pointer indicating the position to start recording in the data recording area is recorded at a predetermined position in the data recording area, and is not recorded by the second recording means. When recording the data of the second frame in the sync block, frame information indicating that the data to be recorded is that of the second frame is recorded at a predetermined position in the sync block, and the frame information of the second frame is recorded. When recording data from the beginning of the encoding unit, a pointer indicating the position to start recording in the data recording area in the sync block is recorded at a predetermined position in the data recording area, and the pointer is recorded in the encoding unit. And a third recording means for recording the address of the second frame and then recording the data of the second frame. Digital signal recording apparatus as. 2. The digital signal recording device according to claim 1, wherein the number of the tracks of the second group is the same as the number of tracks of the tracks of the first group, and is continuous with the tracks of the first group. . 3. The sync, which is uniquely determined in the coding unit in the track 2 when the second recording means records the data of the first frame that could not be recorded in the track 1. 3. The digital signal recording apparatus according to claim 1, wherein recording is performed from a block to a maximum number of consecutive sync blocks. 4. The digital signal recording device according to claim 1, wherein the frame information is recorded in an area before the data recording area in the sync block. 5. The high-efficiency encoding of the input video signal is intraframe encoding for the first frame, and interframe differential encoding using motion compensation for the second frame. The digital signal recording device according to claim 4. 6. A digital signal reproducing apparatus for reproducing and encoding data recorded by the digital signal recording apparatus according to claim 1 and recorded on the first and second groups of tracks. Memory, a data synthesizing circuit for synthesizing the data of the first frame based on the low-frequency component and the high-frequency component of the first frame, and a LAC sync recording the low-frequency component of the first frame from the tracks of the first group. Reproducing the block data and writing the low-frequency component of the first frame into the first memory;
A reproducing unit and an HAC sync block in which each sync block records the high frequency component of the first frame by reproducing the sync block data in the second group of tracks and reading the frame information and the pointer, or Information detecting means for determining which of the MIX sync block in which the high band component of the first frame and the full band component of the second frame are recorded or the INTER sync block in which the full band component of the second frame is recorded In the case of the HAC sync block or the MIX sync block, the reproduced high frequency component of the first frame is output to the data synthesis circuit, and in the case of the MIX block or the INTER sync block, it is reproduced. Second reproducing means for writing all band components of the second frame in the second memory, A high-efficiency decoding circuit for highly-efficiently decoding the first and second frame data obtained from the output of the data synthesizing circuit and the output of the second memory. . 7. A high-frequency component of the first frame is changed from a sync block uniquely determined in a decoding unit, which is a unit for high-efficiency decoding, to a maximum number of continuous sync blocks determined. 7. The digital signal reproducing apparatus according to claim 6, which is recorded. 8. The high frequency component of the first frame having the same decoding unit recorded in a plurality of consecutive sync blocks, and the first frame of the first memory, in the data synthesizing circuit. 7. The low-frequency components of the same decoding unit of 1 are combined at one time.
The described digital signal reproducing device.