JP4389401B2 - Digital audio recording device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for simplifying a recording apparatus for producing a recording apparatus corresponding to a different field frequency based on the system when an audio data recording apparatus corresponding to a certain field frequency exists. For example, the present invention relates to a method for simplifying the audio portion of a VTR recording apparatus. However, the present invention is not limited to the VTR.
[0002]
[Prior art]
The VTR recording / reproducing apparatus needs a digital magnetic recording / reproducing apparatus that can support, for example, each of the HDTV systems in Japan, the United States, and Europe in order to record and reproduce signals of a plurality of different television standards. HDTV, which provides higher-definition images than the current television, was developed by Japan ahead of the world. The Japanese HDTV system is called high-definition, and has 1125 scanning lines and a field frequency of 60 Hz. On the other hand, in Europe and the United States, the HDTV system is different from the Japanese system. For example, the European system has a field frequency of 50 Hz.
[0003]
In this way, if the television system is different and the equipment for producing and transmitting the program is different, the individual equipment has to be developed and manufactured for each, which increases the cost. Also, in order to screen software produced by other methods, it is necessary to prepare a VTR suitable for each method, convert the signal with a separate format converter, and then re-record it. Costs too much.
[0004]
In the first place, a VTR is one of the main equipment for production and transmission, and generally a VTR for broadcasting is expensive. Therefore, a common tape transport, signal processing circuit, cassette and tape are used in different HDTV systems. If it can be used, the equipment cost and running cost will be reduced, which will greatly benefit the user. In addition, there is an advantage that program conversion between countries can be easily performed at a low cost if it is possible to reproduce a tape recorded by another method using the same VTR.
[0005]
[Problems to be solved by the invention]
However, in the conventional magnetic recording apparatus, there has been no apparatus capable of recording audio with high definition images by different HDTV systems by a common mechanism. When considering a device corresponding to a different frequency, a format is required for each different frequency, and a processing device corresponding to each field frequency is required. For example, if the audio input / output sampling frequency is 48 KHz and the number of bits per sample is 24 bits in both 60 Field / s and 50 Field / s devices, the audio format must be considered at 800 samples / field × 24 bits / sample at 60 Field / s. In 50 Field / s, the audio format must be considered as 960 sample / field × 24 bit / sample. The total number of bits per field is greatly different between 800 × 24 = 19200 bits / field and 960 × 24 = 223040 bits / field. Therefore, devices corresponding to different field frequencies have to have completely different formats and completely different devices.
[0006]
Therefore, according to the present invention, when a digital audio recording apparatus serving as a basic apparatus corresponding to a certain field frequency is present, audio data having a different field frequency is converted to match the format of the basic apparatus and changed to an appropriate processing rate. Accordingly, it is a general object to realize a device corresponding to different field frequencies based on the basic device. In particular, when there is an audio recording device as a basic device corresponding to a certain field frequency, when converting audio data of a different field frequency so as to conform to the format of the basic device, at that time in the processing circuit for ECC encoding Therefore, a specific object is to provide a corresponding method by adding a simple circuit.
[0007]
[Means for Solving the Problems]
In order to solve the above-described problems of the prior art and achieve the object of the present invention, the following measures were taken. That is, the present invention Audio data input from the outside and accompanying the video signal having the first field frequency; Predetermined sampling frequency Number And having Predetermined Specifies the data array and bit array of each field First An input unit that receives audio data based on the format and performs at least baseband processing of the audio data; a predetermined sampling frequency; Second With field frequency Predetermined Specifies the data array and bit array of each field Second It is designed to process audio data based on the format and operates with a clock according to a predetermined sampling frequency. Second In a digital audio recording apparatus comprising: a processing unit including an encoding unit that performs encoding processing for error correction of audio data that conforms to a format; and an output unit that writes audio data output from the processing unit to a recording medium ,place The science department has a built-in conversion means for audio data. First The field frequency is Second Unlike field frequency and First Format is Second When different from the format , Strange The alternative means is First Convert format Second Audio data is passed to the encoding means after conforming to the format , Marks The encoding means operates with a clock according to a predetermined sampling frequency, First With field frequency Second While putting a pause at any time in proportion to the ratio to the field frequency, Second Encoding for error correction of audio data adapted to the format is performed. In particular , Strange The conversion means rearranges the number of samples per field and the number of bits per sample while maintaining the total number of bits per field determined by the product of the number of samples per field and the number of bits per sample. First Format Second Convert to format. More specifically, , Strange Alternative means Second It has a bit number register corresponding to the number of bits per sample on the format side, and consists of a bit stream of serially arranged samples First While cyclically writing format audio data to the register, First The number of bits per sample on the format side Second The audio data is cyclically read out from the register while pausing at any time according to the ratio with the number of bits per sample on the format side, and the number of samples per field and the number of bits per sample are rearranged. First Format Second Convert to format.
[0008]
In the audio recording apparatus according to the present invention, audio data format conversion processing is performed by a processing circuit for ECC encoding. Audio data format conversion is performed by the ECC encoding processing circuit, and only the audio clock used for the baseband side is input to the ECC encoding processing circuit. For example, even when a VTR with a field frequency of 50 Field / s and a baseband side audio processing clock of 48 KHz is created based on a VTR with a field frequency of 60 Field / s and a baseband side audio processing clock of 48 KHz, only 48 KHz is input as the audio clock. To do. 48 KHz × 50/60 = 40 KHz is not necessary.
[0009]
Audio data format conversion is performed immediately after input to the ECC encoding processing circuit. Audio data conversion is performed by providing a register for the number of bits per audio baseband sample of the base recording device, and cyclically writing to and reading from the register using LSB fast or MSB fast. Perform the conversion. Also, the read side puts a read break in order to match the data rate on the write side. For example, when a device having a field frequency of 50 Field / s and 960 samples / field × 20 bits / sample is made for a device based on a field frequency of 60 Field / s and 800 samples / field × 24 bits / sample, the ECC encoding processing circuit uses 24. The number of registers (for 24 bits) is provided, where the LSB fast is cyclically written to the register at 20 bits / sample, the LSB fast is read from the register at 24 bits / sample, and the format conversion of the audio data is realized. The reading side rests reading once every 6 samples.
[0010]
The control to the circuit after the audio data format conversion is extended in response to the audio data format conversion register read. That is, the internal counter operation for the control signal is rested according to the rest of the audio data format conversion register reading. For example, when a device having a field frequency of 50 Field / s is made for a device based on a field frequency of 60 Field / s, reading of the format conversion register of 1 sample audio data is taken off every 6 samples. At the same time, the control signal internal counter is also closed. Therefore, the cycle of the control signal is 6/5 of 60 Field / s, and the processing performed at 800 fields / s and 800 samples (1 field) takes 960 samples (1 field) at 50 Field / s and the same processing is performed. become.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
The present invention is a system that simplifies a device when a recording device corresponding to a different field frequency is made based on the system when a recording device having a certain field frequency exists. As a specific example, a VTR recording / reproducing apparatus is taken as an example, and hence the term “recording / reproducing apparatus” will not be used. However, the present invention is not limited to the VTR.
[0012]
FIG. 1 is a block diagram of a VTR corresponding to a field frequency of 60 Field / s. This is the basic VTR. (A) shows the recording side, and (B) shows the reproduction side. The input video signal is sent to the video baseband processing unit 1. The video baseband processing unit 1 operates with a 74.25 MHz clock. Here, brightness, chroma, etc. are controlled. The signal processed by the video baseband processing unit 1 is sent to the video compression unit 2. Here, the video signal is compressed, put on a 46.4 MHz clock, and sent to the ECC encoding & audio / video combination unit 4.
[0013]
On the other hand, the input audio signal has a sampling frequency of 48 KHz. When the number of samples per field is calculated, 48K / 60 = 800 sample / field. One sample is 24 bits. This input audio signal is sent to the audio baseband processing unit 3 for audio baseband processing. For example, gain adjustment or the like is performed here. The signal processed by the audio baseband processing unit 3 is sent to the ECC encoding & audio / video combination unit 4. The ECC encoding & audio / video combining unit 4 generates an error correction code (ECC) for each of audio and video, adds C1 and C2 parities, and performs data processing to match the tape format. The input clock of the ECC encode & audio / video combination unit 4 is 46.4 MHz for video and 48 KHz for audio. The output is 94 MHz serial data as tape recording data.
[0014]
The audio input data of the ECC encoding & audio / video combination unit 4 is serial and is sent in 1 sample 64 bits. An audio serial data format is shown in FIG. As can be seen here, the serial data is sent in the AES / EBU format with two channels mixed. Z, M, J, E, V, U, C, and P are flags, respectively, and main line data is sent in LSB fast. FIG. 2 shows a data format of 24 bits / sample and 20 bits / sample. Thus, the audio input of the ECC encode & audio / video combination unit 4 is serial data. In FIG. 1, 48 KHz is written, which means that when one sample is counted as one clock, the rate is 48 KHz, that is, the sampling frequency. Since the audio input of the ECC encode & audio / video combination unit 4 is serial data, it is 48 KHz × 64 bits / sample = 3.072 MHz when written at the clock frequency of the serial data. However, the sampling frequency, which is a frequency with 1 sample as one unit, is important for audio. In this example, 1 sample is accidentally sent in 64-bit serial, but it may be sent in 256 bit. For this reason, only 48 KHz, which is important in FIG. 1, is described, and the audio clock is described by the sampling frequency before this.
[0015]
The signal generated by the ECC encoding & audio / video combination unit 4 is recorded on the tape. The signal reproduced from the tape is input to the ECC decode & audio / video separation unit 5. The ECC decode & audio / video separating unit 5 separates the audio and video data, and then decodes (decodes) the error correction code to perform error correction. The video data is output on a clock of 46.4 MHz and input to the video decompression unit 6. In the video decompression unit 6, the compression is released and a video baseband signal is output. This signal is sent to the video baseband processing unit 7. The video baseband processing unit 7 controls the brightness, chroma, etc., and then outputs a VTR. On the other hand, the audio is subjected to error correction processing by the ECC decoding & audio / video separation unit 5 and then output from the ECC decoding & audio / video separation unit 5 in the audio baseband. At this time, the number of samples per field and the number of bits per sample are 800 samples / field and 24 bits / sample. This signal is sent to the audio baseband processing unit 8 at a sampling frequency of 48 KHz. The audio baseband processing unit 8 performs output audio gain control and the like. This signal becomes the VTR output audio.
[0016]
FIG. 3A is a video recording format diagram with a field frequency of 60 Field / s. One field is composed of six tracks, and one track constitutes a video 1 ECC (error correction code) block (product code). Since there are 6 Tracks / Fields, the video has 6 ECC blocks / field. V in the tape footprint diagram of FIG. 3A represents video, and the video is divided into two sectors on one track. One ECC block of video is 250 sync / track, and 125 syncs are provided per sector, and 250 syncs are provided for two sectors. That is, there is 250 Sync data in one track, and this ECC block configuration is as shown in FIG. One sync means one piece of data in the C1 direction of the ECC block. The C1 ECC parity is 12 bytes, and the C2 ECC parity is 24 bytes. Video data is compressed data.
[0017]
FIG. 4 is an audio recording format diagram with a field frequency of 60 Field / s. In the tape footprint diagram shown in FIG. 4A, A0 represents the audio channel 0, A1 represents the audio channel 1, A2 represents the audio channel 2, and A3 represents the audio channel 3. The audio ECC block configuration is composed of one field for each audio channel. Audio is recorded on a track by 4 Sync per channel. Therefore, collecting 6 tracks of data for one field results in 4 Sync / track channel × 6 Track / Field = 24 Sync / field channel, which constitutes an ECC block of one audio channel. As shown in FIG. 4B, an audio ECC block is configured, and 12 bytes are allocated as the C1 ECC parity and 12 bytes are allocated as the C2 ECC parity. Since there are 24 bits per audio sample, this is divided into 8 bits × 3 symbols. As shown in FIG. 4 (B), 1 Sample is configured to enter from the MSB as 3 bytes of data in the same Sync. Since one field contains 800 sample data, a data frame for 4 samples is left in the ECC block, but user data is allocated here. Audio sample data contains uncompressed data.
[0018]
FIG. 5 is a block diagram of a VTR that realizes a field frequency of 50 Field / s. (A) shows the recording side, and (B) shows the reproduction side. This VTR is based on the VTR having a field frequency of 60 Field / s shown in FIG. The video compression unit 2, audio baseband processing unit 3, ECC encoding & audio / video combining unit 4, ECC decoding & audio / video separation unit 5, video decompression unit 6 and audio baseband processing unit 8 are all basic 60 Fields. Use exactly the same block as the / s compatible VTR. Each of the video baseband processing unit 1 ′ and the video baseband processing unit 7 ′ is a baseband processing block for video encoding / decoding, but has a processing clock of 74.25 MHz and a video base having a base field frequency of 60 Field / s. Since the processing clocks of the band processing unit 1 and the video baseband processing unit 7 are the same and almost the same processing can be used, the video baseband processing unit 1 ′, the video baseband processing unit 1, and the video baseband processing unit 7 are actually used. 'And the video baseband processing unit 7 have almost no circuit difference.
[0019]
The video clock converter 11 is a clock converter whose output is 61.875 MHz which is 50/60 times the field frequency ratio with respect to the input 74.25 MHz. This example considers high-definition, and the video effective frame area is a picture frame of 1920 sample × 1080 line (or 1440 sample × 1080 line) in both cases of the field frequencies of 50 Hz and 60 Hz. The difference between the effective picture frames at 50 Hz and 60 Hz is as follows. Therefore, even if the frequency is 61.875 MHz which is 50/60 times, the invalid area is simply discarded, and all the valid area becomes valid data as it is.
[0020]
FIG. 6 shows the difference between each field frequency and the image frame in the processing process. (A) shows an image frame with a field frequency of 60 Hz, (B) shows an image frame with a field frequency of 50 Hz, and (C) shows an image frame (signal form) after processing the image frame with a field frequency of 50 Hz by the video clock converter 11. . Thus, the signal form (C) after processing by the video clock converter 11 is exactly the same as the signal form (A) of 60 Field / s and 74.25 MHz including the invalid region.
[0021]
The 61.875 MHz output signal output from the video clock converter 11 is sent to the video compression unit 2. If the output clock is set to 38.666 MHz which is 50/60 times, the clock and the data rate are only 50/60 times for the video compression unit 2, and the processing is exactly the same as the base 60 Field / s VTR. . In other words, it can be said that the role of the video clock converter 11 is to perform the processing after the video clock converter 11 at the rate of 50/60 times exactly the same as the base 60 Field / s compatible VTR.
[0022]
On the other hand, on the audio side, the audio data pack unit 9 performs the same function as the video clock converter 11 on the video side. As shown in FIG. 5, the audio data pack unit 9 converts 48 KHz, 960 sample / field × 20 bits / sample (= 19200 bits / field) into 40 KHz, 800 sample / field × 24 bits / sample (= 19200 bits / field). . Both of these audio data can be converted because the total number of bits per field is the same as 19200 bits / field. Here, 40 KHz = 48 KHz × 50/60, and the audio side can perform exactly the same processing as the base field frequency 60 field / sVTR at a rate of 50/60 times after the audio data pack unit 9.
[0023]
FIG. 7 shows a detailed configuration of the audio data pack unit 9. As can be seen from FIG. 7A, the audio data pack unit 9 includes a FIFO control and a FIFO unit. One sequence of the data pack is 48 samples (20 bits / sample) and 6 samples. Although 20 bits / sample × 6 samples = 120 bits, this is converted into 120 bits = 24 bits / sample × 5 samples in a 40 KHz system (24 bits / sample). Audio data is serially input to the audio data pack unit 9, and is written in 1 bit serial at 48 × 48 KHz of 48 KHz system. At this time, the Z, M, J, E, V, U, C, and P flags are not written in the FIFO, but only the data is written in the FIFO. This is read out serially by 1 bit at 40 × 40 KHz 64 × 40 KHz. However, the flag portion is cleared to 0 without being read from the FIFO (the flag is meaningless data in the subsequent stage). Reading is performed for each sample with 24 bits as 1 sample and sent to the ECC encoding & audio / video combination unit 4. As shown in FIG. 7B, the start point of the sequence is performed at the beginning of the field. As this control signal, the audio data pack unit 9 receives a signal Field-Start indicating the head of the field. FIG. 7B shows how data packs are written to and read from the FIFO. The reason why the FIFO is delimited by 4-bit squares is to make it easier to understand the state of 20-bit-> 24-bit conversion. Actually, it is written every 1 bit as described above, and every 1 bit. It has been read. As for Field-Start, when converting from 48 KHz system to 40 KHz system, the FIFO control in the audio data pack unit 9 outputs a signal Field-Start, and indicates information indicating where the field head is in the converted 40 KHz system. put out. Based on this information, the ECC encoding & audio / video combination unit 4 separates audio field breaks and cuts out audio data to create an ECC block.
[0024]
The video input and audio input of the ECC encoding & audio / video combination unit 4 shown in FIG. 5 are both 50/60 times the rate compared to the case of 60 Field / s. Since the output of the ECC encoding & audio / video combining unit 4 is also 50/60 times the rate, the ECC encoding & audio / video combining unit 4 processes exactly the same processing as in the case of 60 Field / s at a rate of 50/60 times. Will do. As a matter of course, the same circuit can be used in the case of 60 Field / s and 50 Field / s. Then, it is recorded on the tape at a rate of 50/60 times. At this time, the tape running speed, the drum rotation speed, etc. are all 50/60 times the field frequency ratio compared to the case of 60 Field / s. Therefore, the footprint is the same for the base field frequency 60 Field / s VTR and the 50 Field / s VTR.
[0025]
On the other hand, in tape reproduction, data at a rate of 50/60 times the basic field frequency 60 Field / s is input to the ECC decode & audio / video separation unit 5. The ECC decode & audio / video separation unit 5 performs processing at a rate 50/60 times that of 60 Field / s. For this reason, both video output and audio output have a rate 50/60 times that of 60 Field / sVTR. As a matter of course, the ECC decoding & audio / video separation unit 5 is exactly the same processing as in the case of 60 Field / s and only has a different rate, so the same circuit as 60 Field / s can be used. The video output of the ECC decode & audio / video separation unit 5 enters the video decompression unit 6. The video decompression unit 6 also has an input / output processing rate of 50/60 times that of 60 Field / s. Of course, the same circuit can be used as in the case of 60 Field / s. Here, the video clock converter 12 on the reproduction side performs the reverse function of the video clock converter 11 on the recording side. The video clock converter 12 returns from 61.875 MHz, which is a 50/60 rate of 60 Field / s, to 74.25 MHz. As shown in FIG. 6, the effective area does not change, and the invalid area (blanking part) increases to 74.25 MHz. The video baseband processing unit 7 ′ performs video baseband processing and adjusts brightness, chroma, and the like. The field frequency 50 Field / s output of the video baseband processing unit 7 ′ becomes the VTR output.
[0026]
On the other hand, the audio is subjected to error correction processing by the ECC decoding & audio / video separation unit 5 and then input to the audio data depacking unit 10 in a state where the data is packed at 40 KHz, 800 sample / field × 24 bits / sample. The audio data depack unit 10 unwinds the data pack by performing the reverse function of the audio data pack unit 9 and restores the original 48 KHz, 960 sample / field × 20 bits / sample. Details of the audio data depacking unit 10 are shown in FIG. As shown in FIG. 6A, the signal Field-Start indicating the field head is correctly transmitted even if the data is converted from 40 KHz to 48 KHz by the FIFO control as in the audio data pack unit 9. The signal Field-Start on the writing side is a very important signal as the starting point of the data depacking sequence. As in the case of the audio data pack unit 9, the sequence is 5 samples × 24 bits / sample = 120 bits for the 40 KHz system (write side), and 6 samples × 20 bits = 120 bits for the 48 KHz system (read side). Also in the audio data depacking unit 10, the signal Field-Start is the data depacking sequence start point.
[0027]
The 48 kHz, 960 sample / field × 20 bits / sample processed by the audio data depacking unit 10 is input to the audio baseband processing unit 8, and after performing audio baseband processing such as gain adjustment, the field frequency is output as a VTR output. It is output at 50 Field / s, 48 KHz, 960 sample / field × 20 bits / sample. Thus, based on the field frequency of 60 Field / s VTR, it corresponds to the field frequency of 50 Field / s.
[0028]
So far, the case of the field frequency of 50 Field / s has been described, but other field frequencies can also be handled. FIG. 9 shows a block diagram in the case of a field frequency of 48 Field / s. (A) shows the recording side, and (B) shows the reproduction side. The base VTR is the field frequency 60Field / sVTR in FIG. The video side uses the video clock converter 11 and the video clock converter 12 to convert the rate to the field frequency ratio as in the case of the field frequency of 50 Field / s, and in this case, 74.25 MHz <----> 59.4 MHz. (= 74.25 MHz × 48/60).
[0029]
This situation is shown in FIG. (A) shows an image frame with a field frequency of 60 Hz, (B) shows an image frame with a field frequency of 48 Hz, and (C) shows an image frame (signal form) after processing the image frame with a field frequency of 48 Hz by the video clock converter 11. . As can be seen from FIG. 10, as in the case of the field frequency of 50 Field / s, the effective area is not changed by the conversion of the input video clock converter 11 and the output video clock converter 12, and only the invalid area (blanking area) is changed. It can be seen that after conversion, the image frame of the original 60 Field / sVTR including the invalid area and the effective area is exactly the same.
[0030]
On the other hand, when considering audio, the total number of bits per audio field is set to be the same between the base field frequency 60 Field / sVTR and the field frequency 48 Field / sVTR, which is convenient at the field frequency 48 Field / s. The number of samples per field, not the number of bits per sample. Audio can be recorded at 800 Sample / field × 24 bits / Sample per field with the base 60 Field / s VTR. Based on this, consider a case where the audio input unit is 48 KHz with 48 field / s VTR. Since it is 48 field / s, it becomes 1000 sample / field. If simply converted, 800 sample / field × 24 bits / sample = 19200 bits / field, so 1000 samples / field × 19.2 bits / sample. Since 19.2 bits per sample is not an integer number of bits, it cannot be realized. Therefore, it is converted into 800 sample / field × 24 bit / sample via 960 sample / field × 20 bit / sample which is close to this. As shown in FIG. 9, the audio rate converter 13 once converts 1000 samples / field × 20 bits / sample (48 KHz, 48 Field / s) to 960 samples / field × 20 bits / sample (46.08 KHz, 48 Field / s). The audio data pack unit 9 converts this signal into 800 samples / field × 24 bits / sample (36.864 KHz = 46.08 KHz × 48/60, 48 Field / s). As with the field frequency of 50 Field / s, encoding is performed at the field frequency ratio rate.
[0031]
The decoding process is performed in reverse to the encoding process, and the audio data depacking unit 10 converts 800 sample / field × 24 bit / sample (36.864 KHz, 48 Field / s) to 960 sample / field × 20 bit / sample (46.08 KHz, 48 Field / s). Are converted into 1000 samples / field × 20 bits / sample (48 KHz, 48 Field / s) by the audio rate converter 14 and output as a VTR. At this time, the sampling rate is converted to 46.08 KHz, but since the human audible range is generally 20 KHz, the sampling frequency only needs to exceed 40 KHz even if applied to the sampling theorem, such as D / A, A / D, etc. Considering performance, it is considered that a sampling frequency of 46.08 KHz is sufficient. In this way, when the number of bits per sample where the total number of bits is the same is considered, even if the number of bits does not become an integer bit, the number of bits per sample is an integer without reducing the sampling frequency so much by using a sampling rate converter. Can be a bit.
[0032]
When considering the field frequency of 48 Field / s, without using the sampling rate converter of the above method, add 200 samples of stuffing (insignificant data) to 1000 samples / field × 19 bits / sample and convert to 800 samples / field × 24 bits / sample. May be. However, in this case, since the audio data pack / depack sequence becomes long, a large FIFO is required. That is, the least common multiple becomes higher in the numerical relationship between 19 bits and 24 bits than the relationship between 20 bits and 24 bits, and the size of the FIFO increases accordingly.
[0033]
Up to this point, the description has been given by taking the high-vision as an example. Therefore, even if the field frequency is different as in the examples shown in FIGS. 11 and the video clock converter 12 do not perform line conversion filter processing. However, in the case of the standard specification (SD), the effective area image frame is different in number of lines from 720 sample × 480 Line at a field frequency of 60 Field / s and 720 sample × 576 Line at a field frequency of 50 Field / s. become. FIG. 11 shows a block diagram of the standard standard field frequency 60Field / sVTR based on FIG. (A) shows the recording side, and (B) shows the reproduction side. The audio baseband processing unit 3 and the audio baseband processing unit 8 are the same as in the example of FIG. The input video baseband processing unit 15, the video compression unit 16, the ECC encoding & audio / video combining unit 17, the ECC decoding & audio / video separating unit 18, the video decompressing unit 19, and the output video baseband processing unit 20 are for SD. Processing block.
[0034]
FIG. 12 shows a block diagram of an SD field frequency of 50 Field / sVTR based on a field frequency of 60 Field / sVTR. (A) shows the recording side, and (B) shows the reproduction side. FIG. 13 shows the respective image frames and the image frames after processing with a field frequency of 50 Field / s. (A) shows an image frame with a field frequency of 60 Hz, (B) shows an image frame with a field frequency of 50 Hz, and (C) shows an image frame (signal form) after processing the image frame with a field frequency of 50 Hz by a video clock converter. In FIG. 12, video baseband processing units 21 and 24 perform input video baseband processing and output video baseband processing, respectively, but are for a field frequency of 50 Field / s, and because the number of lines is different, the field frequency of 60 Field / The processing is completely different from the video baseband processing units 15 and 20 in FIG. 11 corresponding to s. The video line & clock converter 22 in FIG. 12 corresponds to the video clock converter 11 in FIG. 5, and an effective image frame 720 sample × 576 Line having a field frequency of 50 Field / s is converted into an effective image frame 720 sample × having a base field frequency of 60 Field / s. Line conversion filter processing for conversion to 480 Line is performed. As shown in FIG. 13, the video line and clock converter 22 converts the image frame and also changes the clock.
[0035]
The video line & clock converter 23 in FIG. 12 corresponds to the video clock converter 12 in FIG. 5, and an effective image frame 720 sample × 480 Line having a base field frequency of 60 Field / s is converted into an effective image frame 720 sample × having a field frequency of 50 Field / s. Line conversion filter processing for conversion to 576 Line is performed to restore the original number of lines. As shown in FIG. 13, the video line & clock converter 23 converts the image frame and also changes the clock. As in the high-definition example, the video compression unit 16, the ECC encoding & audio / video combination unit 17, the ECC decoding & audio / video separation unit 18 and the video decompression unit 19 only change the rate, and the circuit is the base field. The same frequency as 60 Field / sVTR can be used. Audio can be processed in the same way as in the high-definition example, and the audio data pack unit 9, audio data depack unit 10, audio baseband processing unit 3 and audio baseband processing unit 8 are completely the same as the high-definition VTR in FIG. The same thing. Although the case of SD has been described as an example, a different field frequency VTR can be created from the base field frequency VTR by applying filter processing for converting the image frame even if the image frames are different.
[0036]
By the way, in the previous VTR shown in FIG. 5, when there is an audio recording device having a base field frequency, when creating a device corresponding to a different frequency based on the audio recording device, the format conversion of the audio data is shown in FIG. As shown, FIFO was used, and clocks were read and written, and two types of clocks were required. The two types of clocks are a clock having a frequency on the baseband side and a clock having a field frequency ratio times that of the clock. The reason why the clock of the field frequency ratio is required is to operate the circuit portion on the recording medium side from the format conversion unit of the audio data at the rate of the field frequency ratio without changing the processing contents. For example, when there is a device with a base field frequency of 60 Field / s, an audio input sampling frequency is 48 KHz, and the number of bits per sample is 24 bits / sample, a sampling frequency of 48 KHz is obtained with a device with a field frequency of 50 Field / s based on this. If a device having a bit number of 20 bits / sample per sample is produced, audio data conversion is performed by applying two 48 KHz clocks and 40 KHz (= 48 KHz × 50/60) clocks to the audio data format conversion unit. It was.
[0037]
In order to improve this point, the development of the VTR shown in FIG. 5 will be described here. That is, the audio data pack unit 9 of the VTR corresponding to the field frequency 50 Field / s shown in FIG. 5 is built in the ECC encoding & audio / video combination unit 4 and has the function therein, and the block The figure is shown in FIG. (A) shows the recording side, and (B) shows the reproduction side. FIG. 14 shows a common VTR corresponding to both field frequencies of 60 Field / s and 50 Field / s. The frequencies described in FIG. 14 having different values for 60 Field / s and 50 Field / s are in a relationship of field frequency ratio multiplication. For example, the output of the video compression unit 2 has a relationship of 38.6666 MHz = 46.4 MHz × 50/60, which is a field frequency ratio multiple.
[0038]
FIG. 15 shows a specific configuration of the ECC encoding & audio / video combination unit 4 ′. Here, the video that has undergone C2ECC processing by the video C2ECC processing unit 35 is sent to the SDRAM read / write control unit 31. On the other hand, the serial data of the audio is serial / parallel converted by the S / P converter 25, and the data is sent to the controller 26. The controller 26 performs RateConvRAM write control (data write control of the RateConv28) and ECC start control (process start control of the other controller 29). The controller 26 includes a conversion register 34. This part will be described in detail later. The RateConvRAM 28 is a Dual Port RAM, in which a clock is changed from an audio 48 kHz system clock to an internal system clock (66 MHz). The controller 29 performs RCRAM (RateConvRAM28) read control, C2RAM30 control, C2ECC parity addition processing, and SDRAM write address generation. The SDRAM read / write control unit 31 controls access to the SDRAM 32. The C1ECC processing unit 33 performs SDRAM read address generation and C1ECC parity addition, and outputs RF data on the RF clock rate. The audio timing generator 27 receives a field signal and a sampling period (FS) signal and counts one field. In this case, since both the field frequency is 60 Field / s and 50 Field / s, the sampling frequency is 48 KHz. Therefore, when the field frequency is 60 Field / s, 800 samples per field are counted by the counter, and the controller 26 and the C1 ECC processor 33 process the processing timing. When the field frequency is 50 Field / s, 960 samples per field are counted by a counter, and processing timing is given to the controller 26 and the C1 ECC processing unit 33.
[0039]
FIG. 16 shows an audio timing chart of the ECC encode & audio / video combination unit 4 ′. FIG. 16 shows a process of a field frequency of 60 Field / s and one sample of 24 bits / sample. That is, when the field frequency is 50 Field / s, the processing timing after 20 bits / sample is converted to 24 bits / sample is written. First, the basic 60 Field / s timing will be described. The RateConvRAM 28 is internally divided into 3 banks, and 48 samples × 24 bits / sample data can be stored in each bank. The numbers in FIG. 16 indicate RCRAMbankNo. Is shown. It can be seen that 800 sample / field is processed at 48 sample / bank × 16 bank + 32 sample (1 bank). Audio data is written to the RateConvRAM 28 at an FS (sampling frequency 48 KHz) rate. Fld-Start (Field-Start) and C2-Start are processing timing control signals coming from the controller 26, and new field data from the Fld-start is written to the RateConvRAM 28. It can be seen from FIG. 16 that new field data is written in the RateConvRAM 28 in order from bank 2 and 0. When the next C2-Start arrives, the C2, ECC processing of bank2, 0 is started. Read from the RateConvRAM 28 in the C2 direction at a system clock of 66 MHz. The controller 29 performs C2ECC processing, adds C2 parity, and then writes the data in the C2RAM 30 in the C2 direction. When writing to all the C2RAMs is completed, the data is read from the C2RAM in the C1 direction, sent to the SDRAM read / write control unit 31 together with the SDRAM write address, and written to the SDRAM 32. Such processing is performed in time division from channel 0 to channel 7 in order. C2-Start comes every time 2 banks are written in the RateConvRAM 28, and the last of the field is C2-Start simultaneously with the Fld-start signal to process the data remaining in the current field. At the end of the field, as a result, processing of 32 samples which is less than 1 bank is performed. Fld-Start and C2-Start are generated from a control signal input from the audio timing generator 27 by the controller 26. In this way, audio ECC encoding processing with a field frequency of 60 Field / s is performed. At the basic field frequency 60 Field / s, the conversion register 34 is not used.
[0040]
Next, a case where a signal having a field frequency of 50 Field / s is input will be described. As can be seen from FIG. 14, when the field frequency is 50 Field / s, the audio input to the ECC encoding & audio / video combination unit 4 ′ comes at 960 samples / field × 20 bits / sample (48 KHz). The audio data pack is converted into 800 sample × 24 bits / sample, and the convert register 34 in FIG. 15 functions as the audio data pack. The S / P converter 25 in FIG. 15 processes the data of 960 samples / field × 20 bits / sample in the same manner as the field frequency of 60 fields / s and performs serial / parallel conversion. The parallel data coming from the S / P converter 25 to the controller 26 comes in 8-bit units with LSB fast. When sending 20 bits / sample, it is divided into LSB 4 bits, MDB (intermediate) 8 bits and MSB 8 bits. This is converted into 24-bit data by the conversion register 34. The unit of the sequence is 960 samples / field × 20 bits / sample, and 6 samples are converted into one sequence, which is converted into 24 bits and 5 samples. That is, 6 samples × 20 bits / sample is converted into 5 samples × 24 bits / sample. Therefore, 960 sample / field × 20 bits / sample is converted to 800 sample / field × 24 bits / sample.
[0041]
An explanatory diagram of the operation of the convert register 34 is shown in FIG. The conversion register 34 has 24 registers (for 24 bits). The input data is 20 bits / sample, and as shown in FIG. 17, the audio data is written in the MSB in the LSB fast order in the register with the signal Field-Start as the head of the conversion processing sequence. As described above, one sample data is decomposed into three parts, LSB 4 bits, MDB 8 bits, and MSB 8 bits, so 1 sample is also written in the register in 3 parts. At the time of writing, when it reaches the MSB of the register, it returns to the LSB and writes it cyclically. In FIG. 17, the left side of the conversion register represents a bit being written, and the right side represents a bit being read. For example, looking at the fourth from the left of the conversion register in FIG. 17, it can be seen that writing is only MSB 4 bits and reading is LSB 8 bits. Note that when writing and reading to the convert register compete at the same time, writing has priority.
[0042]
The conversion register 34 is read for the first 1 sample, and then read from the LSB in units of 8 bits. This is the write data to the RCRAM. In the figure, A to F represent independent samples, and explain what kind of data packing is performed in the audio data pack processing. The conversion register 34 is read with a 48 kHz clock, but a break is entered at the start sample of the sequence, and control is performed so that writing to the RateConvRAM 28 is also suspended when the read is absent. In other words, in 1 sample every 6 samples, reading from the conversion register 34 and writing to the RCRAM 28 are suspended. In addition, the internal counter that generates the C2ECC processing start control signal, the Fld-Start signal, the C2-Start signal, and the like to the controller 29 also generates a signal by resting once every 6 samples in the 48 KHz system. . The counter operation of 95 samples (48 KHz system) at a field frequency of 60 field / s operates at 114 samples (48 KHz system) (= 95 × 6/5) at 50 Field / s. From the part where Fld-start and C2-Start overlap in FIG. 16, the next C2-Start has a field frequency of 60 Field / s and an interval of 96 samples (48 KHz). Considering this at a field frequency of 50 Field / s At 114 sample, the counter for 95 samples (60 field / s) advances, and since the next 1 sample starts the sequence, it becomes a break, and at the next 1 sample, the counter advances, and the counter for 96 samples (60 field / s) advances. That is, C2-Start following Fld-start comes out at 116 samples (114 + 1 + 1). In this way, the C2ECC process of the controller 29 also operates at a field frequency ratio multiple. What is important at this time is that the RateConvRAM 28 and the controller 29 and later operate at a frequency ratio doubled by the RAM write control and the process start control, and the RateConvRAM 28 and the controller 29 have no circuit compared to the field frequency of 60 field / s. It is not necessary to change. Also, the rate conversion of the field frequency ratio is performed by resting the internal counter and control at a rate of 1 sample in 6 samples at the time of audio data pack conversion, and the two clocks of 48 KHz and 40 KHz shown in FIG. 7 are used. Compared with the system in which audio data is packed, rate conversion can be performed with only one 48 KHz clock and only 24 registers.
[0043]
Next, FIG. 18 shows an internal block configuration of the ECC decoding & audio / video separation unit 5 ′ on the reproduction side. In the C1ECC decoding processing unit 36, C1ECC decoding (error correction) is performed on the RF data, and the data is written into the SDRAM 32 via the SDRAM read / write control unit 31. The video is C2ECC-decoded by the video C2ECC decode processing unit 42 and the data read from the SDRAM 32 by the SDRAM read / write control unit 31 to output video data. On the other hand, although it is audio, the timing generator 38 obtains a field signal and a sampling period (FS) signal and counts one field. In this case, since the sampling frequency is 48 KHz for both the field frequencies 60 Field / s and 50 Field / s, when the field frequency is 60 Field / s, 800 samples per field are counted by a counter, and the controller 39 and the C1 ECC decoding processing unit 36 are processed at the same timing. In the case of a field frequency of 50 Field / s, 960 samples per field are counted by a counter, and processing timing is given to the controller 39 and the C1 ECC decoding processing unit. The controller 39 creates C2ECC decode processing timing and sends the timing to another controller 37. The controller 39 controls the reading of the RateConvRAM 28. There is a conversion register 41 inside the controller 39, which will be described in detail later. The controller 37 performs C2ECC decoding in accordance with the C2ECC decoding process start timing signals Fld-Start and C2-Start from the controller 39. Necessary data is read in the C1 direction from the SDRAM 32 via the SDRAM read / write control unit 31, and written in the C2RAM 30 in the C1 direction. After the data is stored in the C2RAM 30, the data is read in the C2 direction, the C2ECC decoding process is performed, and the data is written in the RateConvRAM 28. The operation of the controller 37 and the writing to the C2RAM 30 and the RateConvRAM 28 are performed with an internal system clock of 66 MHz. The controller 39 reads data from the RateConvRAM 28 in a 48 KHz system. The data is sent to the S / P converter 40. The S / P converter 40 performs concealment processing, mute processing, and the like, and then the data is parallel-serial converted to become an audio output of the ECC encode & audio / video separation unit 5 ′.
[0044]
FIG. 19 shows an audio timing chart of the ECC decode & audio / video separation unit 5 ′. FIG. 19 shows a process of a field frequency of 60 Field / s and 1 sample of 24 bits / sample. That is, when the field frequency is 50 Field / s, the processing timing before the conversion from 24 bits / sample to 20 bits / sample is written. First, the basic 60 Field / s timing will be described. The RateConvRAM 28 is internally divided into 3 banks, and 48 samples × 24 bits / sample data can be stored in each bank. The numbers in FIG. 19 indicate RCRAMbankNo. Is shown. It can be seen that 800 sample / field is processed at 48 sample / bank × 16 bank + 32 sample (1 bank). Fld-Start and C2-Start are processing timing control signals coming from the controller 39, and new field data is read from the RateConvRAM 28 from the Fld-start. In FIG. 19, it can be seen that the new field data is read from the RateConvRAM 28 in order from bank 2 and 0. Thereafter, data is read from the RateConvRAM 28 at an FS rate without any breaks. As can be seen from FIG. 19, the bank of the RateConvRAM 28 is cyclically read. C2-Start is issued every time 2 banks of the RateConvRAM 28 are read. Since the new field data must be read from the RateConvRAM 28 from the time when Fld-Start is issued, the first bank of the new field is C2ECC decoded at C2-Start before Fld-Start. In FIG. 19, bank2 is the first bank in the new field, and this is C2ECC processed. In the first process of the new field, one bank of RCRAM is processed. When Fld-Start comes, the next 2 banks are processed, and thereafter, every time C2-Start comes, the processing is performed for 2 banks. In this way, the audio ECC decoding process with a field frequency of 60 Field / s is performed. The conversion register 41 is not used at the basic field frequency of 60 Field / s.
[0045]
Next, the case where the field frequency is 50 Field / s will be described. As can be seen from FIG. 14, at the field frequency of 50 Field / s, the audio output of the ECC decode & audio / video separation unit 5 ′ is depacked as audio data and output at 960 sample / field × 20 bits / sample (48 KHz). The 800 register / field × 24 bit / sample is audio data depacked and converted into 960 sample / field × 20 bit / sample, but the convert register 41 in FIG. 18 functions as the audio data depack. Data read from the RateConvRAM 28 in FIG. 18 is 24 bits / sample, and comes in 800 samples / field × 24 bits / sample. This data is converted to 960 sample / field × 20 bits / sample by performing audio data depack conversion in the conversion register 41. When sending 20 bits / sample to the S / P conversion unit 40, the controller 39 in FIG. 18 divides it into LSB 4 bits, MDB (intermediate) 8 bits, and MSB 8 bits in the same way as at the time of encoding. The unit of the conversion sequence is 960 samples / field × 20 bits / sample as in encoding, and 6 samples is one sequence. That is, 5 samples × 24 bits / sample is converted to 6 samples × 20 bits / sample. Therefore, 800 sample / field × 24 bit / sample is converted to 960 sample / field × 20 bit / sample.
[0046]
An operation explanatory diagram of the convert register 41 is shown in FIG. There are 24 conversion registers (for 24 bits). The input data is 24 bits / sample, and the audio data is written to the register with the signal Field-Start as the head of the conversion processing sequence as shown in FIG. At this time, in the case of the forward reproduction (Forward) shown in (A), the data is written in the MSB in order with LSB fast. Also, in the case of reverse playback (Reverse) shown in (B), data is written in the order of LSB in MSB fast order. In addition, when reading is performed in the forward direction, data is read out in order toward the MSB in LSB fast. If the playback is in the reverse direction, the data is read in the direction of LSB in order with MSB fast. When data is output from the controller 39 to the S / P conversion unit 40, the data is divided into three LSB 4 bits, MDB (intermediate) 8 bits, and MSB 8 bits in accordance with the LSB fast or MSB fast in the conversion register read. Therefore, LSB fast is used for forward playback, and MSB fast is used for backward playback. In decoding, as in encoding, both writing and reading are cyclically written to / read from the conversion register 41. If writing and reading compete at the same time, reading is performed first.
[0047]
The conversion register is controlled so as to rest after writing 1 sample after writing 5 samples. That is, for 1 sample in 6 samples, reading from the RateConvRAM 28 = writing to the conversion register 41 is suspended. In addition, an internal counter for generating a C2ECC decode processing start control signal, Fld-Start signal, C2-Start signal, etc. to the controller 37 is also rested once every 6 samples in a 48 KHz system to generate a signal. The counter operation of 95 samples (48 KHz system) at a field frequency of 60 field / s operates at 114 samples (48 KHz system) (= 95 × 6/5) at 50 Field / s. From the part where Fld-start and C2-Start overlap in FIG. 19, the next C2-Start has a field frequency of 60 Field / s and an interval of 96 samples (48 KHz), but this is considered at a field frequency of 50 Field / s. The counter for 95 samples (60 fields / s) advances at 114 samples, the counter advances at the next 1 sample, and the counters advance for 96 samples (60 fields / s). That is, C2-Start next to Fld-start comes out at 115 sample (114 + 1). In this way, the C2 ECC decoding process of the controller 37 also operates at a field frequency ratio multiple. What is important at this time is that the RateConvRAM 28 and the controller 37 are operating at a frequency ratio doubled by the RAM read control and the process start control. The RateConvRAM 28 and the controller 37 change the circuit as compared with the case of the field frequency of 60 field / s. There is no need to do that. Further, the controller 39 performs rate conversion by multiplying the field frequency ratio by resting the internal count and control at a rate of 1 sample in 6 samples at the time of audio data depack conversion, and the 48 KHz and 40 KHz2 in FIG. Compared with a system that depacks audio data using two clocks, the rate conversion can be performed with only one clock of 48 KHz and with only 24 registers.
[0048]
【The invention's effect】
According to the present invention, format conversion of audio data can be easily processed by the ECC encoding processing circuit. A device (FIFO) dedicated to audio data format conversion is not required. Further, since it is not necessary to put a clock dedicated to audio data format conversion into the ECC encoding processing circuit, it is only necessary to input one type of baseband audio clock to the ECC encoding processing circuit. Format conversion can be realized by providing only 24 registers (24 bits) in the ECC encoding processing circuit. The ECC encoding processing circuit based on most of the processing (eg rate conversion RAM processing, C2 ECC encoding processing) after the format conversion of the audio data can be used as it is by simply changing a part of the control of the ECC encoding processing circuit, so that there is almost no additional circuit. unnecessary.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of a basic digital audio / video recording / reproducing apparatus.
FIG. 2 is a schematic diagram showing audio data input serially.
FIG. 3 is a format diagram of video data.
FIG. 4 is a format diagram of audio data.
FIG. 5 is a block diagram showing a form of a digital audio / video recording / reproducing apparatus according to the original form of the present invention.
6 is a schematic diagram for explaining the operation of the digital audio / video recording / reproducing apparatus shown in FIG. 5. FIG.
7 is a schematic diagram for explaining an operation of an audio data pack unit included in the digital audio / video recording / reproducing apparatus shown in FIG. 5; FIG.
FIG. 8 is a schematic diagram for explaining an operation of an audio data depacking unit included in the digital audio / video recording / reproducing apparatus shown in FIG. 5;
FIG. 9 is a block diagram showing another embodiment of the digital audio / video recording / reproducing apparatus according to the original form of the present invention.
10 is a schematic diagram for explaining the operation of the digital audio / video recording / reproducing apparatus shown in FIG. 9. FIG.
FIG. 11 is a block diagram showing another example of a basic digital audio / video recording / reproducing apparatus.
FIG. 12 is a block diagram showing another embodiment of a digital audio / video recording / reproducing apparatus according to the original form of the present invention.
13 is a schematic diagram for explaining the operation of the digital audio / video recording / reproducing apparatus shown in FIG.
FIG. 14 is a block diagram showing an embodiment of a digital audio / video recording / reproducing apparatus according to the present invention.
15 is a block diagram showing a configuration of an ECC encoder & audio / video combining unit included in the digital audio / video recording / reproducing apparatus shown in FIG. 14;
16 is a schematic diagram for explaining an operation of an ECC encoder & audio / video combination unit included in the digital audio / video recording / reproducing apparatus shown in FIG. 14;
FIG. 17 is a schematic diagram for explaining the operation of a conversion register included in the ECC encoder & audio / video combination unit shown in FIG. 16;
18 is a block diagram showing a configuration of an ECC decoder & audio / video separating unit included in the digital audio / video recording / reproducing apparatus shown in FIG.
FIG. 19 is a schematic diagram for explaining the operation of an ECC decoder & audio / video separating unit included in the digital audio / video recording / reproducing apparatus shown in FIG. 14;
20 is a schematic diagram for explaining the operation of a conversion register included in the ECC decoder & audio / video separation unit shown in FIG. 19;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Video baseband process part, 2 ... Video compression part, 3 ... Audio baseband process part, 4 ... ECC encoding & audio / video combination part, 5 ... ECC decoding & audio / video separation part, 6 ... Video expansion part, DESCRIPTION OF SYMBOLS 7 ... Video baseband process part, 8 ... Audio baseband process part, 9 ... Audio data pack part, 10 ... Audio data depack part, 11 ... Video clock converter, 12 ... Video clock converter, 13 ... Audio rate converter, 14 ... Audio rate converter, 26 ... Controller, 34 ... Convert register, 39 ... Controller, 40 ... S / P converter, 41 ... Convert register

Claims (3)

Inputted from the outside, an audio data inputted in association with the video signal having a first field frequency, specified in the field unit a predetermined data sequence and the bit sequence in co as having a predetermined sampling frequency An input unit for receiving audio data based on the first format and performing at least baseband processing of the audio data;
Designed to process audio data based on a second format having a predetermined sampling frequency and a second field frequency and defining a predetermined data array and bit array in field units. A processing unit including an encoding unit that performs an encoding process for error correction of audio data that is operated with a corresponding clock and that is sequentially adapted to the second format;
In a digital audio recording apparatus comprising an output unit for writing audio data output from the processing unit to a recording medium,
The processing unit includes conversion means, and when the first field frequency of audio data is different from the second field frequency and the first format is different from the second format, the conversion means , After converting the first format and adapting to the second format, the audio data is passed to the encoding means,
Said encoding means, while the clock signal is generated according to a predetermined sampling frequency, the ratio the second while taking any time resting in corresponding to the ratio of the second field frequency and said first field frequency It intends line encoding processing for error correction of the audio data adapted to the format
Digital audio recording apparatus. The conversion means rearranges the number of samples per field and the number of bits per sample while maintaining the total number of bits per field determined by the product of the number of samples per field and the number of bits per sample. that converts the first format to the second format
Digital audio recording apparatus 請 Motomeko 1 wherein. The conversion means includes a register having a bit number corresponding to the number of bits per sample on the second format side, and cyclically converts the audio data in the first format composed of a bit stream of serially arranged samples. one writing, audio cyclically from the register while taking any time pause at a ratio corresponding to the ratio of single-sample per bit number of the first format-side one sample per bit rate and the second format-side reads the data, that converts the first format reclassified the number of bits of the sample number and one sample per field in the second format
Digital audio recording apparatus 請 Motomeko 2 wherein.

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