JP2937664B2 - Error correction method and apparatus for digital VTR - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for correcting an error in a digital video tape recorder, and more particularly to a method for separating video data of a synchronous block into an independent portion having most video information and a non-independent portion having extra data. The present invention relates to a digital video tape recorder error correction method and apparatus for recording / reproducing data.

[0002]

2. Description of the Related Art Digital video tape recorders (D-
VTR) is a conventional analog VT device that converts video information into digital data and records or reproduces it.
Compared with R, the signal-to-noise ratio (S / N) is increased, the resolution is increased, and editing is facilitated. Such a digital VTR converts an analog signal of a frame image into a digital signal and stores the digital signal in a frame memory. The data stored in the frame memory is divided into blocks and VLC (Variabe Length Coding) discrete cosine transform (DC
T) and Huffman variable length coding are performed and compressed. An error correction code (inner code) is added to each of the compressed unit blocks, and the compressed unit blocks are reconstructed in other frame memories at the original positions. An outer code block having another error correction code (outer code) is added to the vertical unit block of the reconfigured frame memory. The unit block and the outer code block are added with a synchronization signal and a block address, and are sequentially recorded on tracks on the tape. At the time of reproduction, a unit block and an outer code block are reproduced from a pickup signal generated by a head that scans a track, and the reproduced unit block and the outer code block are recorded in a frame memory by respective block addresses. Performs error correction on the unit block recorded in the frame memory using an outer code and an inner code, and performs inverse Hoffman variable length encoding and inverse DCT.
Perform the conversion. The digital signal subjected to the inverse DCT conversion is converted to an analog signal, and an analog signal indicating the original video is reproduced.

[0003] DCT transforms a time function into an energy function having DC and AC coefficients. A characteristic of the DCT transform is that most of the energy of the signal is concentrated in the low frequency part. In Huffman variable length coding, the coefficients of the frequency function are variably coded. For variable speed reproduction, the data must be compressed and recorded so that the bit amount of each unit block is constant. When each unit block is compressed so as to have a fixed bit amount, the simple part and the complex part in the original video are compressed to the same bit amount, so the reproduction of the complicated part during reproduction is a simple part reproduction Lower than sex. Therefore, the complexity of the frame is calculated so that the screen at the time of normal reproduction has uniform reproducibility as a whole, and thereby the bit amount of each unit block is adjusted.
That is, the simple part allocates less bits, and the complex part allocates more bits.

Japanese Patent Application No. Hei 4-201540 filed by the present applicant discloses an independent part (Indepe) having most of the information for reproducing the original image of the unit block.
There is disclosed a method of recording separately into an ndent Decodable Code (IDC) and a non-independent portion (Dependent Decodable Code: DDC) having extra information. In such a system, the independent portion and the non-independent portion are all used at the time of normal reproduction, and the original video is reproduced using only the independent portion at the time of variable speed reproduction, so that variable speed reproduction can be simplified. Even if a sync block mismatch occurs due to the head traversing various tracks during variable speed playback, an image close to the original image can be played if only the independent part that is a part of the unit block is detected. . Therefore, in order to increase the reproduction rate of data at the time of reproduction, it is desirable that the independent portion at the time of recording and the non-independent portion are separately subjected to error correction coding.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an error correction coding method suitable for a system in which data of a unit block is separated and recorded into an independent part and a non-independent part. Another object of the present invention is to provide an error correction decoding method which facilitates variable speed reproduction.

It is still another object of the present invention to provide an apparatus suitable for the above error correction coding method. Still another object of the present invention is to provide an apparatus suitable for the above error correction decoding method.

[0007]

In order to achieve the above object, an error correction encoding method according to the present invention comprises a first block identification signal in a unit block, an independent part and a non-independent part.
The method includes a step of adding an inner code and a second inner code. According to another aspect of the present invention, there is provided an error correction decoding method for decoding a block identification signal and an independent part and a non-independent part using a first inner code and a second inner code during normal reproduction, and a block during variable speed reproduction. The method may further include decoding only the identification signal and the independent part using the first inner code.

According to another aspect of the present invention, there is provided an error correction encoding apparatus which receives a unit block to which a block identification signal is added, separates the unit block into an independent part and a non-independent part, and outputs the block. A demultiplexer, a block identification signal from the demultiplexer,
A first inner code encoder that adds a first inner code to the independent part, a second inner code encoder that adds a second inner code to the non-independent part from the demultiplexer, The block identification signal to which the first inner code is added from the inner encoder and the independent portion and the non-independent portion to which the second inner code is added from the second inner encoder are input, and their combination is Is output.

According to another aspect of the present invention, there is provided an error correction decoding apparatus according to the present invention, which receives a synchronous block, receives a block identification signal, a first group including an independent unit and a first inner code, and performs a non-independent operation. A demultiplexer that separates and outputs a second group consisting of a unit and a second inner code, and a block identification signal from the demultiplexer, a first group consisting of an independent unit and a first inner code, and A first inner code decoder for decoding the block identification signal and the independent part by a first inner code, and a second group consisting of a non-independent part and a second inner code from a demultiplexer are input to a second group. A second inner code decoder for decoding a non-independent part by an inner code, a block identification signal from the first inner code decoder, an independent part, and a non-independent part from the second inner code decoder; Of those A multiplexer for outputting a combined output, a buffer for inputting a block identification signal from the first inner code decoder and an independent unit, and a selector for selecting and outputting an output from the multiplexer and an output from the buffer. Features.

[0010]

An error correction method and apparatus according to the present invention are used for recording and reproducing a digital VTR. First, an independent portion having most of video data in a unit block and a non-independent portion having extra data are firstly recorded. By adding and recording the inner code and the second inner code, data integrity is improved.

Further, the error correction encoding method and apparatus of the present invention use only the independent portion with error correction at the time of variable speed reproduction, thereby causing the head to traverse various tracks at the time of variable speed reproduction. This has the advantage of minimizing the loss of valid data due to mismatched synchronized blocks and simplifying error correction processing.

[0012]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a diagram showing a configuration of a recording system in a digital magnetic recording / reproducing apparatus. In FIG. 1, a color signal (RGB signal or luminance / color difference signal) input to a recording system is subjected to data compression through a video compression unit 10, and an error correction code is added by an error correction encoder 12.
The color difference signals between tracks are alternately controlled by the channel encoder 14 and recorded on the tape 16.

FIG. 2 is a diagram showing an error correction encoder according to the present invention. In FIG. 2, reference numeral 20 denotes a block identification signal generator for adding a block identification signal to each unit block (hereinafter, referred to as a synchronous block), and 22 denotes input data which is a root of a primitive polynomial of an RS (Reed-Solomon) code. Are vector-alpha-transformers that convert the data into powers of α, and are first and second outputs 24 and 26 for rearranging and outputting data for outer coding of the RS code through the vector-alpha-transformer 22. Memory and first
A memory controller 28 is an outer code encoder for adding an outer code to the synchronization block in the column direction output from the first memory 24, and 30 and 32 pass through the outer code encoder 28. A second memory and a second memory controller for rearranging and outputting data for inner code encoding of the synchronous block, and a synchronous block output from the second memory 30 as a block identification signal and an independent unit and a non- Demultiplexers for separating into independent parts; and 36 and 38, first and second inner code encoders for adding respective inner codes to the block identification signal and the independent and non-independent parts; 40 is a multiplexer for combining the outputs from the first and second inner encoders 36 and 38;
Reference numerals 42 and 44 denote a third memory and a third memory controller for rearranging and outputting the synchronization blocks recorded on the tape 16, and reference numeral 46 denotes a synchronization signal generator for adding a synchronization signal for each synchronization block. .

The operation of the configuration shown in FIG. 2 will be described in detail.
The synchronization block output from the video compression unit 10 of FIG. 1 is divided into an independent unit and a non-independent unit. The independent unit includes, for example, DC and some low-frequency components in the DCT transform coding method as data for variable speed reproduction, and may be the result of first-order vector quantization in the vector quantization method. The non-independent portion includes the remaining portion excluding the above portion. The input synchronization block is added with a block identification signal for classifying each synchronization block by a block identification signal generator 20, and is converted into a power of α which is a root of a primitive polynomial of the RS code by a vector-alpha-converter 22. The converted data is supplied to the first memory 24.

The operation of the first memory will be described with reference to FIG. The synchronous block input to the first memory 24 is written in the X direction as shown in FIG. 3 under the control of the first memory controller 26, read out bit by bit in the Y direction, and supplied to the outer code encoder 28. . With reference to FIG.
8. The operation of the second memory 30 and the second memory controller 32 will be described.

The outer code decoder 28 includes a first memory controller 2
6, the outer code is encoded for the M bits read out, and OP outer codes (Outer Pa) are output as shown in FIG.
rity) is added and supplied to the second memory 30. The data input to the second memory 30 is written in the Y direction as shown in FIG. 4 under the control of the second memory controller 32, read out in the X direction in units of synchronous blocks, and "decoded" by the demultiplexer 34. The signal is divided into an “independent part” and a “non-independent part” and supplied to the first inner encoder 36 and the second inner encoder 38, respectively.

The operation of the inner code encoders 36 and 38 will be described with reference to FIGS. 5 (A) and 5 (B). The first inner-code encoder 36 performs inner-code encoding on “the block identification signal A and the independent part B” or “the outer code for the ID and the IDC”, and performs one IP encoding as shown in FIG. The inner code (Inner Parity) is added. Second inner code encoder 38
Performs inner coding on “non-independent part C” or “outer code for DDC” and performs IP coding as shown in FIG.
Two inner codes are added. The output of each inner encoder is alternately selected by a multiplexer 40 and supplied to a third memory 42.

The operation of the third memory 42 and the third memory controller 44 will be described with reference to FIG. First inner code encoder 3
2 and the output of the second inner code encoder 38 are multiplexed by the multiplexer 40 and supplied to the third memory 42. The data recorded in the third memory 42 is read out in units of synchronous blocks in the X direction under the control of the third memory controller 44 and supplied to the synchronous signal generator 46 as shown in FIG. The synchronization signal generator 46 adds a synchronization signal to the synchronization block and supplies it to the channel encoder 14 in FIG.

FIG. 7 is a diagram showing a configuration of a reproducing system in a digital magnetic recording / reproducing apparatus. In FIG. 7, a signal recorded on a tape 76 is a channel decoder 74.
After the channel decoding is performed and the error correction and correction by the inner code and the outer code are performed through the error correction decoder 72, the original color signal (RGB or luminance / color difference signal) is demodulated by the video decompression unit 70. You.

FIG. 8 is a diagram showing an error correction decoder according to the present invention. In FIG. 8, reference numeral 80 denotes a synchronization signal detector, and reference numerals 82 and 84 each include a first group and a non-independent portion composed of a block identification signal, an independent portion, and a first inner code, and a second inner code. A fourth memory and a fourth memory controller for rearranging and outputting data in order to separate the second group, wherein a first group and a second group are formed from data output from the fourth memory 82; Demultiplexers for separation, 88 and 90
Is an inner code decoder, 92 is a two-dimensional error flag memory, and 94 is an address generator for generating a display address to the two-dimensional error flag memory 92 based on error signals from the inner code decoders 88 and 90. ,
Reference numeral 96 denotes a multiplexer for selectively outputting an inner code decoded block identification signal and an independent part and a non-independent part. Reference numerals 98 and 100 denote an inner code decoded block identification signal and an independent part and a non-independent part. A fifth memory and a fifth memory controller for combining and rearranging output are provided, and 102 is an outer code decoder. 104 is the first
A circuit breaker controlled so as to cut off a data transmission path by an error signal ERR1 of the inner code decoder 88;
106 is a buffer. Reference numeral 108 denotes an external decoder 10 which receives an externally provided signal indicating variable speed reproduction.
2 is a selector for selecting and outputting the output from the buffer 106, and 110 is an alpha-vector converter for converting the data converted to the power of α into a vector.

In the operation of FIG. 8, the synchronization signal detector 80
Detects a synchronization signal included in the input binary data string, and blocks the synchronization signal in units of synchronization blocks to supply the block to the fourth memory 82. The fourth memory 82 is controlled by the fourth memory controller 84 so as to record the data in units of synchronous blocks inputted as shown in FIG. 6, read the data in the X direction, and supply it to the demultiplexer 86. The demultiplexer 86 alternately selects the first group and the second group or “outer code for ID and IDC and outer code for DDC” from the input data of the synchronous block unit, and respectively selects the first inner code decoder 88. And the second inner code decoder 90.

The first and second inner code decoders 88 and 90 are provided as "first group and second group" or "ID and IDC".
And the outer code for DDC is corrected by the respective inner codes and supplied to the multiplexer 96. The multiplexer 96 is a first and a second.
The outputs of the inner code decoders 88 and 90 are alternately selected and supplied to the fifth memory 98.

The fifth memory 98 controls the inner code decoded “block identification signal and independent part and non-independent part” from the multiplexer 96 or “the outer code for ID and DDC and the outer code for DDC”. Vessel 1
4, the data is recorded in the X direction as shown in FIG.
Is controlled so as to be supplied.

The inner code decoders 88 and 90 generate error signals ERR1 and ERR2 and supply them to the two-dimensional error flag memory 92 when an error exceeding the limit of error correction by the inner code occurs. The two-dimensional memory 92 records the position of the synchronous block where the error has occurred by referring to the error signals ERR1 and ERR2 and the address ADDR from the address generator 94. The outer code decoder 102 refers to the two-dimensional error flag memory 92 to perform error correction using an outer code on a synchronous block in which an uncorrectable inner code error has occurred, and supplies the result to a selector 108. Selector 108
Is supplied to an alpha-vector converter 110 and R
It is converted from the power representation of α, which is the root of the S-code primitive polynomial, to the original vector form and output.

On the other hand, in the case of variable speed reproduction, the selector 108
Is controlled by the variable speed reproduction signal to select the buffer 106 side, and is output from the first inner code decoder through a path formed by the circuit breaker 104, the buffer 106, the selector 108 and the alpha-vector converter 110. Only the block identification signal and the independent part "are output. The circuit breaker 104 is controlled by the error signal ERR1 to output the data supplied from the first inner code decoder 88 to the buffer 106 only when there is no connection. At this time, since the data output from the circuit breaker 104 is not data having a continuous block identification signal, a queue type buffer is required. The selection of the error correction path corresponding to the normal reproduction operation and the variable speed reproduction operation is performed by controlling the selector 108 with a signal indicating the variable speed reproduction.

[Brief description of the drawings]

FIG. 1 is a diagram showing a general configuration of a recording system in a digital VTR.

FIG. 2 is a diagram showing a detailed configuration of an error correction encoder according to the present invention.

FIG. 3 is a diagram showing a form of data recorded in a first memory of FIG. 2 and a recording / reading state.

FIG. 4 is a diagram illustrating a form of data recorded in a first memory of FIG. 2 and a recording / reading state.

5 is a diagram showing data formats of independent part data and non-independent part data to which an inner code has been added by the inner code encoder of FIG. 2;

FIG. 6 is a diagram showing a form of data recorded in a third memory of FIG. 2 and a recording / reading state.

FIG. 7 is a diagram showing a general configuration of a reproduction system of a digital VTR.

FIG. 8 is a diagram showing a detailed configuration of an error correction decoder according to the present invention.

[Explanation of symbols]

 Reference Signs List 20 block identification signal generator 22 vector-alpha-transformer 24, 30, 42, 82, 98 memory 26, 32, 44, 84, 100 memory controller 28 outer code encoder 34, 86, 96 demultiplexer 36 First inner code encoder 38 Second inner code encoder 40 Multiplexer 46 Synchronous signal generator 80 Synchronous signal detector 88 First inner code decoder 90 Second inner code decoder 92 Two-dimensional error flag memory 94 address generator 102 outer code decoder 104 breaker 106 buffer 108 selector 110 alpha-vector converter

Claims (6)

(57) [Claims] 1. An image processing apparatus according to claim 1, wherein the video data of one screen is divided into unit blocks, transformed and encoded for each block unit, and the transformed and encoded result is independently decoded by an independent unit and a non-delayable decoding unit is independently decoded. In a digital video tape recorder that separates and records the data as a synchronous block unit and reproduces the recorded data in the reverse order of recording, the block identification signal in the synchronous block and the independent unit and the non-independent unit respectively An error correction encoding method comprising a step of adding a first inner code and a second inner code. 2. An image data of one screen is divided into unit blocks, transformed and encoded for each block unit, and a transformed and encoded result can be independently decoded. A digital video tape recorder that separates the data into independent sections, adds a first inner code and a second inner code, records the data in units of synchronous blocks, and reproduces the recorded data in the reverse order of recording; And decoding the independent and non-independent parts with the first inner code and the second inner code, and decoding only the independent part with the first inner code during variable-speed playback. Method. 3. An image data of one screen is divided into unit blocks, transformed and coded for each block unit, and a result of the transform and coded is independently decoded by an independent unit which can decode independently and a non-decoding unit which can be decoded independently. In a digital video tape recorder that separates into an independent part, adds a block identification signal and records the same as a synchronous block unit, and reproduces the recorded data in the reverse order of recording, a video of the unit block to which the block identification signal is added A demultiplexer that inputs data and separates and outputs the block identification signal and an independent portion and the non-independent portion; a block identification signal from the demultiplexer; and a first inner code for the independent portion. And a second inner code encoder for adding a second inner code to the non-independent portion from the demultiplexer. And a block identification signal to which the first inner code is added from the first inner encoder and an independent unit and a non-independent unit to which the second inner code is added from the second inner encoder. And a multiplexer for outputting a combined output of the errors. 4. An image processing apparatus according to claim 1, wherein the video data of one screen is divided into unit blocks, transformed and encoded for each block unit, and the transformed and encoded result can be independently decoded. It is separated into independent parts, and the first and second inner codes are added to the block identification signal and the independent and non-independent parts, respectively, and recorded as a synchronous block unit, and the recorded data is reproduced in the reverse order of recording. In the digital video tape recorder, a first group including the block identification signal, the independent unit, and a first inner code, and a first group including the non-independent unit and the second inner code, which are input to the synchronous block. A demultiplexer that separates and outputs the two groups; a first group from the demultiplexer that receives the first group and the block identification signal based on the first inner code. A first inner code decoder for decoding the independent part, and a second inner code decoder for inputting the second group from the demultiplexer and decoding the non-independent part by the second inner code And a multiplexer that inputs the block identification signal from the first inner code decoder, the independent unit and the independent unit from the second inner code decoder, and outputs a combined output thereof. Error correction decoding device. 5. A buffer for inputting the block identification signal from the first inner code decoder and the independent unit, and a selector for selecting and outputting an output from the multiplexer and an output from the buffer. The error correction decoding device according to claim 4, further comprising: 6. The error correction decoding apparatus according to claim 5, wherein said buffer is a queue type buffer.