KR0162243B1 - Digest audio system for digital vcr - Google Patents

Abstract

The present invention relates to a digital audio digest audio device, which reproduces audio data recorded by being shuffled onto a magnetic recording medium through a gshshuffling and editing process to continuously obtain normal audio without errors in a shift mode. It is.

Such present invention comprises: digital processing means for digitally compressing and shuffling an input video signal and an audio signal, respectively; Error correcting and encoding means for correcting and encoding an error of the compressed image and the shuffled audio data obtained by the digital processing means and recording it on a magnetic recording medium; Error correction and decoding means for detecting and correcting and decoding errors from the compressed video and audio data recorded on the magnetic recording medium during shift reproduction; It is achieved by shifting signal processing decoding means for restoring the error-corrected compressed video to the original video signal according to the shift mode provided by the microprocessor and reconstructing audio data for one track to provide a continuous audio signal. do.

Description

Digital VDI's Digest Audio Device

1 is a block diagram of a conventional analog V Digest audio device.

2 is a configuration diagram of an embodiment of a digital audio digest audio device of the present invention.

3 is a block diagram showing in detail the audio editing unit of FIG.

4 is an explanatory diagram showing a scanning state of a head as the tape travels during audio reproduction according to FIG. 2;

FIG. 5 shows the storage state of audio frames reproduced in the audio frame memory of FIG.

6 shows a shuffled memory map according to the channel mode of FIG.

FIG. 7 shows an audio frame state made up of an audio track of a tape according to FIG.

* Explanation of symbols for main parts of the drawings

200: Video input terminal 201: Audio input terminal

202: pulse code modulation and conversion unit 203: error correction coder

205: recording head 207: playback head

209: Error correction decoder 210: Shift signal processing decoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio digest audio device, and more particularly, to continuous audio data during shift playback, which is generated due to the fact that digital data is shuffled and stored for error correction. Significantly, the present invention relates to a digital V-Digest audio device for preventing an unplayed state of an original sound by scanning.

FIG. 1 is a block diagram of a digest audio generator in a conventional analog VR, which is reproduced from an audio signal circuit and samples an analog audio signal input through the audio input terminal 100, and holds and outputs the analog audio signal as a digital value. A conversion unit 101; A system microprocessor 102 for controlling the overall system operation of V-Cal according to a user's shift function and other function selections; According to the shift mode information provided by the system microprocessor 102, the digital audio data input from the analog / digital converter 101 is edited and stored in the memory 104 according to the shift and double speed, and the stored edited audio. A digest audio control logic unit 103 for reading and outputting data at 1x speed; The digital audio / audio converter 105 converts the digital audio data input at the 1x speed from the digest audio control logic unit 103 into an analog audio signal and outputs the same through the output terminal 106.

As described above, in the conventional analog VDA configured digest audio generating device, when the user designates a shift mode through a key operating means (not shown), the system microprocessor 102 receives the information corresponding to the shift mode. In addition to the digest audio control unit 103, the audio signal circuit unit and the servo system are operated in the shift mode.

As described above, when performing the shift mode of V-CAL by the system microprocessor 102, the head of the audio signal system circuit part reproduces the analog audio signal recorded on the tape at the shift and double speed, and then through the audio input terminal 100. It is input to the / digital converter 101.

The analog / digital converter 101 samples and holds an analog audio signal input at shift and double speed through the audio input terminal 100 and provides the digital audio signal to the digest audio control unit 103 as a digital value.

The digest audio control logic unit 103 sequentially edits the digital audio data input from the analog / digital conversion unit 101 according to the shift mode information provided by the system microprocessor 102 in accordance with the shift and double speed, and sequentially stores the memory. It is stored at 104.

Thereafter, when the storage of the audio data is completed, the digest audio control logic unit 103 reads the audio data stored in the memory 194 at a 1x speed and provides the digital / analog converter 105.

The digital / analog converter 105 converts audio data input at the 1x speed from the digest audio control logic unit 103 into an analog audio signal and outputs the same through the output terminal 106, so that continuous audio is reproduced during double speed playback. You can get a signal.

However, unlike the conventional analog VDA digest audio device as described above, in the present digital VLC, audio data is shuffled, ie, rearranged and stored in memory for error correction, so that the data is reproduced continuously. There was a problem that audio data could not be obtained from the head.

Accordingly, an object of the present invention is to deshuffling the shuffled audio data when recording audio data on a magnetic recording medium after the shuffling process and error correction coding during recording of the audio data. And a digital V Digest audio device for reproducing through an editing process and continuously obtaining normal audio without errors in a shift mode.

Another object of the present invention is to gradually reduce or increase the output of continuous audio data obtained through the above-described deshuffling process and editing process to remove pop noise therefrom to improve sound quality.

A digital audio digest audio device of the present invention for achieving the above object comprises: digital processing means for digitally compressing and shuffling an input video signal and an audio signal according to recording on a magnetic recording medium; Error correcting and encoding means for correcting and encoding an error of the compressed image and the shuffled audio data obtained by the digital processing means and recording it on a magnetic recording medium; Error correction and decoding means for detecting and correcting and decoding errors from the compressed video and audio data recorded on the magnetic recording medium during shift reproduction; It consists of a shift signal processing decoding means for restoring the error-corrected compressed image to the original video signal according to the shift mode provided by the microprocessor, and reconstructing audio data for one track to provide a continuous audio signal. It is done.

The digital processing means includes: a first sampling unit configured to sample and output an input video signal; An image compression unit for compressing the sampled video data and providing the error correction coding unit to the error correcting encoding unit; A pulse code modulation converter for converting an audio signal of the video signal into a pulse code modulation signal; And an audio shuffling unit which randomizes the converted pulse code modulation signal and provides the error correcting encoding unit.

The shift signal processing decoding means includes: an image decoding unit for extending and outputting the error corrected image data by the error correction decoding unit; A second sampling unit which samples the image data decoded by the image decoding unit into an original signal; Due to the shift mode of the microprocessor, half-frame audio data of one frame of audio data for one track obtained from the error correction decoding means is stored and reconstructed into one frame, and processed according to row and column shuffling addresses. An audio editing unit outputting the normal audio data rate; And a digital / analog converter for converting and outputting audio data provided by the audio editing unit into an analog audio signal.

Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an embodiment of a digital audio digest audio device of the present invention. As shown in FIG. 2, the recording video signal VS and the recording video signal VS 20 input from the video input terminal 200 and the audio input terminal 201 are respectively shown. A digital processor 202 for digitally compressing and shuffling audio signals AS in accordance with tracks of the magnetic recording medium 206; An error correcting encoder 203 for correcting an error of the compressed image processed by the digital processing unit 202 and the shuffled audio data, encoding the same, and outputting the encoded image; A recording encoder 204 for modulating the compressed video and audio data encoded by the error correcting encoder 203 to be recorded on a magnetic tape 206 through a recording head 205; A microprocessor 213 for performing overall system operation of the V-Cal in the shift mode when the shift mode is selected; A reproduction head 207 for shifting by the microprocessor 203 to read compressed video and audio data recorded on the magnetic tape 206; A signal detector 208 which detects the compressed video and audio data read from the playhead 207 and amplifies and outputs the compressed video and audio data to a predetermined level; An error correction decoding unit 209 for correcting and separately outputting errors from the compressed image and audio data amplified and input by the signal detection unit 208; The error correction decoder 209 restores each of the compressed images separately input to the original image signal, and reconstructs the audio data for the classified tracks due to the shift mode of the microprocessor 213. It consists of a shift signal processing decoding unit 210 to provide a continuous analog processing.

The digital processing unit 202 includes a first sampling unit 202a for sampling and outputting a video signal input through the video input terminal 200; An image compression unit 202b for compressing the video data inputted through the first sampling unit 202a and providing it to the error correction encoder 210c; A pulse code modulation and conversion unit (202c) for converting and outputting an audio signal input through the audio input terminal (201) into a pulse code modulation signal; And an audio shuffling unit 202d that randomizes the pulse coded modulation signal converted by the pulse code modulation and conversion unit 202c and provides it to the error correction coder 203.

The shift signal processing decoding unit 210 includes an image decoding unit 210c which extends and outputs image data input by error correction and separation input by the error correction decoding unit 209; A second sampling unit 210d for sampling and outputting the image data extended by the image decoding unit 210c as an original signal; The half frame audio data of one frame of the audio data for one track that is error corrected and separated by the error correction decoding unit 209 is stored and reconstructed due to the shift mode of the microprocessor 213 and then converted into one frame. An audio editing unit 210a configured to process the row and column despooling addresses after completion and output them as normal audio data rates; A pad in / out unit 210b for removing pop noise by increasing and decreasing the signal strength of audio data provided by the audio editing unit 210a; The digital / analog converter 210c converts the pop noise-removed digital audio data into an analog audio signal and outputs the analog audio signal to the output terminal 212.

The audio editing unit 210a deshuffles the input audio data separated by the error correction decoding unit 209 in units of frames according to the shift mode information of the microprocessor 213 to continuously output audio data. A coupling portion 21; The audio data continuously input from the audio deshuffling unit 21 is rearranged according to the shift mode of the microprocessor 213 to be provided to the pad in / out unit 210b.

In the above description, the audio deshuffling section 21 of the audio editing section 210a includes a frame memory control section 21f for generating a memory control signal in accordance with the shift mode of the microprocessor 213, as shown in FIG. ; A first address generator 21b for generating a column deshuffle address (CAD); A second address generator 21c for generating a Row Deshuffle Address (RDA); An address motion vector generator 21d for generating an address moving vector (AMV); An adder (21e) for adding and outputting an address motion vector (AMV) generated by the address motion vector generator (21d) and a row displeasure address (RDA) generated by the second address generator (21c); A column dispplied address storing audio data for one frame input from the error correcting encoder 209 according to the control signal input from the frame memory controller 21f in the first address generator 21b; By changing the row address according to the motion row displeasure address added by the adder 21e, only half the frame is stored, and data of the unsaved area is reconstructed from the stored data, and one frame audio data is continuously provided to the digest unit 22. Audio frame memory 21a.

The digest section 22 of the audio editing section 210a includes a memory control section 22c for generating a recording / reading signal in accordance with the shift mode provided by the microphone processor 213, as shown in FIG. A third address generator 22a for generating the digest address DA; Receives a read / write signal of the memory controller 22c and reconstructs audio data for one frame continuously input from the audio shuffling unit 21 by the digest address generated by the third address generator 22a. The memory 22b is stored and output to the pad in / out part 210b using a normal audio rate.

If described in detail with reference to Figures 2 to 6 the effect of the present invention configured as described above.

First, the video signal VS to be recorded and the audio signal AS thereof are first sampled 202a and the pulse of the digital processing unit 202 through the video input terminal 200 and the audio input terminal 201, respectively. When input to the code modulation and conversion unit 202c, the first sampling unit 202a samples the input video signal VS and provides it to the image compression unit 202b as a digital value.

The image compressor 202b of the digital processor 202 compresses the sampled and input image data and provides the compressed data to the error correcting encoder 203.

Meanwhile, the pulse code modulation and conversion unit 202c of the digital processing unit 202 converts the analog audio signal AS, which is input through the audio input terminal 201, into pulse code modulation data, and then converts the analog audio signal AS to the audio coupling unit 202d. Will be provided.

The audio shuffling unit 202d of the digital processing unit 202 converts the pulse code modulation signal, which is converted and input through the pulse code modulation and conversion unit 202c, in order to prevent a burst error during recording. As shown in Fig. 6, it is provided to the error correction coder 203 by shuffling.

That is, the n (integer) -th sampled data Dn in one frame is derived by the following shuffling algorithm equation to determine the sampled position.

The shuffling algorithm has a track number of one channel in a two-channel mode of 48 KHz / 44.1 KHz / 32 KHz (INT). + 2 * (n mod 3)) With mod 5, the track number of 2 channels is (INT + 2 * (n mod 3)) Obtained as mod 5 + 5.

And, sync block number is 2 + 3 (n mod 3) + INT The upper byte in the byte position number is 10 + 2 * INT Lower byte is 11 + 2 * INT Obtained by

Here, n is from 0 to 1619 in 48 KHz mode of sampling frequency, n is from 0 to 1488 in 44.1 KHz mode, and n is from 0 to 1079 in 32 KHz mode.

And, track number of 1 channel in 4 channel mode of 32KHz is (INT +2 * (n mod 3)) is obtained by mod 5, and the track number of two channels is (INT +2 * (n mod 3)) Obtained as mod 5 + 5.

Also, the sync block number is 2 + 3 * (n mod 3) + INT The upper byte (Y) in the byte position number is 10 + 3 * INT The upper limit byte (Z) is 11 + 3 * INT The lower byte is 12 + 3 * INT Obtained by

In the 32 KHz mode of the sampling frequency of the four channels, n is from 0 to 1079.

The reason why the n value is different is that since 48 KHz has a faster frequency per second than 32 KHz, more data is generated.

In this way, the audio data shuffled through the audio shuffling unit 202d is provided to the error correcting and encoding unit 203.

The error correcting encoder 203 corrects an error in recording from the image data compressed by the image compressor 202b and the audio data shuffled by the audio shuffling unit 202d, and corrects the error. ).

The recording encoder 204 encodes the compressed image data and the audio data inputted after error correction according to the recording of the magnetic tape 206, and records them on the magnetic tape 206 through the recording head 205.

As a result, audio data is shuffled and recorded on the memory map of the magnetic tape 206 as shown in FIG.

In FIG. 7, one frame of the audio consists of 10 tracks (T0 to T9), and the audio data size of one track has a size of 72 * 8 * 9 = 5184 bits.

Therefore, audio data of two channels of 48 KHz, 44.1 Khz and 32 Khz modes are recorded in the first and second channel areas CH1 and CH2 of FIG.

On the other hand, when the user designates the shift mode through the key manipulation means to reproduce the compressed video data and the audio data recorded on the magnetic tape 206, the microprocessor 213 processes the shift signal, which will be described later. In addition to providing shift mode information to the audio editing unit 210a of the decoder 210, the deck mechanism is driven in the shift mode to read compressed image data and audio data recorded on the magnetic tape 206 through the playhead 207. It will be.

The compressed image data and the shuffled audio data scanned by the playhead 207 are detected and amplified by the signal detector 208 and then provided to the error correction decoder 209.

The error correction decoding unit 209 corrects an error generated during reproduction from the compressed image data and audio data which is amplified and input, and the image data is converted into an image decoding unit 210c of the shift signal processing decoding unit 210. The shuffled audio data is provided to the audio deshuffling unit 21 of the audio editing unit 210a.

At this time, in the case of double speed playback, only one track is read from the playhead 207 along the track of the track by the azimuth angle between the tracks A and B in the track arrangement as shown in FIG.

At this time, the audio data read through the playhead 207 is shuffled, so that audio data of all tracks cannot be obtained continuously at double speed.

Therefore, in order to construct a memory map as shown in FIG. 7 in the double speed mode, the audio deshuffling unit 21 of the audio editing unit 210a reconstructs n + 1 track data from n track information to complete a frame map. .

Where n + 1 relates to the immediately neighboring audio data sampled.

And reconstruction is 2 + 3 * (n mod 3) + INT 2 + 3 * ((n + 1) mod 3) + INT at position Create new tracks by copying data from

In other words, the audio deshuffling section 21 of the audio editing section 210a includes the first and second address generating sections 21b and 21c, the address motion vector generating section 21d, and the frame memory control section 21f. , An adder 21e and an audio frame memory 21a.

The frame memory controller 21f controls the audio frame memory 21a according to the double speed information input from the microprocessor 213 at double speed.

Then, the first address generator 21b generates a column dissipation address (CDA) and provides it to the audio frame memory 21a, and the second address generator 21c and the address motion vector generator 21d. ) Generates a row dispensing address RDA and an address motion vector AMV, respectively, and provides them to the adder 21e.

The adder 21e adds the row discreet address RDA input from the first address generator 21c and the address motion vector AMV input from the address motion vector generator 21d to add the audio frame memory ( 21a).

Therefore, the audio frame memory 21a reads only one frame along the track of the track at twice the speed and is input through the error correcting / decoding unit 209 so that only the half frame audio data of the audio frame memory 21a is inputted to the first address generator. By the column dispensing address CDA of 21b) and the row dispensing address RDA inputted from the adder 21e, they are alternately stored in the corresponding area as shown in FIG.

In order to complete the frame by reconstructing the audio data of the unsaved area from the stored audio data, the audio frame memory 21a copies data of the address motion vector RDA input from the adder 21e. This completes the audio data for the frame.

As described above, when one frame of audio data is completed, the column displeasure addresses CD and the hang displeasure addresses generated by the first and second address generators 21b and 21c according to the read signal of the frame memory controller 21f. RDA) provides audio data in the address to the memory 22b of the digest 22 continuously.

The digest unit 22 rearranges audio data continuously input from the audio deshuffling unit 21 according to the double speed mode of the microprocessor 213 to provide the pad in / out unit 210b.

The digest section 22 includes a memory 22b, a digest address generation section 22a, and a memory control section 22c.

The memory controller 22c generates a write / read signal according to the double speed mode information provided by the microprocessor 213 to control the memory 22b, and the digest address generator 22a generates a digest address. To the memory 22b.

Accordingly, the memory 22b reconstructs and stores audio data continuously input in an area corresponding to the digest address input from the digest address generator 22a according to the read / write signal of the memory controller 22c. The audio data is provided to the pad-in / out part 210b at the normal audio rate.

The pad in / out part 210b may output audio of one end of the digital / analog converter 210c of the rear end and a joint part of a next period to prevent noise that may occur in the digest part 22. Since it is discontinuous, the audio data input from the memory 22b is gradually reduced or increased to eliminate pop noise.

The digital / analog converter 210c converts the audio data from which pop noise is removed through the pad in / out unit 210b into an analog audio signal and outputs a reproduced audio signal through the output terminal 212. .

In addition, the image decoding unit 210c of the shift signal processing decoding unit 210 extends the compressed image data that is error-corrected by the error correction decoding unit 210c into the original image signal, and the second sampling unit 210d. After sampling through the output terminal 211 is output.

As described in detail above, according to the present invention, when recording audio data, the audio data is recorded on a magnetic recording medium through a shuffling process and an error correction encoding process, and then the shuffled audio data is deshuffled and edited during playback. By reproducing, there is an effect of continuously obtaining a normal audio signal without error during shift reproduction, and an effect of improving sound quality by removing pop noise that may be generated during the editing process.

Claims (8)

Digital processing means for digitally compressing, shuffling, and digitally processing an input video signal and an audio signal for recording on a magnetic recording medium; Error correcting and encoding means for correcting and encoding an error of the compressed image and the shuffled audio data obtained by the digital processing means and recording it on a magnetic recording medium; Error correction and decoding means for detecting and correcting and decoding errors from the compressed video and audio data recorded on the magnetic recording medium during shift reproduction; The error corrected compressed video is restored to the original video signal according to the shift mode provided by the microprocessor, and the audio data for one track is reconstructed to analogize the row and the open dress to provide a continuous audio signal. A digital V-Digest audio device, comprising: variable speed signal processing decoding means. The digital signal processing apparatus as claimed in claim 1, wherein the digital processing means comprises: a first sampling unit for sampling an input video signal and outputting the digital video value; An image compression unit for compressing the sampled video data and providing the error correction coding unit to the error correcting encoding unit; A pulse code modulation converter for converting an audio signal of the video signal into a pulse code modulation signal; And an audio shuffling unit for randomizing the converted pulse code modulation signal and providing it to an error correcting encoding unit. The apparatus of claim 1, wherein the shift signal processing decoding means comprises: an image decoding unit which extends the error corrected image data by the error correction decoding unit to an original signal and outputs the original signal; A second sampling unit for sampling and outputting the image data decoded by the image decoding unit as an original signal; Due to the shift mode of the microprocessor, half-frame audio data of one frame of audio data for one track that has been error-corrected by the error correcting / decoding means is stored and reconstructed into one frame and then matched to row and column shuffling addresses. Audio editing means for processing and outputting the normal audio data rate; And a digital / analog converter for converting audio data provided from the audio editing means into an analog audio signal and outputting the digital audio signal. The audio editing unit of claim 3, further comprising: an audio deshuffling unit for outputting audio data continuously by deshuffling the input audio data separated from the error correction decoding unit in units of frames according to the shift mode information of the microprocessor; And a digest unit for rearranging and outputting audio data continuously inputted from the audio deshuffling unit according to a shift mode of a microprocessor. 5. The apparatus of claim 4, wherein the audio deshuffling unit comprises: a frame memory controller for generating a memory control signal in accordance with a shift mode of the microprocessor; A first address generator for generating a heat dissipation address; A second address generator for generating a hang displeasure address; An address motion vector generator for generating an address motion vector; An adder for adding and outputting an address motion vector generated by the address motion vector generator and a row dispensing address generated by a second address generator; In accordance with a control signal input from the frame memory controller, audio data for one frame input from the error correcting and encoding means is added by a column distress address stored in the first address generator and a motion hang destress address added by the adder. Digital VDS Digest Audio, which consists of an audio frame memory that stores only half a frame by changing the address number, and reconstructs the data of the unsaved area from the stored data, and continuously provides one frame audio data to the digest part. Device. The memory device of claim 4, wherein the digest unit comprises: a memory controller which generates a write / read signal in accordance with a shift mode provided by the microprocessor; A third address generator for generating a digest address; Receiving the read / write signal of the memory controller and reconstructing and storing audio data for one frame continuously inputted from the audio shuffling unit by the digest address generated by the third address generator, and outputting the audio data as a normal audio ratio. Digital VDS Digest Audio Device, characterized by a memory. 5. The digital V-Digest audio device according to claim 3 or 4, further comprising a pad in / out unit for removing pop noise by increasing and decreasing the audio data obtained from the digest unit. 6. The digital V Digest audio device according to claim 5, wherein the audio frame memory alternately stores half frame data of one audio frame for one track and completes the data of one frame by an address motion vector.