JP3318771B2 - Digital signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital VT of any format for compressing and recording data using a modulatable code such as D1 format or D2 format.
The present invention relates to a digital signal processing device suitable for application to R and the like.

[0002]

2. Description of the Related Art Conventionally, digital VTRs have been proposed which convert video and audio signals into digital data, record the digital data obtained by the conversion on a magnetic tape, and reproduce the digital data recorded on the magnetic tape. Widely used in etc.

The recording of a signal on a magnetic tape in a digital VTR (for example, a digital VTR in the D2 format) will be described. An analog video signal is converted into digital data, and an outer code is added to the converted digital data by an outer code circuit. Then, the digital data to which the outer code is added is shuffled by a shuffling circuit, an inner code is added to the shuffled digital data, and then channel coding is performed, and a magnetic tape is formed so that an inclined track is formed by a magnetic head. Record the recording signal. Here, in the D2 format, six tracks constitute one field.

[0004] The reproduction of the recording signal recorded on the magnetic tape will be described. The recording signal recorded on the magnetic tape is reproduced by a magnetic head, and the reproduced signal is amplified and equalized. A decoder decodes the channel, synchronously detects a reproduced signal obtained by this decoding by a synchronous signal detecting circuit, decodes the reproduced signal by an inner code decoder, temporarily accumulates the decoded output in a buffer, and then temporarily stores the decoded output in the buffer. The read signal is read out again, and the signal is de-shuffled by a de-shuffle circuit, the read signal subjected to the de-shuffle processing is decoded by an outer code decoder, and an error correction circuit corrects an error in the decoded reproduced signal. After that, it is converted into an analog signal and output.

The data on the tape of such a digital VTR and an ECC (Error Correction Code) block will be described with reference to FIG.

In general, a Reed-Solomon code is used for error correction of a digital VTR, and the error correction capability is enhanced by using a product code. At the time of recording, as shown in FIG. 4, recording is performed on the magnetic tape 11 with the inner code block of the ECC block as the minimum unit.

That is, all data of the ECC block 10 shown in FIG. 4A is recorded on the track trn + 4, for example, of the tracks trn to trn + 10 formed on the magnetic tape 11 shown in FIG. 4B. Further, as shown in the enlarged portion of the track trn + 4 shown by a solid circle in FIG. 4B, a certain portion is the n-th and n-th of the inner code block.
It can be seen that recording is performed with the + 1st, n + 2nd, and n + 3rd as the minimum units of the inner code block.

[0008] Generally, one or two inner code blocks are collected to make a minimum recording unit, and this is called a sync block. FIG. 4 shows this sync block sb.
Is shown.

As described above, in a digital VTR in which an analog signal is converted into digital data and recorded on a magnetic tape, particularly in a digital VTR that does not use a data compression technique such as D1 or D2, when reproducing at a normal tape speed, With reference to FIG. 3, a description will be given of a signal processing circuit of a portion for performing signal processing of a reproduction system at the time of so-called shuttle reproduction (variable reproduction) at a speed different from a normal tape speed.

The signal processing circuit shown in FIG. 3 detects synchronization of a reproduction signal supplied through an input terminal 1 by a synchronization detection circuit 2, and after detecting synchronization by the synchronization detection circuit, an inner code circuit for the reproduction signal. In step 3, an error correction process using an inner code is performed. The reproduction data on which the error correction process has been performed is stored in the field memory 4, and the reproduction data stored in the field memory 4 is read.

The timing of writing and reading data to and from the field memory 4 will be described with reference to FIG. 5. As shown in FIG.
Are sequentially set to be shorter than the period of one field for each field (referred to as "write" in the figure), and the reading (referred to as "read" in the figure) is set to be slightly earlier than the writing start time. .

During normal reproduction, the movable contact 5c of the switch 5 is connected to the fixed contact 5n on the normal reproduction side, and during shuttle reproduction, the movable contact 5c of the switch 5 is connected to the fixed contact 5s on the shuttle reproduction side.

Therefore, at the time of normal reproduction, the data read from the field memory 4 is supplied to the outer coding circuit 6 and subjected to error correction processing by the outer coding circuit 6, and then to the output terminal 7.
To other signal processing circuits (not shown) of the VTR.

On the other hand, at the time of shuttle reproduction, the data read from the field memory 4 is delayed by a delay 8 in which a delay time for error correction by the outer code circuit 6 is set.
Thereafter, the signal is supplied to another circuit (not shown) of the VTR via the output terminal 9.

Next, a case where the magnetic tape 11 recorded as shown in FIG. 4 is reproduced by shuttle reproduction will be described with reference to FIG.

First, as shown in FIG. 6A, at the time of shuttle reproduction, the head scans as shown by a solid arrow h in the figure (the trajectory of this scanning is conceptually shown for convenience of explanation). At this time, data n0 to na of each track is written in the field memory 4 as shown in FIG. 6B.

Reading from the field memory 4 is performed in the order shown by the solid arrow in FIG. 6C in order to perform error correction using an outer code.

Here, since the timing of writing and reading data to and from the field memory 4 is the timing described with reference to FIG. 5, the data is rewritten in the inner code block as shown in FIG. 6D.

However, in the case of a conventional digital VTR, since each symbol is independent, there is no problem even if data having different time axes are mixed in one inner code block. That is, as described with reference to FIG. 3, error correction is not performed on the reproduced data by the outer code circuit 6 during shuttle reproduction, and the data is delayed by the delay 8 that gives a delay time corresponding to the processing time of the outer code circuit 6 to the data. Is given a delay time.

[0020]

A digital VTR for compressing and recording data by using a variable length code.
In consideration of the above, since variable-length codes are encoded and decoded in block units, decoding cannot be performed if the encoded blocks are not completely reproduced.

Although the compression efficiency increases as the size of the variable-length blocks increases, it is desirable that the variable-length blocks be the same as the sync blocks in consideration of shuttle reproduction in which data can be obtained only in sync units.

Although the variable-length block may be smaller than the sync block, a certain size is required in consideration of the compression efficiency, and reproducibility in block units is necessary for decoding.

If a digital VT using a variable length code
When the signal processing similar to the conventional one is performed by the circuit as shown in FIG. 3 when the shuttle reproduction is performed in R, since the data is rewritten in the sink as shown in FIG. 6D, the variable length block is not reproduced. Therefore, this block is erroneously decoded.

In the variable-length code, since one symbol is not independent of each other, two data, 0.8 data,
There is also a case of 0.5. In other words, the variable length code does not have data breaks at symbol breaks, so decoding can be performed only when handled as a data string, and only one symbol has no meaning.

That is, when a signal processing circuit used in a conventional VTR is used, a digital VTR using a variable length code is used.
There is a disadvantage that shuttle reproduction cannot be performed in TR.

The present invention has been made in view of the above points, and it is an object of the present invention to propose a digital signal processing circuit capable of performing shuttle reproduction satisfactorily when applied to a digital VTR using a variable length code. .

[0027]

The digital signal processing apparatus according to the present invention comprises, as shown in FIG. 1 and FIG.
And an address generating means 34 for supplying read address data and write address data to the storage means 4. The data written to the storage means 4 is read at the time of reproduction at normal speed and at the time of reproduction at a speed different from the normal speed. The direction was changed.

[0028]

[0029]

[0030]

According to the present invention described above, the read direction of the data written in the storage means 4 is changed between the time of reproduction at the normal speed and the time of reproduction at a speed different from the normal speed. In this case, the data written in the storage means can be prevented from being destroyed during the reproduction of the data, whereby good shuttle reproduction can be performed when applied to, for example, a digital VTR using a variable length code.

[0031]

[0032]

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the digital signal processing apparatus according to the present invention will be described below in detail with reference to FIG. In FIG. 1, portions corresponding to those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, a signal is supplied from a digital VTR (not shown) (a digital VTR for compressing and recording data using a variable length code and / or reproducing the data recorded in this way) via an input terminal 1. The synchronous detection circuit 2 detects the synchronization of the reproduced data, and then performs an error correction process (for example, correction of a random error) on the reproduced data by an inner code in an inner encoding circuit 3. Is supplied to the switch 30.

The switch 30 performs a connection operation in response to a switching signal from the synchronization detection circuit 33, and falls to the buffer 32 side when data is rewritten in the middle of the sync, and falls to the field memory 4 otherwise.

The switch 31 is closed only when data in the buffer 32 is written into the field memory 4.

The writing of the data supplied through the switches 30 and 31 to the field memory 4 and the reading of the data written to the field memory 4 are performed by the write address signal and the read address signal from the address generating circuit 34.

The address generation circuit 34 generates a write address and a read address signal, and supplies the generated address to the field memory 4 and the synchronization detection circuit 33. The read address output of the address generating circuit 34 has two outputs for shuttle reproduction and normal reproduction. These two outputs are respectively supplied to a shuttle reproduction side fixed contact 35s and a normal reproduction side fixed contact 35n of the switch 35, respectively. Supplied.

This switch 35 is switched by a switching signal from a digital VTR main circuit (not shown). That is, when the VTR is in shuttle reproduction, the movable contact 35c of the switch 35 is set to the shuttle reproduction side fixed contact 35s.
When the VTR performs normal reproduction, the movable contact 35c of the switch 35 is connected to the normal reproduction-side fixed contact 35n.

The synchronization detection circuit 33 detects a match between the write address and the read address from the address generation circuit 34 (however, the read address during shuttle reproduction), and according to the detection result, the buffer 32 and the switch 3
Control for 0 and 31 is performed.

The data read from the field memory 4 is delayed by the delay 8 by the processing time of the outer code circuit 6 by connecting the movable contact 5c of the switch 5 to the fixed contact 5s on the shuttle reproduction side during shuttle reproduction. After that, it is supplied to another circuit of the digital VTR (not shown).

At the time of normal reproduction, the movable contact 5c of the switch 5 is connected to the fixed contact 5n on the normal reproduction side to be supplied to the outer code circuit 6, where, for example, a burst error correction process is performed. Thereafter, the signal is supplied to another circuit (not shown) of the digital VTR via the output terminal 7.

Next, the main operation of the main part of the above-mentioned digital signal processing apparatus will be described. During normal reproduction, the switch 30 falls to the field memory 4 side and the movable contacts 5c and 35c of the switches 5 and 35 are normally The data is written to the field memory 4 by being connected to the reproduction-side fixed contacts 5n and 35n. And this field memory 4
6 is read out by the read address signal for normal reproduction from the address generation circuit 34 as shown in FIG. 6C, and then supplied to the outer code circuit 6 via the switch 5 to be read as an error. After being corrected, it is supplied to another circuit (not shown) of the VTR via the output terminal 7.

On the other hand, at the time of shuttle reproduction, as shown in FIG. 2A, na is read from recorded data n0 of each track, and at the same time, each movable contact 5c of switches 5 and 35 is read.
And 35c are fixed contacts 5s and 3 respectively on the shuttle reproducing side.
Connect to 5s.

The switch 30 is connected to the field memory 4
Then, the data is supplied to the field memory 4. At the same time, a write / read (for shuttle reproduction) address signal from the address generation circuit is supplied to the field memory 4, and write and read are performed as shown in FIGS. 2B and 2C. Here, at the time of normal reproduction, reading is performed as shown in FIG. 6C, but at the time of shuttle reproduction, reading is performed differently from that at the time of normal reproduction as shown in FIG. 2C. Therefore, the data is hardly rewritten as shown in FIG. 2D. In parallel with this, the synchronization detection circuit 33
Detects the coincidence of the write address and read address signals from the address generation circuit 34.

When a match is detected (or a timing at which a match occurs), that is, when a sync in which data is rewritten halfway is detected, a control signal is supplied to the switch 30 and the switch 30 is moved to the buffer 32 side. At the same time, for example, a write signal is supplied to the buffer 32. Thus, the sync block data whose data is rewritten is written to the buffer 32.

At this time, no data is written to the field memory 4. Therefore, the data is not rewritten.

The writing of the data stored in the buffer 32 into the field memory 4 is performed during a period in which neither writing nor reading is performed, or a period in which writing is not performed.
In this case, the synchronization detection circuit 33 controls the switch 31 to close the switch 31 and supplies a read signal to the buffer 32. Thus, the data from the buffer 32 is written to the corresponding area of the field memory 4.

As described above, in this example, a sync block that is rewritten in the middle of a read operation stops writing to the field memory, and a sync block that is rewritten in the middle of a read operation is first stored in the buffer once. Since the data is written to the field memory where there is no possibility that the data is stored and rewritten, even if the timing of the writing to the field memory overlaps, for example, as shown in FIG. 5, the data is compressed using the variable length code. Good shuttle playback on the digital VTR recorded by the above is possible.

As another example of the above example, for example, VT
A method may be used in which the data reproduced by the R head is compressed in the time axis direction so that the write and read timings of the field memory do not overlap. For example, before writing the reproduction data to the field memory, the data is compressed in the time axis direction using a FIFO (first-in first-out) memory or the like so that the write / read timing of the field memory is not overlapped, and the read is performed. So that new data is not written in the middle of
Avoid destruction. In this way, it is possible to avoid different variable-length blocks from being mixed in one sync, thereby enabling shuttle reproduction only by compressing the reproduction data on the conventional digital VTR on the time axis.

The above-described embodiment is an example of the present invention.
It goes without saying that various other configurations can be adopted without departing from the spirit of the present invention.

[0052]

According to the present invention described above, the read direction of the data written in the storage means is changed between the reproduction at the normal speed and the reproduction at a speed different from the normal speed. The data written in the storage means can be prevented from being destroyed at the time of the reproduction of the speed, so that there is an advantage that, when applied to a digital VTR using, for example, a variable length code, good shuttle reproduction can be performed.

[0053]

[0054]

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a digital signal processing device of the present invention.

FIG. 2 is an explanatory diagram for explaining an embodiment of a digital signal processing device according to the present invention;

FIG. 3 is a configuration diagram showing an example of a conventional digital signal processing device.

FIG. 4 is an explanatory diagram showing an arrangement of sync blocks on a tape for explaining a conventional digital signal processing device.

FIG. 5 is an explanatory diagram showing write / read timing of a field memory for explaining a conventional digital signal processing device.

FIG. 6 is an explanatory diagram showing data processing during shuttle reproduction for explaining a conventional digital signal processing device.

[Explanation of symbols]

 3 inner code circuit 4 field memory 32 buffer 33 address generation circuit 34 synchronization detection circuit

Claims (1)

(57) [Claims] 1. A storage device comprising: a storage unit; and an address generation unit that supplies read address data and write address data to the storage unit. A digital signal processing apparatus wherein the readout direction is changed between the time of reproduction and the time of reproduction.