JPH08163498A - Digital signal recorder - Google Patents

Abstract

PURPOSE: To improve the error correction capability of an error correction check code at usual or high speed reproduction in a digital VTR receiving a digital video signal and a digital audio signal in a form of a bit stream and recording/reproducing the bit stream. CONSTITUTION: When a head 27 scans a recording medium at a predetermined high reproduction speed, an area to record special reproduction data and error correction check codes is provided onto a scanning track of the head 27, and an error correction check code added to special reproduction data or at least an error correction check code added to data outputted from a recording data generating means is recorded to the area recording the error correction check codes and an identification of the error check correction code recorded in the recording area is added and recorded in the recording signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video tape recorder having a track format for recording a digital video signal and a digital audio signal in predetermined areas of diagonal tracks (hereinafter
It is referred to as a digital VTR. ), A digital video signal and a digital audio signal are input in a bit stream, and the digital signal recording apparatus records the bit stream.

[0002]

2. Description of the Related Art FIG. 16 is a track pattern diagram of a conventional general household digital VTR. In the figure, a diagonal track is formed on the magnetic tape, and one track is a video area for recording a digital video signal,
It is divided into two areas, an audio area for recording digital audio signals.

There are two methods for recording video and audio signals on such a home digital VTR. One is a so-called baseband recording method in which an analog video signal and an audio signal are input and high-efficiency coding is performed on the video signal and the audio signal to reduce the data rate for recording. The other is a so-called transparent recording system for recording a digitally transmitted bit stream.

ATV being discussed in the United States
The latter transparent recording method is suitable for recording the (Advanced Television) signal. The reason is that the ATV signal is already a digitally compressed signal and a high-efficiency encoder or decoder is not necessary, and since it is recorded as it is, there is no deterioration in image quality. On the other hand, the disadvantage is the image quality during high-speed reproduction, special reproduction such as still and slow reproduction. Particularly, if the bit stream is recorded on the diagonal track as it is, almost no image can be reproduced at the time of high speed reproduction.

As a method of the digital VTR for recording the above-mentioned ATV signal, "Intern" held in Ottawa, Canada from October 26 to 28, 1993.
national Workshop on HDTV '
"A Recording" in the technical announcement in "93"
Method of ATV data on aC
There is an "Digital Summarization VCR". Hereinafter, this content will be described as a conventional example.

As a basic specification of a home digital VTR prototype, SD (Standard Define) is used.
mode), the recording rate of the digital video signal is 25 Mbps, and the field frequency is 60 Hz.
In some cases, one frame of video is recorded in a video area of 10 tracks. Here, if the data rate of the ATV signal is set to 17 to 18 Mbps, transparent recording of the ATV signal becomes possible in this SD mode.

FIG. 17 is a diagram showing the head scanning loci of the rotary head during normal reproduction and high-speed reproduction of the conventional digital VTR. In the figure, adjacent tracks are alternately recorded obliquely by a rotary head having different azimuth angles. During normal playback, the tape feed speed is the same as during recording, so the rotary head moves along the recording track.
It can be traced as shown in FIG. However, during high speed reproduction, the tape speeds are different, so that it is possible to trace across several tracks and reproduce only the fragments of each same azimuth track. FIG. 17B shows the case of fast-forwarding at 5 times speed.

In the MPEG2 bitstream (the ATV signal bitstream conforms to the MPEG2 bitstream), only intra-coded blocks can be independently decoded without referring to other frames.
If the MPEG2 bit stream is recorded on each track in sequence, the reproduction data at the time of high-speed reproduction is the intra-coded data separated from the reproduction signal reproduced intermittently. The image will be reconstructed using only the data. At this time, the reproduced area is not continuous on the screen, and the block fragments spread on the screen. further,
Since the bitstream is variable length encoded, there is no guarantee that all of the screen will be updated periodically, and some may not be updated for a long time. as a result,
The image quality at the time of high-speed reproduction cannot be said to be sufficient, and it cannot be accepted in a home digital VTR.

FIG. 18 is a block diagram of a conventional digital VTR capable of high speed reproduction. Here, the video area of each track includes a main area for recording bit streams of all ATV signals, and an important part (HP) of a bit stream used when an image is constructed during high-speed reproduction.
(Data) is divided into a copy area for recording. During high-speed playback, only the intra-coded block is effective, so this is recorded in the copy area. However, in order to further reduce the data, the low-frequency components are extracted from all intra-coded blocks and the HP data To record as. FIG.
In FIG. 8, 1 is an input terminal of a bit stream, 2 is an output terminal of a bit stream, 3 is an output terminal of HP data, 4 is a variable length decoder, 5 is a counter, 6 is a data sampling circuit, and 7 is an EOB (End of of). Block) additional circuit.

The MPEG2 bit stream is input from the input terminal 1 and output from the output terminal 2 as it is,
It is sequentially recorded in the main area. On the other hand, the bit stream from the input terminal 1 is also input to the variable length decoder 4,
The syntax of the MPEG2 bit stream is analyzed, an intra image is detected, timing is generated by a counter 5, a low frequency component of all blocks of the intra image is extracted by a data extracting circuit 6, and E
The OB adding circuit 7 adds EOB to form HP data and records it in the copy area.

FIG. 19 is a conceptual diagram of a system when normal reproduction and high-speed reproduction are performed by a conventional digital VTR. During normal reproduction, all bit streams recorded in the main area are reproduced and sent to an MPEG2 decoder outside the digital VTR. HP data is discarded. On the other hand, during high speed reproduction, only HP data in the copy area is collected and sent to the decoder, and the bit stream in the main area is discarded.

Next, the arrangement of the main area and the copy area on one track will be described. FIG. 20 is a diagram showing an example of the rotary head scanning locus during high-speed reproduction. If the tape speed is an integral multiple speed and phase lock control is performed, head scanning is synchronized with the same azimuth track. Therefore,
The position of the reproduced data is fixed. In FIG. 20, assuming that a portion where the output level of the reproduction signal is higher than −6 dB is reproduced, a shaded area is reproduced by one head. FIG. 20 shows an example of 9 × speed. At 9 × speed, signal reading in this shaded area is guaranteed. Therefore, HP data may be recorded in this area. However, at other speeds, signal reading is not guaranteed and this area must be chosen for reading at some tape speeds.

FIG. 21 is a diagram for explaining the conventional overlapping areas at a plurality of high-speed reproduction speeds, showing an example of three tape speed scan areas in which the heads are synchronized with the same azimuth track. The area scanned at each tape speed has some overlapping areas. A copy area is selected from these areas to ensure the reading of HP data at different tape speeds. In FIG. 21, 4 times, 9 times,
Although the case of fast-forwarding at 17 times is shown, these scan areas are the same as the case of fast-forwarding at −2 times, −7 times, and −15 times.

At some tape speeds it is not possible for the head to trace the exact same area. This is because the number of tracks traversed by the head differs depending on the tape speed. In addition, it should be possible to trace from any one of the same azimuth tracks. FIG. 22 shows a conventional digital VTR.
FIG. 6 is a diagram showing an example of rotary head scanning loci at 5 × speed and 9 × speed, in which regions 1, 2, and 3 are selected from overlapping regions of 5 × speed and 9 × speed. By repeatedly recording the same HP data on 9 tracks, the HP data becomes 5
Both double speed and 9 times speed can be read.

FIG. 23 shows two rotary head scanning loci at the time of 5 × speed reproduction in the conventional digital VTR. As can be seen, by repeatedly recording the same HP data on the same number of tracks as the tape speed, the HP data can be read by the head synchronized with the same azimuth track. Therefore, by duplicating the HP data for the same number of tracks as the maximum tape speed for high-speed reproduction, the duplicate HP data can be guaranteed to be read at both the forward and backward directions at some tape speeds. You can

FIG. 24 is a track layout diagram in a conventional digital VTR, showing an example of a main area and a copy area. In the home digital VTR, the video area of each track is composed of 135 sync blocks, the main area is 97 sync blocks, and the copy area is 32 sync blocks. This copy area is shown in FIG.
The overlapping area corresponding to 4, 7, and 17 times speed shown by is selected. In this case, the main area data rate is about 1
Since the same data is recorded in the copy area 17 times at 7.46 Mbps, it becomes about 338.8 kbps.

[0017]

Since the conventional home-use digital VTR is constructed as described above, special reproduction data is recorded in the copy area many times, which results in special reproduction. The recording rate of the data for use is extremely low, and there is a problem in that a reproduced image quality cannot be sufficiently obtained particularly in slow reproduction or high speed reproduction. For example, if the intra-frame is 2 frames / second, ATV
The data amount of only intra-coding of the signal is predicted to be about 3 Mbps, but in the conventional example, only about 340 Kbps can be recorded, and the reproduced image quality is extremely deteriorated.

FIG. 25 shows the structure of the error correction code in the video signal area and audio signal area in one track of the digital VTR defined in the SD mode (hereinafter referred to as SD standard). In the SD standard, the error correction code of the video signal area is recorded in the recording direction (85, 7
7, 9) Reed-Solomon code (hereinafter, referred to as C1 check code) is used in the vertical direction (149, 138, 12) Reed-Solomon code (hereinafter, referred to as C2 check code). Also, as an error correction code in the audio signal area, the same as the video signal in the recording direction (85, 77, 9)
Reed-Solomon code (C1 check code) is used in the vertical direction (14, 9, 6) Reed-Solomon code (hereinafter referred to as C3 check code). The structure of one sync block is shown in FIG. As shown in FIG. 26, it is composed of 90 bytes, in which the sync pattern and the ID signal are recorded in the first 5 bytes, and the error correction code (C1 detection code) is recorded in the rear 8 bytes. It

As described above, the ATV signal is data-compressed using the compression method based on motion compensation prediction. The compressed data is the intra data (field, field, which can restore the image using only the reproduced data).
Or intra-frame coding) and inter-data (field or inter-frame coding) for restoring an image using reference field (or frame) data and reproduction data. Therefore, if an error occurs in the reproduced data, the error propagates to a plurality of fields or frames in the ATV signal, which is visually unsightly. Further, when the SD standard digital VTR is used as a storage medium for storing data such as a computer or a program, it may be a dropout caused by scratches on the tape or dust adhering to the magnetic tape. It is desired to add a stronger error correction code to the data that has not been reproduced so as to restore it (error correction).

Further, during special reproduction (high-speed reproduction, slow reproduction, still reproduction, etc.), since the rotary head crosses the recording track diagonally, the reproduction signal is intermittently reproduced from each track. Therefore, an error correction block (video data) as shown in FIG. 25 (a) cannot be constructed during special reproduction. Therefore, during special reproduction, only the error correction by the C1 check code is applied to the reproduced data.

When only the error correction by the C1 check code is applied and the symbol error rate is 0.01, the error detection probability is 1.56 × 10 ⁻³ , and one error is detected in about 8 sync blocks. Will be Especially during special reproduction, the reproduction output is not stable, so that the symbol error rate often becomes 0.01 or more. Since the record data is variable-length coded, if an error occurs, the following reproduction data cannot be used, which causes deterioration of reproduction image quality. Further, residual error is also very occurrence frequency as high as 7.00 × 10 ^{over 8.}

The present invention has been made to solve the above problems, and particularly improves the reproduction image quality by improving the error correction capability for correcting an error that occurs during normal reproduction or high speed reproduction. An object of the present invention is to obtain a digital signal recording device capable of improving the reproduction image quality during high speed reproduction by improving the recording rate of high speed reproduction data.

[0023]

According to a first aspect of the present invention, there is provided a digital signal recording apparatus, which is a digital image coded in a frame or a field or in a frame or an interfield encoded in a transport packet state. In a digital signal recording device in which a signal and a digital audio signal are transparently recorded, a data separation means for separating a frame or field encoded digital video signal from the transport packet, and a separation means by the data separation means. The special reproduction data generating means for reconstructing the reproduced digital video signal subjected to the intra-frame or field encoding and the special reproduction data and the sync for reconstructing the input transport packet data. Block fo Area for recording the special reproduction data and the error correction check code on the scanning locus of the head when the head scans the recording medium at a predetermined high-speed reproduction speed for generating a matte. In addition, the area for recording the error correction check code is provided with either the error correction check code added to the special reproduction data or at least the error correction check code added to the data output from the recording data generating means. One of the data is recorded, and a recording format is generated so that an identification signal of the error correction code recorded in the recording area of the error correction check code is added and recorded in the recording signal.

Further, in the digital signal recording apparatus according to the second aspect of the present invention, when the sync block format is generated by the recording data generating means, the input m transport packets are used to synchronize the n-line sync. A recording format is configured to generate block data and arrange the recording data so that the data of the sync block of the n-line output from the recording data generation unit is not recorded over a plurality of recording tracks. Is.

According to a third aspect of the present invention, in the digital signal recording apparatus, the special reproduction data generated by the special reproduction data generating means is generated and recorded in the form of the input transport packet. Sometimes, it is configured to be converted into a sync block format and recorded in the same manner as the input transport packet.

According to a fourth aspect of the present invention, in the digital signal recording apparatus, when the error correction check code is added to at least the data output from the recording data generating means, the data is recorded using two tracks of data. An error correction code circuit is configured which configures a block and adds an error correction check code to normal reproduction data so as to interleave data of a plurality of blocks of the data block and generate an error correction check code.

The digital signal recording apparatus according to a fifth aspect of the present invention generates a recording format so that the recording area of the error correction check code is arranged adjacent to the special reproduction data recording area. is there.

According to a sixth aspect of the present invention, in the digital signal recording apparatus, the interleaving depth of the data applied when generating the error correction check code added to the recording data generating means is 10 tracks in the NTSC range. In the PAL and SECAM areas, the depth of 12 tracks constitutes the error correction block for normal reproduction.

According to a seventh aspect of the present invention, in the digital signal recording device, an identification signal for identifying the data recorded in the error correction check code recording area is transmitted by the recording data generating means to the transport packet. When the data is converted into the sync block format, a recording area is provided in a data recording portion which is left over and an identification flag is transmitted.

Further, in the digital signal recording apparatus according to the eighth aspect of the present invention, when the error correction check code is added to the output of the recording data generating means, the output of the recording data generating means and a part or all of the output. The data block is constructed by using the output from the special reproduction data generating means.

[0031]

In the digital signal recording apparatus according to the first aspect of the present invention, a digital video signal, which is input in the form of a transport packet, is encoded in a frame or a field, or is encoded between frames or a field, and a digital audio signal. In a digital signal recording device in which a signal and a signal are transparently recorded, first, a digital video signal (hereinafter, referred to as an intra image signal) that has been subjected to frame or field encoding is separated from the transport packet. And
The separated intra-image signal has the high frequency component removed from the image signal, and the recording rate is further compressed. Then, the intra-picture signal whose recording rate is compressed is reconstructed to generate special reproduction data. On the other hand, the input transport packet data is reconstructed and converted into the sync block format. When recording the special reproduction data, the head is arranged on the scanning locus of the head when the head scans the recording medium at a predetermined high reproduction speed. At that time, the area for recording the error correction check code is also arranged on the scanning locus of the head. In the area for recording the error correction check code, either the error correction check code added to the special reproduction data or at least the error correction check code added to the record data converted into the sync block format is used. The data is recorded, and the recording format is generated so that the identification signal of the error correction code recorded in the recording area of the error correction check code is added and recorded in the recording signal.

Further, in the digital signal recording apparatus according to the second aspect of the present invention, when the sync block format is generated by the recording data generating means, the input n transport packets are used for the m line recording. Generate sync block data. Further, when recording the converted sync block format data on the recording medium, the recording format on the recording medium is configured such that the data of the m sync blocks is arranged on the same track.

Further, in the digital signal recording apparatus according to claim 3 of the present invention, when the special reproduction data generating means is used to generate the special reproduction data by using the inputted intra image data, the special reproduction data is inputted. It is generated in the form of transport packets. When the trick play data generated in the transport packet format is recorded on the recording medium, it is converted into the sync block format and recorded like the input transport packet.

Further, in the digital signal recording apparatus according to the fourth aspect of the present invention, when the error correction check code is added to at least the data output from the recording data generating means, the recording data of two tracks is used. Construct a data block. Then, a plurality of the data blocks are collected to form an error correction block of the normal reproduction data. Then, the data in the error correction block for normal reproduction is interleaved to generate an error correction check code.

Further, in the digital signal recording apparatus according to the fifth aspect of the present invention, the recording area of the error correction check code is arranged adjacent to the special reproduction data recording area.

Further, in the digital signal recording apparatus according to the sixth aspect of the present invention, the interleaving depth of the data applied when generating the error correction check code added to the recording data generating means is 10 in the NTSC range. The error correction block for normal reproduction is constructed with a depth of 12 tracks in the PAL and SECAM areas, and the normal reproduction data is interleaved to generate an error correction check code for normal reproduction.

Further, in the digital signal recording apparatus according to the seventh aspect of the present invention, the data transmitted in the transport packet format represented by MPEG2 is converted into the above-mentioned S
When recording on a digital VTR typified by the D standard, when the sync block format is generated by the recording data generation means, data of n lines of sync block is generated using the input m transport packets. . At that time, an identification signal for identifying the data recorded in the error correction check code recording area is recorded in a data recording portion left over when the transport packet is converted into the sync block format by the recording data generating means. It is provided in an area and is configured to transmit an identification signal.

In addition, in the digital signal recording apparatus according to the eighth aspect of the present invention, when the error correction check code is added to the output of the recording data generating means, the output of the recording data generating means, and part or all of the output. The data block is constructed by using the output from the special reproduction data generating means. Then, a plurality of blocks of the above data blocks are collected and interleaved on the data to form an error correction check code for normal reproduction.

[0039]

【Example】

Example 1. FIG. 1 shows a digital V which is an embodiment of the present invention.
It is a block configuration diagram of a recording system of TR. In the figure, 1
Is an input terminal of a transport packet. Reference numeral 10 detects a transport header in a transport packet and also detects a header such as a sequence header or a picture header included in a bitstream, and performs frame or intra-field coding (hereinafter referred to as intra coding). A header analysis circuit for separating data, 11 is a parallel / serial circuit (hereinafter, referred to as P / S conversion circuit) for performing parallel / serial conversion of an input transport packet into 1-bit bit stream data, and 12 is Based on the header information detected by the header analysis circuit 10, bit stream data of a frame or intra-field coded image (hereinafter referred to as an intra image) is separated, and each high reproduction speed (in the present embodiment). 1 generates special playback data at 4x speed and 18x speed) It is a special playback data generating circuit.

Reference numeral 13 temporarily stores the transport packet input from the input terminal 1 in the memory, and at the time of outputting the data, converts it into the sync block format shown in FIG. 6B (details will be described later). The first memory, 14 is a quadruple speed data generation circuit for generating a quadruple speed special reproduction transport packet using the quadruple speed reproduction data output from the special reproduction data generation circuit 12, and 15 is a special memory. This is a 18x speed data generation circuit that generates 18x speed special reproduction transport packets using the 18x speed reproduction data output from the reproduction data generation circuit 12.

Numeral 16 temporarily stores in the memory the data for quadruple speed reproduction input in the form of transport packets, and at the time of outputting the data, converts it into a sync block format (see FIG. 6 for details). The second memory 17, 17 temporarily stores the 18 × speed reproduction data input in the form of transport packets in the memory, and converts the data into the sync block format when outputting the data (see FIG. 6 for details. This is the third memory. A first error correction code circuit 18 adds a special reproduction error correction code (hereinafter referred to as a C5 check code) to each special reproduction data output from the second memory 16 and the third memory 17. , 19 is the first memory 13
A data synthesizing circuit for rearranging the input transport packet output from the first error correction coding circuit 18 and the data output from the first error correction coding circuit 18 in a predetermined sync block order, and 20 for command and servo information input terminals. is there.

Reference numeral 21 indicates whether the recording mode of the error correction code at the time of recording is the special reproduction error correction code recording mode or the normal reproduction error correction based on the command information and servo information input from the input terminal 20. A control signal indicating which of the error correction check codes (the error correction code for special reproduction and the error correction code for normal reproduction) to be recorded in the error correction check code recording area, which will be described later, is discriminated. 1 error correction code circuit 18, data synthesizing circuit 1
9, an error correction code control circuit that outputs a control signal to the second error correction code circuit 23, the third error correction code circuit 24, and the digital modulation circuit 25.

Reference numeral 22 is a fourth memory, 23 is a second error correction code circuit for adding an error correction check code (hereinafter referred to as C4 check code) to normal reproduction data, and 24 is a fourth memory.
Of the data output from the memory 22 in the horizontal direction (C1 check code) and the vertical direction (C2) defined by the SD standard.
(Check code) error correction check code is added to the third error correction code circuit. 25 is a third error correction code circuit 24
This is a digital modulation circuit that digitally modulates the data output from it. The ID information and sync information are added to the data of each sync block at the time of input to the digital modulation circuit 25. Reference numeral 26 is a recording amplifier, 27a is a rotary head for recording / reproducing A track data, 27b is a rotary head for recording / reproducing B track data, and 28 is a rotary drum.

FIG. 2 is a block diagram of a trick play data generation circuit 12 which is an embodiment of the present invention. It should be noted that, in the figure, components having the same reference numerals as those of the conventional example have the same configuration and operation. Reference numeral 30 denotes an input terminal for inputting a bitstream of frame- or field-encoded data (hereinafter referred to as intra data), 31
Reference numerals a and 31b are output terminals for 4 × speed reproduction data and 18 × speed reproduction data. Reference numeral 4 is a variable length decoder for performing variable length decoding on the input intra data, 5 is a counter, 6a and 6b are data for quadruple speed reproduction from a bit stream of the input intra data, and 18
Data sampling circuit for sampling data for double speed playback, 7
a and 7b are EOB at the end of each DCT block
(End Of Block) EOB that adds a code
It is an additional circuit.

FIG. 3 is a block diagram of a quadruple speed data generating circuit 14 which is an embodiment of the present invention. In addition, since the circuit configurations of the 4 × speed data generation circuit 14 and the 18 × speed data generation circuit 15 are the same, in the first embodiment, 1 is set.
Detailed description of the 8 × speed data generation circuit 15 is omitted.
Reference numeral 40 is an input terminal for header information such as a transport header, sequence header, picture header and the like output from the header analysis circuit 10 and additional information such as a quantization table, and 41 is output from the special reproduction data generation circuit 12 Input terminal for double speed reproduction data, 42 is input terminal 40
A transport header correction circuit that corrects and outputs the input transport header, 43 is a sequence header detected by the header analysis circuit 10 in the 4 × speed reproduction data output from the special reproduction data generation circuit 12,
A header addition circuit for adding header information such as a picture header, and additional information (quantization table information, etc.) necessary for decoding the data for quad speed reproduction, and 44 is bit stream data output from the header addition circuit 44. A packetizing circuit that performs serial / parallel conversion to generate 8-bit data of 1 byte and collects 184 bytes of data to form the data portion of the transport packet. 45 is a transport packet output from the packetizing circuit 44. Is a transport header adding circuit for adding a transport header output from the transport header correcting circuit 42 to the data of.

FIG. 4 is a layout view of rotary heads of respective channels on a typical rotary drum used in an SD standard digital VTR, and FIGS. 4 (a) to 4 (c) are used in the SD mode. An arrangement of rotating heads 27a and 27b on a representative rotating drum 28 is shown. Below, FIG.
A system having the arrangement of the rotary head 27 shown in (a) and (b) is referred to as a 9000 rpm system. Hereinafter, the rotary head arrangement shown in FIG. 3A is 1 Ch × 2, the rotary head arrangement shown in FIG. 3B is 2 Ch × 1, and FIG.
The rotary head arrangement shown in is described as 2Ch × 2. Also, FIG.
A system having the arrangement of the rotary head 27 shown in (c) is referred to as a 4500 rpm system. In the following description, FIG.
The case of the system shown in (a) will be described.

FIG. 5 is a diagram showing a recording format in one track of a digital VTR which is an embodiment of the present invention. In the SD standard, as described in the conventional example, as shown in FIG. 5 (or FIG. 25), 149 sync blocks are prepared as an area for recording video data per track. Among them, 3 sync blocks are provided as a VAUX data recording area, and 11 sync blocks are provided as an error correction code recording area (C2 check code). Also,
As in the conventional example, one sync block is composed of 90 bytes as shown in FIG. 26. Of these, the first 5 bytes have the sync pattern and the ID signal recorded, and the last 8 bytes have an error. A correction code (C1 detection code) is recorded. Therefore, the data that can be stored in one sync block is 77 bytes.

FIG. 6 is a diagram showing a data packet which is an embodiment of the present invention. FIG. 6A is a transport packet diagram included in an input bitstream (or data), and FIG. 6B is a magnetic packet. The record data packet figure recorded on a tape is shown. The bit stream input from the input terminal 1 includes a digital video signal, a digital audio signal, and digital data related to the video signal and the audio signal, which are converted into transport packets shown in FIG. It is separated and transmitted. The packet consists of a 4-byte header part and 18
It consists of a 4-byte data section.

In the first embodiment, the bit stream is detected in transport packet units, and the two detected transport packets are converted into recording data blocks of 5 sync blocks and recorded as shown in FIG. 6B. . In the figure, H1 is the first header and H2 is the second header. Identification data and the like indicating which sync of 5 sync blocks (the data area in one sync block is composed of 77-byte data as shown in FIG. 26) are recorded in H1. Identification data such as video data or audio data is recorded in H2. In addition,
The sync byte added to the beginning of each transport header does not have to be recorded. In the first embodiment, the description will be continued assuming that all the data in the transport packet is recorded.

FIG. 7 is a diagram showing the number of sync blocks that can be reproduced from one track at each high reproduction speed. It should be noted that each value in the figure is a sync that can be reproduced from one track at each reproduction speed when special reproduction is performed using a rotary head having a diameter of 10 μm (the track pitch in the SD standard is 10 μm). This shows the number of blocks. The calculation is performed assuming that the number of sync blocks in one track (corresponding to 180 degrees) is 186 sync blocks, and that a portion where the output level of the reproduction signal is higher than -6 dB can be obtained as in the conventional example.

FIG. 8 is a diagram showing a track pattern of 4 track periods including the arrangement of the special reproduction data recording area according to the first embodiment of the present invention. As shown in FIG.
Then, the special reproduction data recording area and the error correction check code recording area on each track are repeated every four tracks. Hereinafter, these four tracks will be referred to as a track format. In FIG. 9, 4 shown in FIG.
The arrangement of the data of the track cycle (data of one track format) on the magnetic tape is shown.

The recording format of the first embodiment will be described below with reference to FIGS. In the following description, the track recorded by the rotary head 27a is A track, and the track recorded by the rotary head 27b is B track. In FIG. 8, T1 is a first track recorded by the A-channel rotary head 27a, T2 is a second track recorded by the B-channel rotary head 27b, and T3 is recorded by the A-channel rotary head 27a. The third track, T4, shows the fourth track recorded by the rotary head 27b of the B channel.
In the first embodiment, as described above, data is recorded on the magnetic tape with the four tracks from the first track to the fourth track as one unit (one-track format). In the drawing, f0, f1 and f2 shown on the lower side of the tracks indicate the types of pilot signals recorded on each track as reference signals for tracking during reproduction. Note that FIG. 8 shows the video area of 135 sync blocks excluding the C2 check code recording area and the VAUX data recording area in the video area.

In FIG. 8, A0 to A4 indicate the arrangement of the 18 × speed reproduction data recording area on the magnetic tape. Each 18 × speed reproduction data recording area (A0 to A4) has a width of 5 sync blocks. As shown in the figure, the 18x speed reproduction data recording area is provided with five areas on each A track (T1 and T3). The same data is recorded in the areas marked with the same reference numerals in the figure.

Similarly, in the figure, B0 indicates the arrangement of the data recording area for quadruple speed reproduction on the magnetic tape. The data recording area for quadruple speed reproduction has a width of 25 sync blocks. Further, as shown in the figure, one data recording area for quadruple speed reproduction is provided on the T2 track.

Similarly, D0 to D5 in the figure show the arrangement of the error correction check code recording area on the magnetic tape. Each error correction check code recording area (D0 to D5) has a width of 5 sync blocks. The D1 recording area is provided adjacent to the 4 × speed data recording area. The area D4 is provided at the same height as the recording area D1.

The number of sync blocks assigned to each data recording area was determined based on the data shown in FIG. That is, as shown in FIG. 7, in the 9000 rpm system, 62 sync blocks can be obtained from one track during quad speed reproduction. Also, at the time of 18 × speed reproduction, 10.9 sync blocks can be obtained from one track.
The data arrangement on the magnetic tape corresponding to each special reproduction speed constructed based on this is shown in FIG.

The input transport packet is recorded in the special reproduction recording area (A0-A0) in the video area.
A4, B0), error correction check code recording area (D0 to D
5), C2 check code, and recorded in areas other than the VAUX recording area. (Hereafter, this area will be referred to as the main area.)

Next, a method of recording an error correction code, which is one of the cores of the present invention, will be described. As described in the conventional example, the ATV signal is compressed using a compression method based on motion compensation prediction. Therefore, when an error occurs in the reproduced data during normal reproduction, the above-mentioned error propagates to a plurality of fields or frames in the ATV signal, which is visually unsightly. Further, when the SD standard digital VTR is used as a storage medium for storing data of a computer or the like, a program, etc., it may be scratched on the tape or may be dropped out due to dust adhering to the magnetic tape. For the data that was not reproduced,
There is also a problem that it is desired to add a stronger error correction code to restore it.

Further, as described in the conventional example during high-speed reproduction, since only the error correction by the C1 check code is applied to the reproduced data, there is a problem that the frequency of error occurrence is high and the reproduced image during special reproduction is visually unsightly. .

On the other hand, the amount of additional data that can be recorded on the magnetic tape is limited as described in the conventional example. Therefore, in the first embodiment, in order to effectively utilize the limited data area, the area to which the error correction check code is added is arranged on the locus scanned by the rotary heads 27a and 27b during the special reproduction, and the normal reproduction by the user is performed. When the image quality at the time is emphasized, data is generated so that the error correction check code is added to the normal reproduction data, and when the reproduction image quality at the time of special reproduction is emphasized, the error correction check code is added to the special reproduction data. Error correction check code is generated.

As a result, the data can be effectively utilized in the limited data recording area, and the error correction check code can be added to the desired data. When the digital VTR is used as a storage medium such as a computer, it is possible to construct a strong error correction code with the same recording format. (The error correction check code for normal reproduction is written in the error correction check code recording area.)

Considering the above, the data to be recorded in the error correction check code recording area will be described below. FIG.
As shown in FIG. 6, the error correction check code recording area is provided with 6 areas (5 sync blocks each) in one track format. In the case of the mode for recording the error correction check code (hereinafter, referred to as C4 check code) for the normal reproduction data, the C4 check code is recorded in the above-mentioned six areas.

On the other hand, in the mode for recording an error correction check code (hereinafter referred to as a C5 check code) in the special reproduction data, the C5 check code for the 18x speed data is recorded in the D0 and D3 areas. Then, the C5 check code for the 4 × speed data is recorded in the D1 area. At that time, predetermined fixed value data (for example, data in which all the data are 0 is recorded in the D2, D4, and D5 areas. If the predetermined data is the fixed value data. It is not necessary.) Is recorded.
Thus, when the magnetic tape on which the error correction code for special reproduction is recorded is normally reproduced, the area (D
Since the data recorded in D2, D4, and D5) are fixed values, the error correction capability of the C2 code at the time of error correction decoding during normal reproduction can be slightly improved.
(At the time of C2 decoding, since a predetermined fixed value is recorded for the above-mentioned symbol, it is possible to eliminate the error and improve the error correction capability.)

The method of constructing the C4 check code and the C5 check code will be described later. The switching of the error correction check code recorded in the error correction check code recording area is performed based on the error correction check code recording mode signal output from the error correction code control circuit 21.

In addition, a data recording area (B
0) can be reproduced from one track by one scan of the rotary head 27b during 4 × speed reproduction. Also, 1
In the 8 × speed areas A0 to A4 and the error correction check code recording area D0 (or D3), 6 areas can be reproduced from 6 tracks by one scan of the rotary head 27a during 18 × speed reproduction. (Details will be explained in the operation of the playback system.)

If the error correction check code recorded in the error correction check code recording area is a C5 check code, error correction is performed on the special reproduction data by using these error correction check codes during special reproduction. Is given. On the other hand, C4
If it is a check code, it is ignored during special playback. Also,
At the time of normal reproduction, when the error correction check code recorded in the above area is the C4 check code, the reproduced digital data is subjected to error correction using these error correction check codes. On the other hand, in the case of the C5 check code, these data are ignored during normal reproduction. The details of the method of configuring the error correction check code during normal reproduction and special reproduction will be described later.

Details will be described in the reproduction system, but FIG.
According to the data arrangement (recording format) of the 1-track format shown in (1), the rotary heads 27a and 27b scan the ITI area and the subcode area on the magnetic tape during the 4x speed reproduction and the 16x speed reproduction. .
That is, the pilot signal f in the ITI area during special reproduction
Tracking can be controlled by using 0, f1, and f2, and additional information such as time information and music number information recorded in the sub code area can be reproduced.

Data is recorded on the magnetic tape by repeatedly recording the one-track format shown in FIG. FIG. 9 is a diagram showing a recording format on the magnetic tape. In the figure, 4 × speed reproduction data (recorded in the B0 area) is repeatedly recorded twice (see FIG. 9),
The 18 × speed reproduction data is repeatedly recorded 9 times. That is, the 18x speed data has a 1-track format (4
Since the same data is recorded on two tracks in one track, the same data is repeatedly recorded 18 times as a whole. (The data for special reproduction at 18x speed changes in a cycle of 36 tracks.) Further, the same data for 4x speed is repeatedly recorded twice.
(The data for quadruple speed trick play changes at the cycle of 8 tracks.) In FIG. 9, the data of the same signal is recorded in the areas marked with the same symbols.

Further, FIG. 9 shows the data arrangement when special reproduction data is recorded in the error correction check code recording area. For 18x speed reproduction data, a1, a
2, a3, a4, and a5 (a6, a7, a8, a
9 and a10) are used to generate the C5 check code.
The generated C5 check code is recorded in the d18,1 (d18,2) area. That is, a1, a2, a3, a4, a
5 and d18,1 data constitutes one error correction block for 18 × speed reproduction. Similarly, a6, a7, a
8, a9, a10, and d18, 2 constitute one error correction block of 18 × speed reproduction data.

For the 4 × speed reproduction data, the data of the 4 × speed reproduction data recording area and the data of the error correction check code recording area provided adjacent to the 4 × speed reproduction data recording area are used for the 4 × speed reproduction. Construct one error correction block of data. Specifically, b1, and d4
1 or b2 and d4,2 or b5 and d4,5 are used to form one error correction block of quadruple speed reproduction data. In the figure, the area marked d0,0 is a mode for recording the error correction check code for special reproduction, so that the fixed data is recorded as described above. In the case of the mode for recording the error correction check code for normal reproduction, the error correction check code recording area (D0 to D5)
A C4 check code is recorded in.

Next, the code structure of the error correction code used in normal reproduction and special reproduction will be described with reference to FIGS. First, the code structure of the error correction check code (C4 check code) for normal reproduction will be described. In the first embodiment, data of 10 tracks is collected and the collected data is interleaved to generate a C4 check code. C4
A (245, 230, 16) Reed-Solomon code is used as the check code. An embodiment of interleaving of 10 tracks will be described below with reference to FIGS. 10 and 11.

FIG. 10 is a diagram for explaining a method of constructing a data block when constructing an error correction check code to be added to normal reproduction data according to an embodiment of the present invention. Further, FIG. 10B shows a specific arrangement of the ATV data, the trick play data, and the error correction check code (C4 check code or C5 check code) on the A track and the B track. A and B shown in the figure indicate data of A track and B track, respectively. In the first embodiment, in order to perform interleaving of 10 tracks, first, two adjacent tracks (T1,
It shall consist of a T2 track or a pair of T3 and T4 tracks. ) Is used to construct a data block of 245 sync blocks. (See Figure (g))

The method of constructing the data block of the 245 sync block will be described below. When constructing the data of the 245 sync block, the 18 × speed reproduction data recorded in the A track is excluded. This is because the error correction check code adopted in the SD standard is composed of elements on the Galois field defined by GF (2 ⁸ ). Therefore, the maximum code length of the Reed-Solomon code defined under the Galois field is 255. If all the data of two tracks is used, the code length becomes 270 and it becomes impossible to construct an error correction code. Therefore, in the first embodiment, the data block for normal reproduction is formed by excluding the 18 × speed reproduction data different from the normal reproduction data. Since the data for quadruple speed reproduction is recorded only on the T2 track as shown in FIG. 8, the error correction code for normal reproduction is added this time. This is because the circuit scale at the time of identifying T2 and T4 and forming a data block becomes large, so in the first embodiment, the circuit scale is reduced by treating the quadruple speed reproduction data in the same manner as the normal reproduction data. There is. When the data for quadruple speed reproduction is excluded, two data blocks must be formed by using the data of four tracks when forming the data block described later, and the control becomes complicated and the circuit scale increases. To do.

In the SD standard digital VTR, when the frame frequency is 60 Hz, one frame of digital video signal is recorded on 10 tracks. At that time, 1 above
Track numbers are sequentially added to the ID signal from the beginning of the 10 tracks for recording frame data. Specifically, since the same number is added to the pair of the A track and the B track, track numbers 0 to 4 are added. As is well known in the United States, since the frame frequency is 30 Hz, the track number is added in the above-described manner in the SD standard digital VTR. Therefore,
In the first embodiment, the interleaving is performed in units of 10 tracks, whereby the C4 check code can be added to the data without newly adding additional information. Example 1
Then, I will omit the explanation, but PAL / SECA in Europe etc.
In the M area, since the frame frequency is 25 Hz, one frame of data is recorded on 12 tracks, and track numbers 0 to 5 are added. Therefore, it goes without saying that interleaving may be performed in units of 12 tracks.

Further, when the element on the Galois field of the error correction check code is changed to, for example, GF (2 ⁹ ), the primitive polynomial for generating the error correction code, the bit width of one symbol, etc. are changed. Not only can it not be shared with an SD standard compliant error correction code circuit (for example, a multiplication circuit on a Galois field, a division circuit, etc.), but also the bit width of one symbol increases, so the circuit scale becomes very large. Therefore, in the first embodiment, the C4 check code (24
5, 230, 16) Reed-Solomon code is used. Therefore, the error correction code for normal reproduction is excluded from the 18 × speed reproduction data that is not used during normal reproduction when the error correction code is generated, and a data block of 245 sync blocks is formed. Data for quad speed playback is not used during normal playback, but this area is T2.
It exists only in the track, and when this area is excluded, it is necessary to configure the above two blocks with 4 tracks, and the track period when generating the C4 check code is 20 tracks, which increases the circuit scale In the first embodiment, the quadruple speed reproduction data is used when generating the error correction check code for normal reproduction. In the first embodiment, the interleave depth is 10 tracks.

Considering the above, the method of constructing the error correction code of the first embodiment will be described. First, a method of forming a data block of a 245 sync block will be described with reference to FIG. In FIG. 10A, first, as described above, the 18 × speed reproduction data areas [13] to [17].
Is excluded. In addition, the error correction check encoder recording area [1
0] is also excluded from the data area when the C4 check code is generated. FIG. 10C shows the extracted normal reproduction data of the A track. Similarly, FIG. 9B shows the arrangement of ATV data, special reproduction data, and error correction check code data on the B track. Area [8]
Regarding, regarding the T2 track, it is the recording area of the quadruple speed reproduction data, but on the T4 track, it is the recording area of the normal reproduction data.

In the first embodiment, when the data block of the 245 sync block is generated, the data group formed by using the area [7] and the area [9] excluding the area [8] (see FIG. )), And a data group (see (e) in the same figure) composed of the data of the area [8]. Further, the error correction check code recording areas [10] and [1] recorded on the A track and the B track are recorded.
1] and [12] are collected to form a data group shown in FIG.

FIG. 10C constructed in the above manner,
As shown in the figure, the data groups shown in (d) and (e) are 21 and 20 in 5 sync blocks, respectively.
, And 5 blocks. The data divided in units of 5 sync blocks starts with the data of the B′1 block shown in FIG.
Data shown in (c) of the figure and (d) of the figure are arranged alternately in the order of A2, B2, .... And the same figure (g)
As shown in, the data of A21 is followed by B'2, B'3,
B'4 and B'5 are arranged, and error correction check code recording areas [11], [10], and [12] are arranged in that order, and a data block of 245 sync blocks is formed. In addition, the area of the same code described in the drawing indicates the same area. (For example, FIG.
The area marked [1] in (a) indicates the same area as the area marked [1] in FIG. ) Further, the horizontal numbers shown in FIG. 9G indicate the position (address) of the data in the sync block, and the numbers written in the vertical direction are the sync block addresses in the data block of the 245 sync block. Indicates.

Data blocks of 245 sync blocks constructed as described above are collected into 5 data blocks, and 10-track interleaving is applied to normal reproduction data to generate a C4 check code. The interleaving pattern applied to the data when the C4 check code to be added to the normal reproduction data is generated will be described with reference to FIG.

FIG. 11 is a diagram for explaining an interleaving method of 5 data blocks to be applied to the data when the error correction check code is added to the normal reproduction data according to the embodiment of the present invention. Here, the above-mentioned 24 shown in FIG.
The block number of the data block of 5 sync blocks is Bn (0 ≦ Bn ≦ 4), the sync block number in the data block is SBn (0 ≦ SBn ≦ 244),
If the data number in the sync block is Dn (0 ≦ Dn ≦
76) is defined by D [Bn, SBn, Dn], in one embodiment of the shuffling shown in FIG.
(D [0,0,0], D [1,1,1], D [2,
2, 2], ..., D [(i mod 5), i,
(I mod 77)], ..., D [4,229,7
5], D [0,230,76], D [1,231,
0], ..., D [4,244,13]). Here, 2 from D [0,0,0] to D [4,229,75]
30 bytes are information symbols, D [0,230,76]-
The 15 bytes up to D [4,244,13] are the C4 check code. FIG. 11 schematically shows the shuffling operation. Interleave is 245 above in the direction of the alternate long and short dash line.
Interleaving of 5 data blocks is performed on the data of the data blocks of the sync block to be executed.
(Note that, since data blocks are formed substantially as shown in FIG. 10G, data is subjected to data interleaving of about 10 tracks.) The dotted line indicates the interleaving direction within the data blocks. Indicates.
(Actually, since interleaving is performed for every 5 data blocks, 1 data is sampled for every 5 data blocks.)

This operation is performed for all the data in the sync block at the head of each track. That is, when the C4 check code is generated with the kth data starting from the sync block at the beginning of the jth track, (D [j, 0,
k], D [(j + 1 mod 5), 1, (k + 1
mod77)], ..., D [(j + i mod
5), i, (k + i mod 77)], ..., D
[(J + 229 mod 5), 229, (k + 229)
mod 77)], D [(j + 230 mod
5), 230, (k + 230 mod 77)], ...
., D [(j + 244 mod 5), 244, (k +
244 mod 77)]), and k per track
Is changed from 0 to 76, and this is changed to 5 data blocks (j
Is changed from 0 to 4. ) To perform interleaving to generate a C4 check code. Note that FIG.
The middle or (X mod Y) in the above formula represents the remainder when the integer X is divided by the integer Y. The data for which the C4 check code is generated by the above interleaving is
It is recorded in a predetermined area shown in FIGS. 10 (a) and 10 (b). When the error check code addition mode is the special reproduction error correction code recording mode, the C5 check code is recorded in the error correction check code recording area and the C4 check code is discarded.

Next, the burst error correction capability of the C4 check code will be briefly described. 2 shown in FIG.
As shown in FIG. 11, data interleaving with a depth of 5 data blocks is applied to the data blocks of 45 sync blocks. Since the C4 check code has a minimum distance of 16, it is possible to correct errors up to 15 erasures. As described above, since the data block shown in FIG. 10G is interleaved with a depth of 5, the maximum burst error correction capability is 15 × 5 = 75 sync blocks. Therefore, in the case of the A track, since the C4 check code is not added to the 18x speed reproduction data area, the maximum burst error correction capability is 75 + 20 (= 95) sync blocks. Similarly, with respect to B track data, it is possible to correct burst errors of up to 75 sync blocks. Since the data for quadruple speed reproduction is repeatedly recorded twice on the T2 track, the maximum burst error can be obtained by exchanging the same quadruple speed data recorded on different tracks with the data in the above area when a burst error occurs. Correction ability is 75 + 25
(= 100) It becomes a sync block. Therefore, even if the data of 75 sync blocks in one track is not reproduced due to dropout during normal reproduction, C4
Data can be restored by the check code.

Next, the structure of the error correction code added to the trick play data will be described with reference to FIG. FIG. 12 is a diagram showing the structure of an error correction check code (C5 check code) added to special reproduction data. (Hereinafter, the data structure shown in FIG. 12 will be referred to as an error correction block.) The C5 check code uses the Reed-Solomon code of (30, 25, 6). FIG. 10A shows the arrangement of the 18 × speed reproduction data to be recorded on the A track and the error correction check code. The data of the error correction block shown in FIG. 12 is divided into 5 sync blocks for the 18 × speed reproduction data, and each area [13] to [13] shown in FIG.
It is recorded in the area shown in [17]. The C5 check code is recorded in area [10].

Similarly, the 4 × speed reproduction data recorded on the B track is recorded in the special reproduction area (area [8]) in units of 25 sync blocks. On the other hand, the C5 check code is stored in the error correction check code recording area of the area [11] provided adjacent to the area [8].

In the first embodiment, as described above, the data is interleaved with a depth of 10 tracks to generate a C4 check code. At that time, the first memory 13 and the second memory 1
6 and the third memory 17 convert the transport packet (FIG. 6A) input through the input terminal 1 into sync block unit data shown in FIG. 6B. Then, the ATV signal output from the first memory 13 converted into sync block units and the special reproduction data output from the first error correction coding circuit 18 are used by the data synthesizing circuit 19 in FIG. The block data of the 245 sync block shown in is generated. The C added to the 18 × speed reproduction data output from the first error correction coding circuit 18 and the special reproduction data of each double speed number.
The 5 check code is temporarily stored at a predetermined address in the memory in the data synthesizing circuit 19.

The above 24 constructed by the data synthesizing circuit 19
The data block of the 5 sync blocks is the fourth memory 22.
Is stored at a predetermined address in At this time, the 18x speed reproduction data stored in the memory in the data combination circuit 19 and the C5 check code added to the special reproduction data of each speed number are also generated at the same timing as the data block. It is read out from 19 and stored in a predetermined address in the fourth memory 22. The detailed circuit operation of the recording system will be described later.

Next, the operation of the recording system will be described with reference to FIGS. The transport packet input from the input terminal 1 is input to the first memory 13 and the header analysis circuit 10. First, the header analysis circuit 10 detects a transport header from the input transport packet and separates the transport packet for transmitting video data. Then, the data in the transport packet that has transmitted the separated video data is analyzed to detect header information such as a sequence header, a picture header, and a slice header, and an intra image is separated from the transport packet. The various header information and additional information added to the header information are also separated.

The sequence header is header information provided in the bit stream of the video signal and is MPE.
Identification information of G1 and MPEG2 and the like are added. The picture header is a header added to the beginning of each frame or field to indicate the beginning of each frame or field, and a mode signal such as an encoding mode is added. Also, MP
In the EG2, when transmitting one frame of data, the screen of one frame (field) is divided into a plurality of slice blocks for transmission. The slice header points to the beginning. (For details about each header, refer to the draft of MPEG2)

The header information detected by the header analysis circuit 10 and the additional information (for example, quantization table information) accompanying it and the intra image information are P
It is output to the / S conversion circuit 11, the 4x speed data generation circuit 14, and the 18x speed data generation circuit 15.

The P / S conversion circuit 11 performs P / S conversion on the input transport packet data to convert it into 1-bit bit stream data. The intraframe transport packet data converted into 1-bit serial data is input to the special reproduction data generation circuit 12. The operation of the special reproduction data generation circuit 12 will be described with reference to FIG. In image compression by MPEG2, a block of 8 lines × 8 pixels (hereinafter referred to as DCT block) is subjected to discrete cosine transform (hereinafter referred to as DCT), and data subjected to DCT (hereinafter referred to as DCT).
Described as a coefficient. ) Is sequentially read from the low-frequency component in which the power spectrum is concentrated in a scanning order called zigzag scanning, and run-length coding (separating into run-length data and coefficient data) with a coefficient of 0 is performed, and then two-dimensional. Apply variable length coding.

The serial data of the intra image input via the input terminal 30 is input to the variable length decoder 4, the data extracting circuit 6a and the data extracting circuit 6b. The variable length decoder 4 performs variable length decoding on the input bit stream. In the first embodiment, the input bit stream is not completely decoded at the time of variable length decoding, but
The circuit size is reduced by detecting and outputting only the run length length of the variable length codeword and the code length of the variable length codeword. (It goes without saying that variable length decoding may be performed completely.) The counter 5 counts the number of DCT coefficients in one DCT block decoded based on the run length length, and the data sampling circuit 6
The count result is output to a and the data sampling circuit 6b.

The data extracting circuit 6a extracts the variable length code word of the quadruple speed reproduction data to be transmitted based on the count result output from the counter 5. The data sampling timing is controlled so that the number of decoded DCT coefficients output from the counter 5 is compared with a predetermined value and the variable length codeword before the predetermined value is transmitted. The break of the variable length code word is detected by the code length information output from the variable length decoder 4. Similarly, the data extracting circuit 6b extracts the variable length code word of the 18 × speed reproduction data independently at preset timings (thresholds) based on the information output from the counter 5 and the variable length decoder 4. . The data respectively extracted are the EOB adding circuit 7a and the EOB adding circuit 7b.
Then, an EOB code is added to the end of each DCT block and output from the output terminals 31a and 31b, respectively. The head of each DCT block is detected by the variable length decoder 4 and output to the counter 5 and the data sampling circuits 6a and 6b.

At this time, the number of DCT coefficients for extracting data may be the same or different in each data extracting circuit. The fact that the number of extracted DCT coefficients is different means that the number of DCT blocks recorded in the recorded special reproduction transport packet is different. The area in which special reproduction data can be recorded is limited as described above.
Therefore, if the trick play data recording area has the same number of sync blocks for each trick play speed, 1 DCT
If the number of DCT coefficients recorded in a block is increased, a special reproduction data recording area for recording is required, and the update cycle (hereinafter referred to as refresh) of high-speed reproduction image data during high-speed reproduction becomes long. The reproduction image quality is improved because more DCT coefficients are transmitted. On the contrary, if the number of recorded DCT coefficients in one DCT block is reduced, the data amount of the special reproduction data per frame is reduced, and the special reproduction data recording area is reduced, so that the refresh of the high-speed reproduction image is shortened. The reproduced image quality is poor because the number of recorded DCT coefficients is small. The amount of data to be extracted at each double speed may be determined by the trade-off between refresh and image quality.

The 4 × speed reproduction data and the 18 × speed reproduction data output from the special reproduction data generation circuit 12 are input to the 4 × speed data generation circuit 14 and the 18 × speed data generation circuit 15, respectively. Since the subsequent processing is the same at each reproduction speed (4 × speed and 18 × speed), a method of generating 4 × speed reproduction data will be described here. Hereinafter, with reference to FIG. 3, the 4 × speed data generation circuit 1 will be described.
The operation of No. 4 will be described. In the 4x speed data generation circuit 14, the transport header information and various header information (including additional information) input from the header analysis circuit 10 and the 4x speed reproduction output from the special reproduction data generation circuit 12 are output. A transport packet for quad speed reproduction is generated using the data. The transport header information input via the input terminal 40 is modified by the transport header modification circuit 42. Specifically, based on the intra information output from the header analysis circuit 10, the header information indicating the continuity of the transport packet in the transport header of the transport packet transmitting the intra image is rewritten. On the other hand, in the header addition circuit 43, the trick play bit stream output from the trick play data generation circuit 12 includes header information such as a sequence header, a picture header, and a slice header detected by the header analysis circuit 10, and each header. Information necessary for decoding the special reproduction data is added from the above. (Encoding mode flag, quantization table information, etc.)

The special reproduction data to which the header information is added is subjected to serial / parallel conversion in the packetizing circuit 44 and 1 byte is converted into 8-bit data. The serial / parallel converted 8-bit data is 184
The data portion of the transport packet is composed by dividing it into bytes. It should be noted that when serial / parallel conversion, each header information is set to 4 as specified in MPEG2.
"0" data is inserted before each header information so as to be composed of bytes. (Each header information is composed of 32 bits and needs to be composed of 4 bytes when a transport packet is generated.) Specifically, when the header information spans 5 bytes, the header information The header information is controlled to be composed of 4 bytes by adding "0" information to the front. The data of the 184-byte transport packet formed by the packetization circuit 44 is output with the transport header information output from the transport header correction circuit 42 added by the transport header addition circuit 45. The reading of the header information from the transport header correction circuit 42 is output based on the timing signal output from the packetization circuit 44. The 4 × speed reproduction data generated by the 4 × speed data generation circuit 14 is output to the second memory 16 in the form of transport packets.

Although the transport packetization of the 4 × speed reproduction data has been described above, the same processing is performed on the 18 × speed reproduction data. The 18 × speed reproduction data output from the special reproduction data generation circuit 12 is input to the 18 × speed data generation circuit 15. In the 18-fold data generation circuit 15, after the header addition circuit 43 adds each header and additional information based on the header information output from the header analysis circuit 10, the packetization circuit 44 performs serial / parallel processing as described above. After the conversion, the data portion of the transport packet is configured, and the transport header adding circuit 45 transports the transport header modifying circuit 4
The modified transport header output from the data No. 2 is added and output to the third memory 17 in the form of a transport packet.

Now, the operation of the error correction code control circuit 21 will be described. In the error correction code control circuit 21, the error correction check code recording mode is set according to the command information input through the input terminal 21 (either the special reproduction error correction code recording mode or the normal reproduction error correction code recording mode).
First error correction code circuit 18, data combination circuit 19, second error correction code circuit 23, third error correction code circuit 2
4 and the digital modulation circuit 25, and also outputs a track identification signal of a 4-track cycle and a track identification signal of 10 tracks based on the servo information output from the tape running control and drum rotation control system. . In the first embodiment, switching of the error correction code is performed by the output of the fourth memory 22.

4 × speed data generation circuits 14 and 18
Each special reproduction transport packet data output from the double data generation circuit 15 is stored in the second memory 1
6, and is temporarily stored in the third memory 17. Second,
In the third memories 16 and 17, the input data is stored in the memory in the form of transport packets to form one frame (field) of special reproduction data. One frame of special reproduction data composed of the second memory 16 and the third memory 17 is read from each memory in units of two transport packets, and as shown in FIG. The data is converted into block data and output to the first error correction coding circuit 18.
The reading of data from the second and third memories 16 and 17 is performed based on the control signal output from the first error correction code circuit 18. Further, the H1 and H2 header information is assumed to be added when the first error correction coding circuit 18 is input.

In the first error correction coding circuit 18, FIG.
As shown in (b), the special correction data corresponding to each double speed number converted in sync block units are collected into 25 sync blocks to form an error correction block for adding a C5 check code. Then, data for 4 × speed reproduction, and 18
A C5 check code is generated and added to the double speed reproduction data. The data for the 4 × speed reproduction and the 18 × speed reproduction data to which the C5 check code is added are the data synthesizing circuit 1
9 is input. The C5 check code added to the special reproduction data is generated based on the control signal (data request signal) output from the data synthesizing circuit 19.

On the other hand, the AT input through the input terminal 1
The transport packet of the V signal is input and stored in the first memory 13. The first memory 13 reads the input data based on the control signal output from the data synthesizing circuit 19. At this time, the data input in transport packet units is converted into data of 5 sync blocks as shown in FIG. 6B in units of 2 transport packets, and is output.

In the data synthesizing circuit 19, based on the track identification signals of 4 tracks and 10 tracks output from the error correction code control circuit 21, FIG.
A data block of the 245 sync block shown in FIG. At this time, the number of times the special reproduction data is repeated is counted by an internal counter, and the first error correction code circuit 18
Output a data request signal for trick play data to. In the data synthesizing circuit 19, first, the normal reproduction data for two tracks is read from the first memory 13. First
The data read from the memory 13 is stored in the memory provided in the data synthesizing circuit 19. Similarly,
The special reproduction data output from the first error correction code circuit 18 and the C5 check code are also stored in a predetermined memory provided in the data synthesis circuit 19. The data read order of the data stored in the data synthesizing circuit 19 is changed, and a data block of 245 sync blocks shown in FIG. It should be noted that switching between the 4 × speed reproduction data and the normal reproduction data on the B track is processed in the data synthesizing circuit 19 using the track information of the 4 track cycle. The 18 × speed reproduction data and the C5 check code for each trick reproduction data are output from the data block of the 245 sync block to the fourth memory 22 by the fourth data synthesizing circuit 19.

The above data output from the data synthesizing circuit 19 is written into a predetermined address of the fourth memory 22. The write address to the fourth memory 22 and the control signal are output from the second error correction code circuit 23.

Next, the operation of generating the C4 check code will be described. When the block construction for 5 data blocks is completed in the fourth memory 22, the second error correction coding circuit 2
In 3, the read address of data for generating the C4 check code and the control signal are output to the fourth memory 22. The fourth memory 22 reads data based on the input control signal. (It is assumed that the read data is interleaved as shown in FIG. 11. That is, the read address output from the second error correction coding circuit 23 is previously interleaved. Second error correction coding circuit 2
In 3, the C4 check code is generated based on the data read from the fourth memory 22. Second error correction coding circuit 2
The C4 check code generated in 3 is stored in the C4 code storage area provided in advance in the fourth memory 22.
When the generation of the C4 check code for the five data blocks is completed, the data stored in the fourth memory 22 is output to the third error correction code circuit 24.

The reading of the data from the fourth memory 22 is performed based on the reading address of the data output from the third error correction code circuit 24 and the control signal.
In the third error correction code circuit 24, based on the mode signal output from the error correction code control circuit 21 and the track identification signal, the data stored in the fourth memory 22 is stored in FIG. Alternatively, the data is rearranged and read in the order of the sync block of (b). At that time, C4
The check code and the C5 check code are also selected based on the mode signal output from the error correction code control circuit 21. ) Is executed. In the first embodiment, C5 is used in the error correction code recording mode for special reproduction.
When the check code is read from the fourth memory 22, the fixed data is recorded in D2, D4, and D5 in FIG. 8 as described above. It is assumed that fixed value data is stored.

The data read from the fourth memory 22 is stored in the memory in the third error correction coding circuit 24 in track units. When one track of data is formed, the SD shown in FIG. 25 is used in the third error correction coding circuit 24.
An error correction code based on the standard is added to the above data. That is, the above-mentioned data recorded in the video area is first generated and added with the C2 check code for each track unit. For the data to which the C2 check code is added, a C1 check code is generated and added in sync block units. Further, the C3 check code and the C1 check code are also added to the audio area. In the first embodiment, the audio data area is opened for future expansion, and in the first embodiment, fixed-value dummy data is recorded. The data to which the error correction code based on the SD standard is added is read from the third error correction code circuit 24 at a predetermined timing for each track unit. At that time, a track format based on the SD standard is generated. Specifically, an interval of 5 bytes is provided to add a sync signal and an ID signal between each sync block, and a predetermined amount of an ITI area, a subcode area, and a gap between data are provided. The above data is output. The output of the third error correction code circuit 24 is input to the digital modulation circuit 25.

In the digital modulation circuit 25, first, a sync signal and an ID signal are added to the head of each sync block. At that time, regarding the sync block recorded in the error correction code recording area, flag information for identifying the type of the error correction code is added to the ID signal. At the time of reproduction, the type of the error correction code is identified by the flag in the ID signal, and the error of each data is corrected. The data to which the ID signal is added is digitally modulated, amplified by the recording amplifier 26, and rotated by the rotary heads 27a and 2
It is recorded on the magnetic tape via 7b.

Next, the structure of the reproducing system of the digital VTR for reproducing the magnetic tape having the above recording format will be described. FIG. 13 is a block diagram of a reproducing system of a digital VTR which is an embodiment of the present invention. It is to be noted that the components designated by the same reference numerals as those in FIG. In the figure, 50 is a reproduction amplifier, 51 is a digital demodulation circuit, and 52 is a first error correction decoding circuit for correcting and detecting an error in a reproduction signal by using a C1 check code and a C2 check code for a reproduction digital signal. Is. The ID signal in the reproduced signal is detected and output to the error correction decoding control circuit 54.

Reference numeral 53 is an input terminal for a mode signal (normal reproduction or special reproduction) indicating the current reproduction state, 54 is an ID signal output from the first error correction decoding circuit 52, and the reproduction mode signal based on the reproduction signal. The control signal for switching the error correction decoding process during special reproduction or normal reproduction is output to the second error correction decoding circuit 56 and the third error correction decoding circuit 57, and the switching signal of the switch 59 is also output. Error correction decoding control circuit. The error correction decoding control circuit 54 also detects information such as track number information, sync block address information, and the type of error correction check code recorded in the error correction check code recording area from the ID signal. 55 is a fifth memory for storing normal reproduction data, and 56 is a control signal output from the error correction decoding control circuit 54 (a discrimination result of the ID information detected by the first error correction decoding circuit 52, and a reproduction mode). In the case where a C4 check code is recorded in the error correction check code recording area based on the signal), the data stored in the fifth memory 55 is subjected to error correction decoding by the C4 check code and is reproduced normally. A second error correction decoding circuit for correcting or detecting an error occurring in the working signal, 57 is a C in the error correction check code recording area based on the control signal output from the error correction decoding control circuit 54.
When 5 check codes are recorded, a third error correction decoding circuit for performing error correction decoding using the C5 check code to correct and detect an error generated in the special reproduction data, and 58 is a third error correction decoding circuit. A sixth memory for storing special reproduction data output from the error correction decoding circuit 57, 59 is a switch, and 60 is an output terminal.

Before explaining the operation of the reproducing system, FIG.
4 and FIG. 15, the operation in the case of performing the 4 × speed reproduction and the 18 × speed reproduction by the digital VTR shown in the first embodiment will be described. FIG. 14 is a diagram showing the relationship between the scanning locus of the rotary head and the track pattern when the magnetic tape having the recording format shown in FIG. 9 is reproduced at 4 × speed with the drum structure of 1 Ch × 2. In the figure, the scanning trace marked A is
The scanning locus | trajectory of the rotary head 27a of A channel is shown. Similarly, the scanning locus denoted by B indicates the scanning locus of the rotary head 27b of the B channel. As described above, the 4 × speed reproduction data is recorded on the track of the B channel, and as described above, the same data is repeatedly recorded during the 2-track format period (the same data is recorded in two recording areas. Therefore, as shown in FIG. 14, the recording area for the data for quadruple speed reproduction is recorded on the A-channel rotary head 27a and the B-channel rotary head 27 during the two scanning periods of the rotary heads 27a and 27b.
Since b is scanned once, it is possible to reproduce the 4 × speed reproduction data recorded by the rotary head 27b of the B channel. At this time, the rotary heads 27a and 27b can also reproduce the data in the sub code area as shown in FIG. Also, tracking can be applied in the ITI area. 2Ch x 1
Although the description of the case where the 4 × speed reproduction is performed by the digital VTR having the drum structure of No. 1 is omitted, the rotary head 27a simultaneously scans the left side of the rotary head 27b of 1 Ch × 2.
(In FIG. 14, the scanning locus of the rotary head 27a scans the left side of the rotary head 27b adjacently.) Therefore, it is possible to reproduce the special reproduction data for 4 × speed recorded by the rotary head 27b of the B channel. it can.

FIG. 15 is a diagram showing the relationship between the scanning locus of the rotary head and the track pattern when the magnetic tape having the recording format shown in FIG. 9 is reproduced at 18 × speed with the drum structure of 1 Ch × 2. In the figure, the scanning trace marked A is
The scanning locus | trajectory of the rotary head 27a of A channel is shown. Similarly, the scanning locus denoted by B indicates the scanning locus of the rotary head 27b of the B channel. Since the 18 × speed reproduction data is recorded in the A channel track repeatedly in a 9-track format (the same data is recorded at 18 locations in total), it is recorded by the A channel rotary head 27a as described in the conventional example. The 18x speed reproduction data thus generated can be reproduced. (As shown in FIG.
The 18 × speed reproduction data can be reproduced by the rotary head 27a of the channel. ) Also at this time, the rotary head 2
The signal 7a can also reproduce the signal in the sub code area. At this time, since it also passes through the ITI area, tracking can be performed by the pilot signal recorded in the ITI area. A digital VTR having a drum structure of 2 Ch × 1 as in the case of the 4 × speed reproduction described above.
A description of the case of performing the 18 × speed reproduction with is omitted, but 1C
The rotary head 27b simultaneously scans the right side of the h × 2 rotary head 27a. (In FIG. 15, the scanning locus of the rotary head 27b scans the right-hand side of the rotary head 27a adjacently.) Therefore, the special reproduction data for 18x speed recorded by the rotary head 27a of the A channel can be reproduced. it can.

The amount of data that can be reproduced from one track during reproduction at 4 × speed and 18 × speed is 45 as shown in FIG.
With a 00 rpm system, the speed is 62 SB at 4 times speed and 10.9 SB at 18 times speed. It should be noted that the reproduction positions of the data on the tracks for the −2 × speed reproduction and the −16 × speed reproduction are the same as those for the 4 × speed and the 18 × speed reproduction, respectively, and thus can be realized by the recording format shown in FIG. Although detailed description is omitted, 4500 rpm
When reproducing a magnetic tape having the above-mentioned recording format in the above system, the reproduction speed during high-speed reproduction is doubled (93
SB) and 8 times speed (13 SB). Therefore, at the time of high speed reproduction of each double speed, in addition to the special reproduction data, an error correction check code recording area (4 times speed reproduction data) arranged adjacently or an error correction check code recording area (18) provided separately on the track is provided.
Double speed playback) can also be played simultaneously. Further, during normal reproduction, the rotary heads 27a and 27b reproduce all tracks. Therefore, the error correction code recording area is used for high speed reproduction (4 × speed, 18 × speed reproduction, −2 × speed,
Since it can be reproduced in both the case of normal reproduction and -16 × speed), it can be shared in the same recording area as described at the time of recording. (That is, whichever error correction code is added, the error correction check code recording area can be reproduced during high speed reproduction or normal reproduction.)

In the above description, the tracking at the time of high speed reproduction is explained in the ITI area, but the present invention is not limited to this. For example, in the case of 18 × speed reproduction, one data area of the special reproduction data recording area is used. May be used to detect and control the tracking phase, or the tracking phase may be detected and controlled in the plurality of special reproduction data recording areas. For quad speed reproduction, the rotary head 27a is moved to a predetermined position on the adjacent A track.
The tracking phase may be detected and controlled by. Further, the tracking phase may be roughly adjusted in the ITI area and finely adjusted in the special reproduction area. In particular, the tracking control method described above is effective when there is a bend in the track due to compatible reproduction or the like.

Next, the operation of the reproduction system during normal reproduction will be described. The data reproduced from the magnetic tape via the rotary heads 27a and 27b on the drum 28 is amplified by the reproduction amplifier 50, and the digital demodulation circuit 51
Is input to The digital demodulation circuit 51 performs data detection from the input reproduction data, converts it to reproduction digital data, and then performs digital demodulation. The reproduced digital data digitally demodulated by the digital demodulation circuit 51 is input to the first error correction decoding circuit 52. When the reproduced digital data is input, the error correction decoding circuit 52 separates the ID signal added to the head of each sync block, and the result is separated by the error correction decoding control circuit 5
Output to 4. The reproduced digital data from which the ID signal is separated is C in the first error correction decoding circuit 52.
The 1 check code and the C2 check code are used to correct and detect an error that occurred during reproduction. The reproduced digital data subjected to error correction in the first error correction decoding circuit 52 is output to the fifth memory 55 and the third error correction decoding circuit 57. At that time, the special reproduction data (4 × speed reproduction data and 18 × speed reproduction data) reproduced from the special reproduction data recording area is input to the third error correction decoding circuit 57 to convert the 18 × speed reproduction data. The reproduced digital data excluding it is input to the fifth memory 55. In the first embodiment, the error correction decoding operation using the C5 check code in the third error correction decoding circuit 57 is not performed during normal reproduction. (That is, the trick play data is only input to the third error correction decoding circuit 57, and no error correction decoding operation is performed.)

On the other hand, the ID signal detected by the first error correction decoding circuit 52 is input to the error correction decoding control circuit 54. The error correction decoding control circuit 54 detects the ID signal separated from the sync block recorded in the error correction check code recording area, and identifies the type of error correction check code using the added identification flag data. In addition, during normal playback, the track number currently being played,
It also detects the sync block number. Also, according to the reproduction mode signal input through the input terminal 53,
Detect the current playback mode. Then, the identification result of the error correction check code, the track number, the sync block number, and the reproduction mode information are output to the second error correction decoding circuit 56 and the third error correction decoding circuit 57, and the reproduction mode signal is output. Supply to the switch 59.

The reproduced digital data input to the fifth memory 55 on a track-by-track basis is the rotary head 27.
The A track and the B track are identified using the reproducing head information of a and 27b. Then, using the signal shown in FIG. 10A reproduced from the A track and the signal shown in FIG. 10B reproduced from the B track, a data block of 245 sync blocks is formed in the memory. On the other hand, in the second error correction decoding circuit 56, when the error correction code recorded in the error correction check code recording area is the error correction check code for normal reproduction (C4 check code), the error correction decoding control circuit 44 It is confirmed using the output track number information whether the error correction block by the C4 check code shown in FIG. 11 is formed in the fifth memory 55.

When the error correction block by the C4 code shown in FIG. 11 is formed in the fifth memory 55, the data is read from the fifth memory 55 as shown in FIG. 11 and the error correction by the C4 check code (hereinafter, C4 decoding) is applied to normal reproduction data and quadruple speed reproduction data. The read address of the data from the fifth memory 55 and the read control signal are output from the second error correction decoding circuit 56. Data interleaving over five data blocks is also performed at the time of reading from the fifth memory 55. (The interleave control is performed by the data read address output from the second error correction decoding circuit 56.) 1
The 8 × speed data is discarded at the input of the fifth memory 55. The data subjected to the C4 decoding is supplied to the output terminal 60 via the switch 59.

On the other hand, when the error correction code recorded in the error correction check code recording area is the error correction check code for special reproduction, the reproduced digital data is read out from the fifth memory 55 without any processing. It is output to the switch 59. When the reproduced digital data is read from the fifth memory 55, the 4 × speed reproduction data and the data recorded in the error correction check code recording area are deleted and added to the data of 5 sync blocks. The transport packet is reconfigured based on the header information (H1 and H2 header information) and the data is output. (See FIG. 6) The switch 59 outputs a selection control signal (reproduction mode signal) from the error correction decoding control circuit 54 so as to select the output of the fifth memory 55 during normal reproduction.

Next, the operation during special reproduction will be described. Rotating heads 27a and 2 on the drum 28 from the magnetic tape
The data reproduced intermittently via 7b is the reproduction amplifier 5
It is amplified at 0 and input to the digital demodulation circuit 51. The digital demodulation circuit 51 performs data detection from the input reproduction data, converts it to reproduction digital data, and then performs digital demodulation. The reproduced digital data that has been digitally demodulated in the digital demodulation circuit 51 is input to the first error correction decoding circuit 52. When the reproduced digital data is input, the first error correction decoding circuit 52 separates the ID signal added to the head of each sync block, and the result is error correction decoding control circuit 5
Output to 4. The reproduced digital data from which the ID signal is separated is C in the first error correction decoding circuit 52.
Correction of errors that occurred during special playback using 1 check code,
And detection is performed. It should be noted that since data is intermittently reproduced during special reproduction as described in the conventional example,
5 or the error correction block as shown in FIG. 5 cannot be configured, and therefore the error correction by the C2 check code and the error correction by the C4 check code are not performed.

The reproduced digital data subjected to error correction in the first error correction decoding circuit 52 is output to the fifth memory 55 and the third error correction decoding circuit 57. At this time, the special reproduction data reproduced from the special reproduction data recording area is temporarily stored in the memory provided in the third error correction decoding circuit 57. The fifth
The reproduced digital data is not written in the memory 55 of FIG.

As in the normal reproduction, the ID signal detected by the first error correction decoding circuit 52 is input to the error correction decoding control circuit 54. The error correction decoding control circuit 54 detects the ID signal separated from the reproduced digital data recorded in the error correction code recording area, identifies the type of the error correction check code added to the ID signal, and Detects the track number being played and the sync block number. Further, the current reproduction mode is detected by the reproduction mode signal input via the input terminal 53. Then, the identification result of the error correction check code, track number, sync block number, and reproduction mode information (normal reproduction and high-speed reproduction information (4
Double speed playback, 18x speed playback, or -2x speed playback, -1
6 × speed reproduction)) is output to the second error correction decoding circuit 56 and the third error correction decoding circuit 57, and a reproduction mode signal is supplied to the switch 59.

In the third error correction decoding circuit 57, when the error correction check code recorded in the error correction check code recording area is the C4 check code, the special reproduction data reproduced without doing anything is changed to the sixth. Output to the memory 58.
On the other hand, in the case of the C5 check code, the error correction block shown in FIG. 12 is configured in the third error correction decoding circuit 57 and the special reproduction data is subjected to error correction by the C5 check code (hereinafter referred to as C5 decoding). Note.). The data subjected to C5 decoding is output to the sixth memory 58. Sixth memory 58
Is supplied to the switch 59. The switch 59 is controlled so as to select the output of the sixth memory 58 during special reproduction. When the special reproduction digital data is read from the sixth memory 58, the data recorded in the error correction check code recording area is deleted, and the header information (H
1 and H2 header information) to reconfigure the transport packet and output the data. (See FIG. 6) The switch 59 outputs a selection control signal (reproduction mode signal) from the error correction decoding control circuit 54 so as to select the output of the sixth memory 58 during special reproduction.

Since the digital VTR shown in the first embodiment is constructed as described above, the error correction code recording area provided in the recording track is recorded at a position where it can be read during normal reproduction and high speed reproduction. Therefore, the recording area of the error correction check code can be shared, and the error correction code to be generated is switched according to the application, so that the area for recording the limited additional information can be effectively used, and in the future, When the digital VTR is used as an external device such as a computer for recording data, a powerful error correction code can be added to the data in the same recording format.

Further, since the error correction check code is generated according to the purpose, when the reproduction image quality during special reproduction is emphasized, C
By recording the 5 check code in the error correction check code recording area, the error correction capability during special reproduction is improved, and when the reproduction image quality during normal reproduction is emphasized, the C4 check code is usually recorded in the above area. By improving the error correction capability of the reproduced data, it is possible to efficiently utilize the limited area on the magnetic tape. Further, when the digital VTR is used as an external storage device such as a computer in the future, a strong error correction check code can be added to the recording data in the same recording format, and it can be shared with the external storage device. Further, the digital VTR currently on hand can be used as an external storage device such as a computer. (Because the recording formats are compatible, it can be reused.) Also, since the recording area on the recording track is used efficiently as described above, the amount of data that can be allocated to special playback data increases and during special playback. The playback image quality of can be improved.

In the first embodiment, the case where the recording format is shown in FIG. 9 has been described. However, the recording format is not limited to this format, and the special reproduction data is separated from the input data and stored in a predetermined area on the recording medium. Digital signal recording device having recording format for recording, reproducing device, and recording / reproducing device (digital VT
R, digital disk player, etc.), the data area is arranged so that the special reproduction data recording area and the error correction check code recording area can be reproduced from the head of each device during special reproduction. A system having a recording format has the same effect. For example, in the first embodiment, the rotary head 2
When arranging the error correction recording area on the scanning locus of 7a (data for 18x speed reproduction) and when arranging the error correction check code recording area adjacent to the data recording area for special reproduction (data for 4x speed reproduction) ).

Further, the depth of interleaving at the time of normal reproduction is not limited to 10 tracks (5 data blocks), but the PAL area centered on Europe (the frame frequency is 25H).
In z), for example, 12 tracks (6 data blocks), NTSC range (10 tracks), and interleave depth may be changed. Also, it may be in the NTSC range, for example, 12 tracks. The interleave depth is NTSC
It goes without saying that the same may be used in the area and the PAL area. Further, the interleaving method is shown in FIG. 10 and FIG.
However, it goes without saying that the present invention is not limited to this. For example, the direction of interleaving in the track may be vertical. The data block configuration method is not limited to that shown in FIG. 10. For example, the 18 × speed data and the error correction check code recording area are removed, and the sync block number of the A track is in ascending order (for example, 135 syncs in the video area). After reading the data to the block), the data of the B track is similarly read in the ascending order of the sync block number to form a data block of 230 sync blocks, and then the area [10], the area [11], and the area in FIG. Data in the error correction check code recording area is added in the order of [12]
The data block of the sync block may be configured.

Further, it goes without saying that the recording data is not limited to the ATV signal, and the same effect can be obtained when a European DVB signal for compressing a video signal based on MPEG2 or a signal compressed by MPEG1 is recorded. Also, the reproduction speed at the time of high speed reproduction is not limited to 4 × speed and 18 × speed, and the special reproduction data recording area is arranged according to the reproduction speed required for the digital signal recording device, and the error correction code is provided. A system having a recording format in which a data area is arranged such that the special reproduction data recording area and the error correction check code recording area can both be reproduced from the head during special reproduction of the recording area will produce the same effect.

Further, since the data is arranged as described above, one transport packet is not arranged across two or more tracks, so that the data arrangement can be completed for one track. It is possible to reduce the circuit scale when performing interleaving, and
Even if the interleave depth is set to 12 tracks in the AL or SECAM area, the data is completed for one track, and therefore control is very easy. In addition, since the data block can be composed of 2 tracks, 12
It is also very easy to control when performing track interleaving. For example, in the case of the recording format shown in the conventional example, since each track main area is composed of 97 sync blocks, data will be arranged in a cycle of 5 tracks. That is, when converting the input transport packet into the sync block format shown in FIG. 6B and recording the data, data is transferred from the head sync block every 5 tracks from the head data of the transport packet in the conventional example. However, in this case, it is necessary to add an identification signal for identifying the start data to detect the sync block to which the start transport packet is added. In the case of completion, since the head of the transport packet can be easily detected without adding the identification signal, the ID signal, or H1 in FIG. 6B,
The H2 header area can be effectively used, and the circuit scale can be reduced.

When recording the data transmitted in the transport packet format represented by MPEG2 in the digital VTR represented by the SD standard, the first embodiment is adopted.
In the above, two transport packets were converted into the 5 sync block format and recorded, but the present invention is not limited to this, and when the sync block format is generated, n transport packets are input using the input m transport packets. Generates sync block data for a line.
(M and n are positive numbers) Further, when recording the converted sync block format data on the recording medium, recording on the recording medium is performed so that the n sync block data is arranged on the same track. By configuring the format, there is an effect that the data of the transport packet can be efficiently converted into the sync block format. Further, since the data of the n sync blocks is completed in the same track, when converting the data of the sync block format into the data of the transport packet at the time of reproduction, the track information such as the track identification signal and the sync block number are You can easily separate the above set of n sync block formats using
Particularly, there is an effect that the circuit scale of the reproducing system can be reduced. Moreover, there is no need to record the identification signal of the n sync block, and the data recording area can be effectively utilized. The length of one sync block is also shown in FIG.
It is not limited to that shown in FIG.

Example 2. The arrangement of the data recording area for 4 × speed reproduction, the data recording area for 18 × speed reproduction, the error correction check code recording area, or the number of areas is not limited to this. Also, the track cycle is not limited to the 4-track cycle. Further, in the first embodiment, the 4 × speed or the 18 × speed is selected as one example of the high speed reproduction speed, but the present invention is not limited to this, and other rotary speeds such as the rotary head 27a, A data recording area for special reproduction and an error correction code recording area are provided on the scanning loci of and 27b, and the error correction check code to be recorded in this area is added with the error correction check code for the normal reproduction data according to the application. The same effect can be obtained by arranging to switch whether to add the error correction check code to the special reproduction data.

In the first embodiment, the error correction check code stored in the error correction check code recording area is switched according to the input command (for example, set by the user). However, the present invention is not limited to this. For example, in order to reduce cost, a digital VTR having only one of the error correction encoder and the error correction decoder (only the error correction code added to the special reproduction data is recorded and reproduced in the error correction code recording area). Digital V with configuration
Even if it is a TR or a digital VTR having a structure for recording and reproducing only the error correction code added to the normal reproduction data in the above area), the magnetic tape recorded by each digital VTR is compatible and which model is used. However, it can be played back, and in the future the digital VTR
When used as an external storage device such as a computer, a powerful error correction check code can be added to the recorded data in the same recording format, and it can be shared with the external storage device. Further, as described above, since the recording area on the recording track is used efficiently, the amount of data that can be allocated to special reproduction data is increased, and the reproduction image quality during special reproduction can be improved.

A low-priced digital VTR which does not have an encoder for an error correction check code added to the error correction check code recording area and a decoder.
However, if a flag for identifying the above signal is recorded in, for example, an ID signal, compatibility with the above digital VTR can be achieved, and it is not necessary to determine a new recording format for low cost, and in the future, a computer will be used. Even when the above digital VTR is used as an external recording device such as the above, compatibility can be achieved.

When performing compatible reproduction using the above-mentioned three types of low-priced digital VTRs, an error correction decoder for decoding the error correction check code recorded in the error correction check code recording area is prepared. If not, it is needless to say that compatibility can be achieved as described above by configuring so that reproduced digital data is output without performing error correction decoding using the error correction check code.

Example 3. Although the identification signal of the error correction check code is added to the ID signal in the first embodiment, the present invention is not limited to this. In the first embodiment, since the sub-code area is reproduced at the time of high-speed reproduction, the above three signals (error correction check code for normal reproduction, error correction check code for high-speed reproduction, or error correction check code other than the above-mentioned error correction code are included in the sub-code area. If an identification signal of a signal indicating that the signal is a signal (for example, a signal of a predetermined fixed pattern) is recorded, the same effect can be obtained. At this time, there is almost no increase in the circuit scale. The identification signal may be added to both the ID signal and the subcode signal. Further, in the case of a standard in which an error correction code is always added, the identification flag is 2
It goes without saying that it is only necessary to switch two signals. Further, the C4 check code is H1 shown in FIG.
It goes without saying that the same effect can be obtained even if the identification signals of the above-mentioned three signals are recorded in this header portion without being applied to the header portion. Alternatively, it may be stored in the H2 header portion and transmitted. Further, it may be added to the H1 or H2 header portion of the normal reproduction or special reproduction data and transmitted. As mentioned above, H1 or H2
By transmitting the data by adding it to the header part, especially in a shared machine with the SD digital VTR, only the identification code of the recording signal can be added and recorded in the ID part, so that the limited ID area can be effectively used.

Example 4. Regarding the error correction check code recording area, when there is a track in which the special reproduction data is not recorded (T4 track shown in FIG. 8), the same azimuth angle at which the special reproduction data is recorded is set. The recording area of the error correction check code is provided at the same height as the error correction check code recording area provided on the track formed by the rotary head. (T2 track shown in FIG. 8) As a result, the burst error correction capability can be made substantially uniform for tracks having the same azimuth angle, and control at the time of interleaving at the time of C4 check code generation is greatly simplified, reducing the circuit scale. Can be achieved. Although the circuit scale is slightly increased, a track having no special reproduction area is different from the error correction code recording area arranged on the track recorded at the same azimuth angle and having the special reproduction data recording area. It goes without saying that they may be arranged in areas (different heights).

Example 5. Also, the C4 check code and C
The code configurations of the five check codes are (245, 230, 1
6) Reed-Solomon code, and (30, 25, 6)
Although the Reed-Solomon code is used, the present invention is not limited to this, and it is needless to say that the same effect can be obtained if the recording format is configured in the above manner even if other code configurations are used. That is, a special reproduction data recording area and an error correction code recording area are provided on the scanning loci of the rotary heads 27a and 27b, and the error correction check code recorded in this area is used as an error for the normal reproduction data depending on the application. The same effect can be obtained if it is configured to switch between adding the correction check code and adding the error correction check code for the special reproduction data.

Further, the depth of interleaving of data to be applied when generating the error correction check code to be added to the normal reproduction data is set to 10 tracks in the NTSC range, and P
In the AL and SECAM areas, the error correction block for normal reproduction is constructed with a depth of 12 tracks, and the normal reproduction data is interleaved to generate an error correction check code for normal reproduction. Thus, for example, in the SD digital VTR, the frame frequency is 30 Hz in the NTSC area.
In addition, since digital data is recorded in correspondence with the frame frequency 25 in the PAL and SECAM areas,
It is possible to interleave the normal reproduction data in accordance with the frame frequency of the SD standard digital VTR. Therefore, a digital VTR for recording normal signals
And a digital VTR for recording an ATV signal or the like can be used in a very compact system (the number of the error correction block can be identified by identifying the interleaved data by the track number added to the ID signal). Is not required to be additionally provided, and a circuit for separating the error correction block is not required to be additionally provided). The circuit scale can be reduced.

[0137]

Since the present invention is constructed as described above, it has the following effects.

According to the digital signal recording apparatus of the first aspect of the present invention, a digital video signal coded in a frame or field, or in a frame or field is input in the form of a transport packet, and a digital video signal. In a digital signal recording device in which an audio signal is transparently recorded, the intra image signal is first separated from the transport packet. Then, in the separated intra-image signal, the high frequency component in the image signal is removed and the recording rate is further compressed. Then, the intra-picture signal whose recording rate is compressed is reconstructed to generate special reproduction data. On the other hand, the input transport packet data is reconstructed and converted into the sync block format. When recording the special reproduction data, when the head scans the recording medium at a predetermined high reproduction speed,
It is arranged on the scanning locus of the head. At that time, the area for recording the error correction check code is also arranged on the scanning locus of the head. In the area for recording the error correction check code, either the error correction check code added to the special reproduction data or at least the error correction check code added to the record data converted into the sync block format is used. Data is recorded, and a recording format is generated so that the identification signal of the error correction code recorded in the recording area of the error correction check code is added and recorded in the recording signal. There is an effect that the recording areas (special reproduction data recording area, error correction code recording area, etc.) can be effectively utilized.

For example, in a digital signal recording device as a consumer device, the above-mentioned ATV signal (or motion compensation prediction represented by MPEG1, MPEG2, etc. (when decoding one image data, refer to other image data). When recording image data such as a signal which adopts a compression method based on a compression method for restoring image data), for example, an error correction check code for special reproduction data is recorded in the area. When the digital signal recording device is recorded in an area and used for business, or when the digital signal recording device is used as an external recording device for recording data such as a computer, normal reproduction is performed in the recording area of the error correction check code. Control is performed so that an error correction code to be added to the work data is added. that time,
With the same recording format, a powerful error correction check code can be added to the required data,
Since the identification signal is recorded in the recording signal, for example, even in a digital signal recording / reproducing apparatus having only one of the decoders for the error correction code, the error recorded in the error correction check code recording area is recorded. If the type of the correction check code is identified and the decoding control of the error correction code is performed, compatibility reproduction can be performed.

Further, as described above, the recording area of the error correction check code is also used as an area for recording the error correction check code added to the normal reproduction data and the error correction check code added to the special reproduction data for use. Since the data is switched and recorded in accordance with this, the error correction check code recording area in the limited additional data recording area can be suppressed to a small amount. Therefore, the area for recording the special reproduction data can be increased accordingly and the special reproduction can be performed. Since the recording rate of the use data can be improved, the reproduction image quality at the time of special reproduction can be improved.

Further, according to the digital signal recording apparatus of the second aspect of the present invention, the data transmitted in the transport packet format represented by MPEG2 is recorded in the SD.
When recording on a digital VTR represented by the standard, when the sync block format is generated by the recording data generating means, data of n lines of sync block is generated by using the input m transport packets. Also, when recording the converted sync block format data on the recording medium, the transport packet is configured by configuring the recording format on the recording medium so that the data of the n sync blocks is arranged on the same track. There is an effect that the data of can be efficiently converted into the sync block format. Also,
Since the above n sync block data is completed within the same track, when converting sync block format data into transport packet data during playback, track information such as a track identification signal and sync block number are used. The set of n sync block formats can be easily separated, and in particular, the circuit scale of the reproduction system can be reduced. Moreover, there is no need to record the identification signal of the n sync block, and the data recording area can be effectively utilized.

According to the digital signal recording apparatus of the third aspect of the present invention, when the special reproduction data generating means uses the input intra image data to generate the special reproduction data, the special reproduction data is input. Generate in the form of port packets. When the special reproduction data generated in the transport packet format is recorded on the recording medium, it is converted into the sync block format and recorded similarly to the input data, so that the high speed reproduction is performed by the digital signal reproducing apparatus. , No circuit for transport packet generation is required, and a circuit for converting the sync block format for normal playback into transport packets can be shared, and the circuit scale is reduced especially in a playback-only device. There is an effect that can be.

According to the digital signal recording apparatus of the fourth aspect of the present invention, when the error correction check code is added to at least the data output from the recording data generating means, the data is recorded by using the recording data of two tracks. Make up a block. A plurality of the above data blocks are collected to form an error correction block for normal reproduction data. And
Since the data in the error correction block for normal reproduction is interleaved to generate an error correction check code, SD
The data recording area of the digital VTR represented by the standard can be effectively used to generate the error correction check code for normal reproduction, and the burst error correction capability can be sufficiently ensured. Further, since the recording format described in claim 2 can be generated, there is an effect that the circuit scale in the reproducing system can be reduced.

According to the digital signal recording apparatus of the fifth aspect of the present invention, since the recording area of the error correction check code is arranged adjacent to the special reproduction data recording area, the special reproduction is surely performed at high speed reproduction. Since the error correction check code recording area can be reproduced together with the use data, the special reproduction data and the error correction check code can be efficiently arranged on the recording medium, and the influence of the linearity of the track, etc. can be prevented. There is an effect that it is possible to realize a data arrangement that is difficult to receive.

According to the sixth aspect of the digital signal recording apparatus of the present invention, the interleaving depth of the data applied when the error correction check code added to the recording data generating means is 10 tracks in the NTSC range. In the PAL and SECAM areas, the error correction block for normal reproduction is formed with a depth of 12 tracks, and the normal reproduction data is interleaved to generate an error correction check code for normal reproduction. As a result, for example, in the SD standard digital VTR, the frame frequency is 3 in the NTSC range.
Since digital data is recorded in correspondence with 0 Hz and in the PAL and SECAM areas with a frame frequency of 25, it is possible to interleave normal reproduction data in accordance with the frame frequency of the digital VTR of the SD standard. Therefore, a digital VTR for recording a normal signal and a digital VTR for recording an ATV signal, for example.
Sharing with the TR can be performed in a very compact system, and the number of shared portions when configuring the above digital VTR is increased, and the circuit scale can be reduced.

According to the digital signal recording apparatus of the seventh aspect of the present invention, when the data transmitted in the transport packet format represented by MPEG2 is recorded on the digital VTR represented by the above SD standard, When generating the sync block format by the recording data generation means, the data of the sync block of n lines is generated by using the input m transport packets. At that time, an identification signal for identifying the data recorded in the error correction check code recording area is recorded in a data recording portion left when the transport packet is converted into the sync block format by the recording data generating means. The area is provided and the identification signal is transmitted.
There is an effect that it is not necessary to newly provide a recording area for transmitting the identification signal, and the recording data can be efficiently generated. Further, this also has the effect of increasing the recording area of the special reproduction data and improving the reproduction image quality of the high-speed reproduction image.

According to the digital signal recording apparatus of the eighth aspect of the present invention, when the error correction check code is added to the output of the recording data generating means, the output of the recording data generating means and a part or all of the output. The data block is constructed by using the output from the special reproduction data generating means.
Since a plurality of blocks of the above data blocks are interleaved with the data to form an error correction check code for normal reproduction, when the area for recording special reproduction data is repeated at a plurality of track cycles, normal reproduction data If the control is performed so that the error correction code is added to only the data block, the above data block cannot be efficiently constructed, the maximum burst error correction capability is extremely different in each track, or the circuit scale unnecessarily increases. In some cases, by generating the data block by using a part or all of the special reproduction data, the degree of freedom in constructing the data block is increased, and the data block configuration is increased accordingly. The circuit scale can be reduced and the maximum burst error correction capability can be made uniform between tracks. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a recording system of a digital VTR which is an embodiment of the present invention.

FIG. 2 is a block diagram of a trick play data generation circuit 12 that is an embodiment of the present invention.

FIG. 3 is a block configuration diagram of a quadruple speed data generation circuit 14 that is an embodiment of the present invention.

FIG. 4 is a layout view of rotary heads of respective channels on a typical rotary drum used in an SD standard digital VTR.

FIG. 5 is a diagram showing a recording format in one track of a digital VTR which is an embodiment of the present invention.

6A and 6B are a transport packet diagram of an input bitstream and a recording data packet diagram to be recorded on a magnetic tape according to an embodiment of the present invention.

FIG. 7 is a diagram showing the number of sync blocks that can be reproduced from one track at each high reproduction speed.

FIG. 8 is a diagram showing a track pattern of a 4-track cycle including an arrangement of data recording areas for special reproduction which is an embodiment of the present invention.

FIG. 9 is a diagram showing a recording format on a magnetic tape which is an embodiment of the present invention.

FIG. 10 is a diagram for explaining a method of configuring a data block when configuring an error correction check code to be added to normal reproduction data according to an embodiment of the present invention.

FIG. 11 is a diagram for explaining a method of interleaving five data blocks when data is added with an error correction check code, which is an embodiment of the present invention.

FIG. 12 is a diagram showing a configuration of an error correction check code (C5 check code) added to trick play data according to an embodiment of the present invention.

FIG. 13 is a digital VTR which is an embodiment of the present invention.
3 is a block configuration diagram of a reproduction system of FIG.

FIG. 14 is a diagram showing the relationship between the scanning trace of the rotary head and the track pattern when the magnetic tape having the recording format shown in FIG. 9 is reproduced at 4 × speed with a 1 Ch × 2 drum structure.

FIG. 15 is a diagram showing the relationship between the scanning trace of the rotary head and the track pattern when the magnetic tape having the recording format shown in FIG. 9 is reproduced at 18 × speed with a 1 Ch × 2 drum structure.

FIG. 16 is a track pattern diagram of a conventional general home-use digital VTR.

FIG. 17 is a diagram showing a head scanning locus of the rotary head during normal reproduction and high-speed reproduction of the conventional digital VTR.

FIG. 18: Conventional digital VTR capable of high-speed reproduction
It is a block configuration diagram of.

FIG. 19 is a conceptual diagram of a system when performing normal reproduction and high-speed reproduction with a conventional digital VTR.

FIG. 20 is a diagram showing an example of a rotary head scanning locus during general high-speed reproduction.

[Fig. 21] Fig. 21 is a diagram for explaining an overlapping area at a plurality of conventional high-speed reproduction speeds.

22 is a rotary head scanning locus diagram at 5 × speed and 9 × speed in a conventional digital VTR. FIG.

FIG. 23 is a scanning locus diagram of two rotary heads during 5 × speed reproduction in a conventional digital VTR.

FIG. 24 is a track layout diagram of a conventional digital VTR.

FIG. 25 is a data format diagram of a video signal recording area in one track of a video signal according to the SD standard.

FIG. 26 is a diagram showing the structure of one sync block in the SD standard.

[Explanation of symbols]

4 variable length encoder, 5 counter, 6 data extracting circuit, 7 EOB adding circuit, 10 header analyzing circuit, 1
2 special reproduction data creation circuit, 13 first memory,
14 4 times data generation circuit, 15 18 times data generation circuit, 16 second memory, 17 third memory, 18
First error correction coding circuit, 19 data synthesizing circuit, 2
1 Error Correction Code Control Circuit, 22 4th Memory, 23
Second error correction code circuit, 24 Third error correction code circuit, 25 Digital modulation circuit, 42 Transport header correction circuit, 43 Header addition circuit, 44 Packetization circuit, 45 Transport header addition circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H03M 13/00 8730-5K H04N 9/80

Claims (8)

[Claims] 1. A digital signal recording device for transparently recording a digital audio signal and a digital video signal, which is input in the form of a transport packet and is encoded in a frame or field or between frames or fields, Data separation means for separating the frame or field encoded digital video signal from the transport packet and the frame or field encoded digital video signal separated by the data separation means are reproduced. Special reproduction data generating means for forming special reproduction data, recording data generating means for reconstructing input transport packet data to generate a sync block format, and predetermined high-speed reproduction speed When the head scans the recording medium at a time, the special reproduction data is placed on the scanning locus of the head,
And an area for recording the error correction check code, and in the area for recording the error correction check code, the error correction check code added to the special reproduction data, or at least the data output from the recording data generating means. Data of either one of the error correction check codes to be added to is recorded, and the identification signal of the error correction code recorded in the recording area of the error correction check code is added and recorded in the recording signal. Characteristic digital signal recording device. 2. When the sync block format is generated by the recording data generating means, the data of the sync block of n lines is generated by using the m transport packets and is output from the recording data generating means. 2. The digital signal recording apparatus according to claim 1, wherein the recording data is arranged so that the data of the sync block of the n lines is not recorded over a plurality of recording tracks. 3. The trick play data generated by the trick play data generating means is generated in the form of the input transport packet, and at the time of recording, in the sync block format like the input transport packet. 2. The data is converted and recorded.
The digital signal recording device described. 4. When adding an error correction check code to the data output from at least the recording data generating means,
2. The digital signal recording apparatus according to claim 1, wherein a data block is formed by using recording data of two tracks, and an error correction check code is generated by interleaving a plurality of blocks of the data block. 5. The digital signal recording apparatus according to claim 1, wherein a recording area for the error correction check code is arranged adjacent to the special reproduction data recording area. 6. The depth of interleaving of data applied when generating the error correction check code added to the recording data generating means is 10 tracks in the NTSC range,
5. The digital signal recording apparatus according to claim 4, wherein the depth is 12 tracks in the PAL and SECAM areas. 7. A data recording portion which is left over when the recording data generating means converts the identification signal for identifying the data recorded in the error correction check code recording area into the sync block format. 3. A digital signal recording apparatus according to claim 2, wherein a recording area is provided in the recording area and data is transmitted using the recording area. 8. When adding an error correction check code to the output of the recording data generating means, the output of the recording data generating means,
2. The digital signal recording apparatus according to claim 1, wherein the data blocks are constructed by using outputs from some or all of the special reproduction data generating means.