JP3304634B2 - Digital signal reproduction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compact disk player (hereinafter referred to as CD), a digital audio tape recorder (hereinafter referred to as DAT), and a digital video signal recording / reproducing apparatus (hereinafter referred to as digital VTR). The present invention relates to a digital signal reproducing apparatus such as a digital VTR for recording a bit stream of a digital video signal and a digital audio signal represented by MPEG2 or the like, and particularly to an interface control at the time of special reproduction.

[0002]

2. Description of the Related Art FIG. 29 shows a general home digital VT.
FIG. 7 is a track pattern diagram of R. In the figure, a diagonal track is formed on a magnetic tape, and one track is divided into two areas, a video area for recording a digital video signal and an audio area for recording a digital audio signal.

There are two methods for recording video and audio signals on such a home digital VTR. One is a so-called baseband recording system in which an analog video signal and an audio signal are input and recorded using a high-efficiency video or audio encoder. The other is a so-called transparent recording method for recording a digitally transmitted bit stream.

ATV being discussed in the United States
To record (Advanced Television) signals, the latter transparent recording method is suitable. The reason is that the ATV signal is a signal that has already been digitally compressed and does not require a high-efficiency encoder or decoder, and there is no deterioration in image quality because it is recorded as it is. On the other hand, the disadvantages are the image quality at the time of high-speed reproduction and special reproduction such as still and slow. In particular, if a bit stream is simply recorded on an oblique track as it is, almost no image can be reproduced during high-speed reproduction.

[0005] As a digital VTR system for recording an ATV signal as described above, "Intern" was held in Ottawa, Canada from October 26 to 28, 1993.
national Workshop on HDTV '
93, "A Recording
Method of ATV data on aC
onser Digital VCR ". The contents will be described below as a conventional example.

[0006] As a basic specification of a prototype of a home digital VTR, SD (Standard Definition) is used.
Ition) mode, the recording rate of the digital video signal is 25 Mbps, and the field frequency is 60 Hz.
In some cases, one frame of video is recorded in a video area of 10 tracks. Here, if the data rate of the ATV signal is 17-18 Mbps, transparent recording of the ATV signal becomes possible in this SD mode.

FIG. 30 is a diagram showing head scanning trajectories of a rotary head during normal reproduction and high-speed reproduction of a conventional digital VTR. In the figure, adjacent tracks are alternately recorded diagonally by heads having different azimuth angles. During normal playback, the tape feed speed is the same as during recording, so the head moves along the recording track as shown in FIG.
It can be traced as shown in FIG. However, at the time of high-speed reproduction, since the tape speed is different, it is possible to trace across several tracks and reproduce only fragments of the same azimuth track. FIG. 30B shows a case of 5 × fast forward.

An MPEG2 bit stream (ATV
The bit stream of the signal substantially conforms to the MPEG2 bit stream. ) Can be independently decoded only by intra-coded blocks without referring to other frames. If the MPEG2 bit stream is recorded in each track in order, the reproduction data at the time of high-speed reproduction is obtained by separating the intra-coded data from the intermittently reproduced reproduction data, The image is reconstructed using only the data obtained. At this time, the area to be reproduced is not continuous on the screen, and the fragments of the block spread on the screen. Furthermore, because the bitstream is variable length coded, there is no guarantee that all of the screen will be updated periodically, and some may not be updated for long periods of time. As a result, the image quality during high-speed playback is not sufficient,
This would not be acceptable for a home digital VTR.

FIG. 31 is a block diagram of a conventional bit stream recording apparatus capable of high-speed reproduction. here,
The video area of each track is divided into a main area for recording all ATV signal bit streams and a copy area for recording an important part (HP data) of a bit stream used for image reconstruction during high-speed reproduction. At the time of high-speed playback, only the intra-coded block is valid, so this is recorded in the copy area. To further reduce the data, the low-frequency components are extracted from all the intra-coded blocks and the HP data Record as In FIG. 31, 1 is a bit stream input terminal, 2 is a bit stream output terminal, 3 is an HP data output terminal, 4 is a variable length decoder, 5 is a counter, 6 is a data extraction circuit, and 7 is EOB (End). of Blo
ck) Additional circuit.

[0010] The MPEG2 bit stream is input from an input terminal 1 and output from an output terminal 2 as it is.
It is sequentially recorded in the main area. On the other hand, the bit stream from the input terminal 1 is also input to the variable length decoder 4,
The syntax of the MPEG2 bit stream is analyzed, an intra image is detected, the timing is generated by the counter 5, the low frequency components of all blocks of the intra image are extracted by the data extracting circuit 6, and
The EOB is added by the OB addition circuit 7 to compose HP data, which is recorded in the copy area.

FIG. 32 is a diagram showing an outline of a conventional digital VTR at the time of normal reproduction and at the time of high-speed reproduction. At the time of normal reproduction, all bit streams recorded in the main area are reproduced, and MPEG2
Sent to the decoder. HP data is discarded. On the other hand, at the time of high-speed reproduction, only the HP data in the copy area is collected and sent to the decoder, and the bit stream in the main area is discarded.

Next, the arrangement of the main area and the copy area on one track will be described. FIG. 33 is a head scanning locus diagram during general high-speed reproduction. If the tape speed is an integer multiple speed and phase locked, head scanning is synchronized with the same azimuth track. Therefore, the position of the data to be reproduced is fixed. In the drawing, assuming that a portion where the output level of the reproduction signal is higher than -6 dB is reproduced, a shaded area is reproduced by one head. FIG. 33 shows an example of 9 × speed. At 9 × speed, signal reading in this shaded area is guaranteed. Therefore, HP data may be recorded in this area. However, at other double speeds, signal reading is not guaranteed, and this area must be selected so that reading can be performed at several tape speeds.

FIG. 34 is a diagram for explaining a conventional overlap area at a plurality of high-speed reproduction speeds, and shows an example of a scan area at three tape speeds in which the head is synchronized with the same azimuth track. There are several overlapping areas in the area scanned at each tape speed. A copy area is selected from these areas to guarantee reading of HP data at different tape speeds. FIG. 34 shows the case of the fast forward of 4 times, 9 times, and 17 times. However, these scan areas are the same as those of the fast forward of −2 times, −7 times, and −15 times.

At some tape speeds, it is impossible for the head to trace exactly the same area. This is because the number of tracks traversed by the head differs depending on the tape speed. In addition, it must be possible to trace from any one azimuth track.

FIG. 35 is a diagram showing the trajectories of 5 × and 9 × speed head scanning in a conventional digital VTR. In the figure,
Regions 1, 2, and 3 are selected from the 5 × speed and 9 × speed overlapping regions. By repeatedly recording the same HP data on nine tracks, the HP data can be read at both 5 × speed and 9 × speed.

FIG. 36 is a diagram showing two head scanning trajectories during 5 × speed reproduction in a conventional digital VTR. As can be seen, the same number of tracks as the tape speed and the same HP
By repeatedly recording data, HP data is
Data can be read by a head synchronized with the same azimuth track. Therefore, by repeating the copying of the HP data to the same number of tracks as the maximum tape speed of the high-speed reproduction, it is possible to ensure that the copied HP data is read at several tape speeds in either the forward direction or the reverse direction. Can be.

FIG. 37 is a track layout diagram of a conventional digital VTR, showing an example of a main area and a copy area. In a home digital VTR, the video area of each track is composed of 135 sync blocks, the main area is 97 sync blocks, and the copy area is 32 sync blocks. This copy area is shown in FIG.
The overlapping areas corresponding to the 4, 7, and 17-times speeds indicated by are selected. In this case, the data rate of the main area is about 1
7.46 Mbps, and the same data is recorded 17 times in the copy area, so that it is about 338.8 kbps.

[0018]

The conventional home digital VTR is configured as described above, and as described above, special reproduction data is repeatedly recorded in the copy area many times. However, the recording rate of the data for special reproduction is extremely low, and there is a problem that a sufficient reproduction image quality cannot be obtained especially in slow reproduction or high-speed reproduction. For example, if there are two intra frames per second,
Data amount of ATV signal only for intra coding is about 3Mb
ps, but about 340 Kbps in the conventional example
Recording can only be performed, and the reproduced image quality is extremely deteriorated.

When outputting a bit stream (transport packet) of an ATV signal formed by using data recorded in the special reproduction area during special reproduction, only intra-coded data is output.
For example, when the amount of data of an intra frame is large, there is a problem that a transport packet overflows in a process of transmitting the transport packet and a system breaks down in an ATV decoder. In addition, there is a problem that the memory capacity of the special reproduction memory on the reproduction side becomes unnecessarily large.

FIG. 38 shows the structure of an error correction code for a video signal area and an audio signal area in one track of a digital VTR defined in the SD mode (hereinafter referred to as SD standard). According to the SD standard, an error correction code (85, 7
7, 9) Reed-Solomon code (hereinafter, referred to as C1 check code) is used in the vertical direction (149, 138, 12) Reed-Solomon code (hereinafter, referred to as C2 check code). In addition, the same (85, 77, 9) as the video signal in the recording direction as the error correction code of the audio signal area.
And a Reed-Solomon code (C1, check code) (14, 9, 6) in the vertical direction. Also, one sync block (C1 block) as a recording unit in the recording direction is shown in FIG.
Shown in As shown in FIG. 39, one sync block is composed of 90 bytes, of which the first 5 bytes record a sync pattern and an ID signal, and the last 8 bytes contain an error correction code (C1 detection code). ) Is recorded.

As described above, at the time of special reproduction (high-speed reproduction, slow reproduction, still reproduction, etc.), the rotating head obliquely crosses the recording track, and the reproduction signal is intermittently reproduced from each track. Therefore, at the time of special reproduction, FIG.
The error correction block (video data) shown in FIG. Therefore, at the time of special reproduction, only error correction using the C1 check code is performed on the reproduction data.

[0022] When subjected only error correction by C1 check code, when the symbol error rate is 0.01, the error detection probability is detected one error 1.56 × 10 ^-3, and the approximately 8 sync blocks Will be. Particularly, during special reproduction, the reproduction output is not stable, so that the symbol error rate often becomes 0.01 or more. Since the recording data has been subjected to variable-length encoding, if an error occurs, the subsequent reproduced data cannot be used, resulting in deterioration of the reproduced image quality. Further, residual error is also very occurrence frequency as high as 7.00 × 10 ^{over 8.}

When outputting a bit stream (transport packet) of an ATV signal formed by using data stored in the special reproduction area during special reproduction, only intra-coded data is output.
For example, when the amount of data of an intra frame is large, there is a problem that a transport packet overflows and a system breaks down in an ATV decoder. In addition, there is a problem that the memory capacity of the special reproduction memory on the reproduction side becomes unnecessarily large.

The present invention has been made to solve the above-described problems. In particular, the present invention has been made to improve the reproduction image quality at the time of slow reproduction or high-speed reproduction, and at the same time, at the time of special reproduction (high-speed reproduction, slow reproduction, and The interface control can be performed so that the control on the ATV decoder side is not different from that during normal reproduction at the time of (still reproduction), and the memory capacity at the time of high-speed reproduction can be reduced so that high-speed reproduction can be performed efficiently. It is intended to obtain a signal reproducing device.

[0025]

According to a first aspect of the present invention, there is provided a digital signal reproducing apparatus, comprising: a digital video signal input in the form of a packet and encoded within a frame or a field, or between a frame or an inter-field; And the digital audio signal is transparently recorded, and special reproduction data to be used during special reproduction is generated from the digital video signal subjected to intra-frame or field encoding from the packet , and the generated special reproduction data is generated. In a digital signal reproducing apparatus for reproducing a recording medium recorded at a predetermined position, data separating means for separating the special reproduction data from the reproduction signal during special reproduction, and storing the separated special reproduction data Data storage means and all macros in the slice A still image slice data generating means for generating slice data in which a lock has a motion vector of 0 and a prediction error of 0, wherein the special reproduction data for one frame or one field separated from the data storage means; And outputting the output of the still image slice generating means for a predetermined number of frames.

According to a second aspect of the present invention, there is provided a digital signal reproducing apparatus, comprising: a digital video signal input in the form of a packet and encoded within a frame or a field, or between a frame or an inter-field; Are recorded transparently, and special reproduction data to be used at the time of special reproduction is generated from the digital video signal subjected to frame or intra-field encoding from the packet , and the generated special reproduction data is stored at a predetermined position. A digital signal reproducing apparatus for reproducing a recording medium recorded in the digital reproduction device; a data separation unit for separating the special reproduction data from the reproduction signal during the special reproduction; and a data storage unit for storing the separated special reproduction data. , All macroblocks in the slice And a still image slice data generating means for generating slice data having a prediction vector of 0 and a prediction error of 0. The special reproduction data separated by the data separation means from the reproduction data intermittently reproduced is provided. One or more slices and the output of the still image slice data generating means are used to form a transport packet for one frame, and the transport packet is a field or a packet in an inter-frame prediction mode. The packet is configured to transmit the trick play data in a forced intra-frame mode.

In the digital signal reproducing apparatus according to a third aspect of the present invention, during still reproduction, the output of the still picture packet generating means is changed to the end of the final data output of the frame or field reproduced during normal reproduction. Later, it is configured to always select.

In the digital signal reproducing apparatus according to a fourth aspect of the present invention, the servo system is locked and the special reproduction intra-frame data is reproduced from the high-speed reproduction area after the mode for high-speed reproduction. Until
To select the output of the still image packet generation means,
The data switching means is configured to be controlled.

A digital signal reproducing apparatus according to a fifth aspect of the present invention is configured to use the above-mentioned control method at least at the time of special reproduction in the reverse direction.

A digital signal reproducing apparatus according to a sixth aspect of the present invention is a digital signal reproducing apparatus, comprising: a digital video signal input in a packet state, encoded in a frame or a field, or encoded between a frame or an inter-field; Are recorded transparently, and special reproduction data to be used at the time of special reproduction is generated from the digital video signal which has been subjected to frame or intra-field encoding from the packet , and the generated special reproduction data is stored at a predetermined position. In a digital signal reproducing apparatus for reproducing a magnetic tape recorded in a digital signal, data separation means for separating the special reproduction data from a reproduction signal, and decoding of data output from the digital signal recording / reproduction apparatus to restore reproduced image data When doing
It has a specific area fixed packet generating means for generating a packet for stopping a signal of a specific area on the screen, and when forming a reproduced image using intermittently reproduced data during special reproduction, The output of the packet fixing means,
By switching the reproduction data, one frame of the special reproduction data is divided into a plurality of frames and transmitted.

[0031]

In the digital signal reproducing apparatus according to the first aspect of the present invention, a digital video signal and a digital audio signal which are input in the form of a packet and which are coded within a frame or a field, or between a frame or an inter-field, and Is recorded transparently, and special reproduction data to be used at the time of special reproduction is generated from the digital video signal subjected to frame or intra-field encoding from the packet , and the generated special reproduction data is placed at a predetermined position. In a digital signal reproducing apparatus for reproducing a recorded recording medium,
At the time of special reproduction, a data separation unit that separates the special reproduction data from the reproduction signal, a data storage unit that stores the separated special reproduction data, and all macro blocks in the slice are predicted with a motion vector of 0. A still image slice data generating means for generating slice data having an error of 0, and outputting the one frame or one field of the special reproduction data separated from the data storage means, Since the still image slice generating means is controlled so as to output the output of the generating means for a predetermined number of frames, the memory capacity can be reduced and the circuit size can be reduced.
Special reproduction can be realized without making the decoder aware of the special reproduction mode.

In the digital signal reproducing apparatus according to a second aspect of the present invention, a digital video signal input in the form of a packet and encoded within a frame or a field, or between a frame or an inter-field, and a digital audio signal. The signal and the signal are transparently recorded, and special reproduction data to be used at the time of special reproduction is generated from the digital video signal subjected to frame or intra-field encoding from the packet , and the generated special reproduction data is converted to a predetermined data. In a digital signal reproducing apparatus for reproducing a recording medium recorded at a position, data separating means for separating the special reproduction data from the reproduction signal during special reproduction, and data storage means for storing the separated special reproduction data And all macros in the slice A still image slice data generating means for generating slice data having a motion vector of 0 and a prediction error of 0, wherein the special data separated from the intermittently reproduced data by the data separating means is provided. One or a plurality of slices of the reproduction data are used to form a transport packet for one frame using the output of the still image slice data generating means, and the transport packet is a field or a packet in an inter-frame prediction mode. Packets are configured to transmit intermittently reproduced special reproduction data in forced intra-frame mode, so that the memory capacity during high-speed reproduction can be reduced, and the circuit scale can be reduced. Can be.

In the digital signal reproducing apparatus according to a third aspect of the present invention, during still reproduction, the output of the still picture packet generating means is output as the final data of the frame or the frame reproduced during normal reproduction. After the end, the digital VTR is always output even in still reproduction without using data for special reproduction.
There is no need to provide a memory for storing one frame of intra information on the side, and a good reproduced image can be formed by using the still image packet generating means used for high-speed reproduction.

In the digital signal reproducing apparatus according to a fourth aspect of the present invention, the servo system is locked when the mode is set to the high-speed reproduction mode, and the data of the intra-frame for special reproduction is transmitted from the high-speed reproduction area. Since the data switching means is controlled so as to select the output of the still picture packet generating means until the reproduction, the mode transition can be performed smoothly without disturbing the reproduced image even at the time of mode transition. Can be.

Further, in the digital signal reproducing apparatus according to the fifth aspect of the present invention, since the above-mentioned control system is used at least at the time of special reproduction in the reverse direction, the memory capacity at the time of high-speed reproduction can be reduced. While you can
A memory for rearranging data provided for reverse reproduction is not required, and the circuit scale can be further reduced.

In the digital signal reproducing apparatus according to a sixth aspect of the present invention, a digital video signal input in the form of a packet and encoded within a frame or a field, or between a frame or an inter-field, and a digital audio signal. The signal and the signal are transparently recorded, and special reproduction data to be used at the time of special reproduction is generated from the packet by the digital video signal subjected to intra-frame or intra-field encoding. In a digital signal reproducing apparatus for reproducing a recording medium recorded at a position, data separating means for separating the special reproduction data from a reproduction signal, decoding data output from the digital signal recording / reproducing apparatus, and reproducing reproduced image data. When restoring, the on-screen It has a specific area fixed packet generating means for generating a packet for stopping the signal of the area, and at the time of special reproduction, when forming a reproduced image using intermittently reproduced data, the specific packet fixing means Since the output and the reproduction data are switched to transmit the special reproduction data of one frame in a plurality of frames, the memory capacity at the time of high-speed reproduction can be reduced.

[0037]

【Example】

Embodiment 1 FIG. FIG. 1 shows a digital V according to an embodiment of the present invention.
FIG. 2 is a block diagram of a reproduction system of a TR. In the figure, 1
9 is a rotating drum, 20a and 20b are rotating heads,
21 is a head amplifier, 22 is a signal detection circuit for detecting digital data from a reproduced signal, and 23 is a signal detection circuit 22
A digital demodulation circuit for digitally demodulating the reproduced digital data output from the digital demodulation signal; 24, an ID detection circuit for detecting an ID signal from the digital demodulated signal; 25, an error included in the digitally demodulated reproduced signal; A first error correction decoding circuit that performs error correction or error detection using a check code (error correction code in the recording direction);
Reference numeral 26 denotes a C2 check code (an error correction code added in the vertical direction of the video signal) to data that has not been corrected by the C1 check code (data in which an error has been detected or data in which an error has been missed) during normal reproduction. A second error correction decoding circuit for performing error correction or error detection using
The memory 28 performs error correction or error detection using an error correction code (hereinafter referred to as a C4 check code; details of the C4 check code will be described later) added to the special reproduction data. A third error correction decoding circuit to perform;
29 is a fourth memory, 30 is a third memory 27, or a still image packet generation circuit that generates a still image packet based on a control signal output from the fourth memory 29;
1 and 32 are switches, and 33 is a data output terminal.

Hereinafter, before describing the contents of the first embodiment, an ID signal used for a digital VTR or the like will be briefly described. The ID signal of the digital VTR described in the SD standard records additional information such as a track number and a sync block number, and an error correction detection code for correcting or detecting an error included in the ID signal during reproduction. You. This is because when information of several sync blocks is lost due to dropout during normal playback,
Immediately after dropout, it is used as an auxiliary signal for storing the correctly reproduced sync block data at a predetermined address in one error correction block shown in FIG. Also, during special playback such as high-speed playback and slow playback, it is used as a reference signal when a write address of data of the playback sync block is written to the memory 40 (the details of the memory 40 will be described later). In the first embodiment, I
It is assumed that the track number, the sync block number in the track, and an error detection code for detecting an error occurring in the ID signal during reproduction are recorded as the D signal.

FIG. 2 is a block diagram of a third error correction decoding circuit 28 according to one embodiment of the present invention. (Note that the second
The error correction decoding circuit 26 basically has the same configuration although the size of each memory is different. In the figure, reference numeral 40 denotes a memory; 41, a data update flag memory for storing an update flag of reproduced data; 42, an update flag memory control circuit for controlling the data update flag memory 41; An error correction circuit to be applied, 44 is an error correction control circuit for controlling the memory 40, the data update flag memory 41, the update flag memory control circuit 42, and the error correction circuit 43, 45 is an input terminal for reproduced data, 46
ID information output from the ID detection circuit 24, and ID
An input terminal of a signal error detection flag, 47 is an output terminal of error-corrected data, and 48 is an output terminal of an error detection flag. The details of the update flag data will be described later.

FIG. 3 is a block diagram of an error correction circuit 43 according to an embodiment of the present invention. In the figure, reference numeral 50 denotes an error correction core circuit (which is stored in the memory 40) for generating a syndrome from the data read from the memory 40 and then correcting or detecting an error in the reproduced data based on the syndrome. Error correction of data is also performed by the error correction core circuit 50.) 51 is an error correction control circuit 44.
Error correction core circuit 50 based on a control signal output from
Error correction core control circuit for generating a control signal for controlling the
52 is a forced erasure flag storage memory for storing a data update flag position output from the data update flag memory 41, and 53 is a first error correction decoder 25 for error correction decoding using a C1 check code (hereinafter referred to as C1 decoding). A C1 error detection flag storage memory 54 stores an error position detected at the time, and a C4 error detection flag storage memory 54 stores an error position detected at the time of error correction decoding (hereinafter, referred to as C4 decoding) using a C4 check code. is there.

Reference numeral 55 denotes data writing to the forced erasure flag storage memory 52, C1 error detection flag storage memory 53, and C4 error detection flag storage memory 54 based on the control signal output from the error correction core control circuit 51, and data A flag memory control circuit for generating a read control signal for reading an error, an error detection flag generation circuit for generating an error detection flag added to data in which an error has been detected, and 57 an error detection flag output from the error detection flag generation circuit 56 An error detection flag memory for storing a flag,
58 is an input terminal for a data update flag output from the data update flag memory 41, 59 is an input / output terminal for exchanging data with the memory 40, 60 is an input / output terminal for a control signal with the error correction control circuit 44, 61 is An output terminal for outputting data read from the error detection flag memory 57 at a predetermined timing based on a control signal output from the error correction core control circuit 51. The reproduced data subjected to the error correction is input from the memory 40 to the fourth memory 29 via the output terminal 47.

FIG. 4 is a diagram showing an arrangement of data in one track according to an embodiment of the present invention based on the SD standard. FIGS. 5A to 5C show a typical arrangement of the rotary heads 20a and 20b on the rotary drum 19 used in the SD mode. FIG. 6 is a diagram showing a data packet according to an embodiment of the present invention. FIG. 6 (a) shows a transport packet included in an input bit stream, and FIG. 6 (b) is recorded on a magnetic tape. 4 shows a recording data packet. FIG. 7 is a diagram showing a code configuration of an error correction code added to special reproduction data of a digital VTR according to an embodiment of the present invention. FIG. 8 is a diagram showing the number of sync blocks from which data can be acquired during high-speed playback. FIG. 9 is a diagram showing a layout of a special reproduction data recording area in a track of a digital VTR according to an embodiment of the present invention, and a diagram showing a layout of a special reproduction data recording area. FIG. 10 is a diagram showing a 16-fold speed (-1) of a digital VTR according to an embodiment of the present invention.
FIG. 9 is a diagram illustrating a method of dividing one error correction block of data (4 × speed). FIG. 11 is a diagram showing a track format of a digital VTR according to one embodiment of the present invention. Less than,
Before describing the operation of the reproducing system of the present invention, the recording format of the first embodiment will be briefly described with reference to FIGS.

At the time of recording, an input transport packet (the content is composed of a digital video signal, a digital audio signal, and furthermore, digital data related to a video signal and an audio signal, etc.) is shown in FIG.
As shown in FIG. 3A, the header is composed of a 4-byte header and a 184-byte data.

On the other hand, although the SD standard has been described in the conventional example,
As shown in FIG. 39, one sync block is composed of 90 bytes, of which the first 5 bytes record a sync pattern and an ID signal, and the last 8 bytes contain an error correction code (C1 check code). ) Is recorded. Therefore,
The data that can be stored in one sync block is 77 bytes as shown in the figure. Therefore, in the first embodiment, the transport packets are detected from the bit stream, and the two detected transport packets are
As shown in (b), the data is converted into a recording data block of 5 sync blocks and recorded. In the figure,
H1 is a first header, and H2 is a second header. H1
, Identification data indicating the order of the five sync blocks and a flag for identifying whether the data is data for special reproduction or data for normal reproduction are recorded. H2
Is recorded with identification data such as video data or audio data. As described in the conventional example, 149 sync blocks are prepared as areas for recording video data per track as shown in FIG. Three of them are VAU
An X data recording area and 11 blocks are provided as an error correction code recording area (C2 check code).

Next, the data recording area for special reproduction on the magnetic tape will be described with reference to FIGS. FIG.
Shows the number of sync blocks that can be obtained from one track at each high-speed playback speed. In the figure, the 9000 rpm system refers to the system with the head arrangement shown in FIGS. 5A and 5B, and the 4500 rpm system refers to the system with the head arrangement shown in FIG. 5C. Each value in the figure is the number of sync blocks that can be reproduced from one track at each reproduction speed when performing special reproduction using a rotating head of 10 μm (the track pitch in the SD standard is 10 μm). It is shown. The calculation was performed on the assumption that the number of sync blocks per track (corresponding to 180 degrees) was 186 sync blocks, and that a portion where the output level of the reproduced signal was higher than -6 dB was obtained as in the conventional example.

FIG. 9A shows the arrangement of the special reproduction data recording area in the track of the digital VTR according to the first embodiment in consideration of the number of sync blocks from which data can be acquired as shown in FIG. In this recording format, the data recording area for special reproduction is repeated at a cycle of 4 tracks.
A special reproduction data recording area corresponding to each multiple speed is provided on the four tracks. In addition, in the figure, a1,
And a2 are areas for recording special reproduction data for 2x speed, 4x speed and -2x speed, and b1 and b
2 is provided as an area for recording special reproduction data for 8 × speed and -6 × speed, and c1 and c2 are provided as areas for recording special reproduction data for 16 × speed and -14 × speed. I have. The ATV signal is recorded in another area (hereinafter, referred to as an ATV data recording area).

FIG. 9B shows data (the number of sync blocks) recorded in each special reproduction data recording area. It is assumed that the same signals are recorded in the areas denoted by the same reference numerals in the figure. (For example, the data of 1 in a1 is a2
It is also recorded in part 1 inside. A) and a and a
The same data is repeatedly recorded twice for the two areas, and the same data is recorded for the b1 and b2 areas.
It is recorded repeatedly. As for the c1 and c2 areas, special reproduction data (one error correction block) to which the above error correction code is added is stored as 5 bits as shown in FIG.
The data is divided into four in units of a sync block, and the upper two blocks are repeatedly recorded eight times, and then the lower two blocks are repeatedly recorded eight times. FIG. 11 shows the detailed arrangement of each special reproduction data recording area on the magnetic tape. In the figure, areas (A1, A1 ', B
1, B1 ', C1, C1', etc.), the same special reproduction data is recorded.

The operation during special reproduction will be briefly described with reference to FIG. In the case of the 9000 rpm system, 4
At double speed, 62 sync block data can be reproduced from one track, while only 4 sync blocks can reproduce 31 sync blocks. That is, in this recording format, at the time of 4 × speed reproduction,
In the 9000 rpm system, all the special reproduction data recorded on the track a1 can be reproduced (that is, all the signals 1, 2, 3, and 4 shown in FIG. 9B (ECC in the figure). Can be reproduced.) However, since about 9 sync blocks are not reproduced in the 4500 rpm system, one error correction block shown in FIG. 7 cannot be formed. (That is,
In FIG. 9B, the first few sync block data of the portion 1 and the last few sync block data of the portion 4 are not reproduced. Therefore, in the digital VTR shown in the first embodiment of the present invention, the auxiliary data used in the 4500 rpm system is recorded in the portion a2. (45
Regarding the configuration method of one error correction block at the time of special reproduction in the 00 rpm system, the rotating heads arranged adjacently
The one error correction block is constituted by using the data reproduced from 20b . Since the details are different from the gist of the present invention, they are omitted. )

Hereinafter, the recording format will be described. The bit stream of the ATV signal synthesized in sync block units as shown in FIG. 6B is recorded in the recording area of the ATV signal. On the other hand, the trick play data is an intra frame (MPE) separated from the bit stream.
It is generated from intra-frame or intra-field coded (intra-coded) data in the G2 bit stream. In the first embodiment, it is assumed that special reproduction data is generated from different intra frames at a preset multiple speed. Hereinafter, refresh times during 4 × speed playback, 8 × speed playback, and 16 × speed playback in the recording format shown in FIG. 9 (at the above playback speed, the special time using the data recorded in the special playback data recording area). When a reproduced image is composed, the minimum amount of time for updating the reproduced image) is 0.5 seconds, and the code amount of the special reproduced image that constitutes one frame at each speed is about 1.32 Mbit at 8 × reproduction, and 8 bits. Approx.
It is about 0.33 Mbit at 66 Mbit, 16 × speed, and the reproduction image quality at each double speed at the time of special reproduction can be improved as compared with the conventional example. In the following, a description will be given assuming that the above-mentioned code amount is assigned to the code amount at each double speed number.

The intra-coded data separated from the input bit stream is subjected to variable length decoding, and the data amount is reduced to the above-mentioned code amount. Each of the data whose data amount has been reduced is re-synthesized, and header information and the like are added to form the transport packet shown in FIG. Then, two transport packets are collected to form a recording data block shown in FIG. Then, three error correction blocks are formed by collecting the three recording data blocks, and after adding the C4 check code shown in FIG. 7, the C1 check code is added.

In the first embodiment, (2)
0, 15, 6). In the first embodiment, at the time of the special reproduction, one error correction block for the special reproduction shown in FIG. 7 is formed and error correction is performed on the reproduced data. Error correction code is performed), the error detection probability becomes about 1.54 × ^10-13 when the symbol error rate is 0.01,
The error detection probability is improved by about 10 ¹⁰ times, so that there is no practical problem. Further, residual errors also becomes level with no practical problem about 2.38 × 10 ^-16. As described in the conventional example, the symbol error rate is 0.0
In many cases, the number becomes 1 or more, but as far as the calculation result regarding the error rate is concerned, the above code configuration has a practically satisfactory level and a good special reproduction image can be obtained.

Based on the above, the recording format of the first embodiment will be described below. The input ATV signal bit stream is composed of two transport packets with five sync blocks as described above, and an ATV data area on the recording track in units of one sync block (see FIG. 4, hereinafter, this area). Is recorded as a main area.) It is recorded in an area other than the special reproduction data recording area.

On the other hand, the above 20 to which the error correction code is added
The double-speed special reproduction data of each sync block is recorded in the corresponding special reproduction data recording area shown in FIG. The special reproduction data corresponding to each double speed is repeatedly recorded a predetermined number of times as described above. Specifically, in the case of quadruple-speed playback data, as shown in FIG. 9B, twice (in the case of the a1 area, one error correction block is composed of the first 20 sync blocks and the second 20 sync blocks are used).
Another error correction block is constituted by the sync block. That is, the contents are different between the first half error correction block and the second half error correction block. ), Four times in the case of 8 × speed reproduction data, and in the case of 16 × speed reproduction data, as shown in FIG. 10, one error correction block is divided into the first half 10 sync blocks and the second half 10 sync blocks, and
After repeating the data of the sync block eight times, the data of the last ten sync blocks is repeatedly recorded eight times.

It should be noted that refreshing of the special reproduction data corresponding to each multiple speed is performed at a predetermined cycle as described above. (In the first embodiment, an intra image is extracted from the input bit stream every 4 seconds at 4 × speed, every 4 seconds at 8 × speed, and every 8 seconds at 16 × speed, and the image for special reproduction is updated. The cycle is not limited to this.) FIG. 11 shows a recording format according to the first embodiment.

The operation of the reproduction system of the digital VTR having the above-described recording format will be described below with reference to FIGS. First, the normal reproduction operation will be described. At the time of normal reproduction, the rotary head 20a is
The data reproduced via the amplifiers 20a and 20b is amplified by a head amplifier 21 and then detected by a signal detection circuit 22 to be converted into reproduced digital data. At this time, a synchronization signal added to the head of each sync block is detected. The reproduced digital data output from the signal detection circuit 22 is subjected to digital demodulation by a digital demodulation circuit 23. The digitally demodulated data is input to an ID detection circuit 24 and a first error correction decoding circuit 25. The ID detection circuit 24 separates the ID signal added to the head of each sync block based on the synchronization signal detected by the signal detection circuit 22, and uses the error detection code added to the ID signal. An error contained in the ID signal is detected. On the other hand, the first error correction decoding circuit 25
In, the error occurring in the reproduced signal is corrected and detected using the C1 check code added in the recording direction. The error-corrected data is input to a second error correction decoder 26 and a third error correction decoder 28.

In the second error correction decoder 26, the above C1
Error correction or error correction using C2 check code (error correction code added in the vertical direction of the video signal) to data not corrected by the check code (data in which an error is detected or data in which an error is missed) Detection is performed (hereinafter, referred to as C2 decoding). The data subjected to the C2 decoding is input to the third memory 27. Third memory 27
In, the bit stream of the ATV signal is separated from the input data, and only the bit stream is stored in the memory. (The data for special reproduction is discarded at this stage as in the conventional example.)

On the other hand, in the data input to the third error correction decoder 28, first, the special reproduction data recorded in the special reproduction data recording area is separated from the reproduction data, and the data shown in FIG. An error correction block is configured. The data recording area for special reproduction is separated by detecting the position of the data recording area for special reproduction on the track by the sync block number recorded in the ID signal in the sync block and detecting the header in the sync block. By doing so, the data for special reproduction or the normal AT
It is determined whether the bit stream is a V signal bit stream.

When the data of the one error correction block is formed, the third error correction decoder 28 outputs the data not corrected by the C1 check code (the data in which the error is detected or the data in which the error is missed). ) Is subjected to error correction or error detection using a C4 check code (an error correction code added in the vertical direction of the special reproduction data).
The data subjected to the C4 decoding is input to the fourth memory 29. The details of the operation of the third error correction decoding circuit 28 will be described when describing the operation during high-speed reproduction.

In the first embodiment, the minimum distance of the C4 check code of the special reproduction data and the minimum distance of the C3 check code of the audio data are designed to be the same. This is AT
Since the audio signal of the V signal is transmitted together with the digital video data in the bit stream of the ATV signal as described in the conventional example, it is not recorded in the audio signal area but is recorded in the video signal area together with the video signal. Will be. Therefore, the digital VT recording the ATV signal
When reproducing R, the error correction decoding circuit for the audio signal is not used. In the first embodiment,
As described above, by making the minimum distance of the C4 check code and the minimum distance of the C3 check code the same, the circuit size can be reduced by using the third error correction decoder 28 in common with the error correction decoder of the audio signal. Plan.

The fourth memory 29 stores the input error-corrected special reproduction data in the memory. During normal playback, the switch 32 is configured to always select the output of the third memory 27, and the ATV bit stream restored to 188-byte packet information in the third memory 27 is output from the output terminal 33. Is done.

Next, the still mode will be described.
Still playback includes two cases: a transition to the still mode during normal playback, and a case where the still mode is selected from the stopped state. First, a case where the mode is shifted from the normal reproduction operation to the still mode will be described. When the still mode is selected from the normal reproduction, the reproduction data is stopped and the data is not input to the third memory 27 and the fourth memory 29. Therefore, when the still mode signal is input, the third memory 27 detects the end of the frame data of the reproduction data of the ATV signal from the reproduction signal. this is,
The frame may be an intra frame or a predicted frame. When the end of the frame data is detected, the third memory 27
The end detection signal of the frame data is output to the still image packet generation circuit 30. In the first embodiment, the end of the frame data is detected by the output of the third memory 27.

When the end detection signal of the frame data is input, the still image packet generation circuit 30 generates a transport packet indicating that the image is a still image. Hereinafter, before starting a specific description, a configuration of one frame of image data defined by MPEG2 will be briefly described.

In MPEG2, 8 lines × 8 pixels DCT
The block is the minimum unit of processing at the time of high efficiency coding. Then, a plurality of DCT blocks are collected to form a macro block. A macro block is a unit for detecting a motion vector. A slice is formed by collecting a plurality of macro blocks. Also, M
In PEG2, the slice is defined to be composed of data in the same horizontal block of a macroblock, and the number of macroblocks contained therein is not limited. In addition, the macro block in the ATV signal has four DCT blocks of the luminance signal (16 lines × 16).
Pixel) and one DCT block (8 lines × 8 pixels) of two color difference signals at the same position on the screen. In the ATV signal, the image data is 4: 2: 0.
Is sent in the form of (Refer to the MPEG2 standard for details)

In consideration of the above, the contents of the transport packet output from the still picture packet generation circuit 30 and indicating the still picture will be described. More specifically, in the first embodiment, the data in the macroblock is a plurality of transport packets in which the motion vector is 0 and the prediction error signal is 0, and slice data is generated. Generate a transport packet that collects multiple slices. (Hereinafter, this transport packet is referred to as a still image packet.) In the still image packet generation circuit 30, the ATV
A packet indicating no data is generated together with the still image packet so that the frame cycle in the decoder matches, and a transport packet is generated by combining these two packets so that the frame cycle in the ATV decoder matches.

In the first embodiment, as one embodiment, the motion vectors of all the macroblocks belonging to the slice are 0, and the data in all the DCT blocks in the macroblock are all 0 (that is, the DC data is 0). so,
AC data is composed of only EOB (end of block). ) Indicates a transport packet composed of one or more slices. The no-data packet is a transport packet defined by the bit stream of the ATV signal, and the packet information means a packet having no meaning as transmission information. In addition,
If the no data packet is defined in the transport header portion, the data in the subsequent transport packet is ignored during decoding by the ATV decoder. That is, in the still picture packet generation circuit 30, the data portion in the transport packet always generates the above-mentioned information of the still picture packet, and the switching of the output is added to a predetermined position of the transport header and the no data packet transmitted. A header part for determining whether or not the data is switched is generated. As a result, the circuit size of the still image packet generation circuit 30 can be reduced.

The switch 31 selects the output of the still picture packet generation circuit 30 when the still mode signal is input. Further, the switch 32 controls the output of the switch 31 to be selected based on the end signal of the frame data of the ATV signal output from the third memory 27. In the first embodiment, the end of the frame data is detected from the output data of the third memory 27. However, the present invention is not limited to this.
The same effect can be obtained even if the still image packet generation circuit 30 and the switch 32 are controlled with a predetermined delay. Needless to say, the data switching timing may be switched at the position where the last packet of the intra frame is detected. (Constructing a still image with intra frames is effective because the quality of a reproduced image is slightly better than composing with inter frame data.)

Next, a case where the still mode is selected from the stop state will be described. In the stopped state, since correct data is not transmitted to the ATV receiver (decoder) side, if the still mode is selected in this state, the data is reproduced once and one screen worth of data is transferred to the ATV receiver side. After that, the switches 31, 32 and the rest control the packet generation circuit 30 and stop the tape in the above-described manner. In this case, the third memory 27 detects the end position of the data of the intra frame and performs control to output the end signal of the frame data. This is because even if an inter-frame end signal is detected, a reproduced image cannot be formed because only a motion vector and a prediction error component are transmitted.

In the first embodiment, the ATV signal used in the normal reproduction is used as the still reproduction data. However, the present invention is not limited to this, and the special reproduction data stored in the fourth memory 29 may be used. Similar effects can be obtained by performing similar control. (When the still mode signal is input, the switch 32 selects the output of the switch 31. On the other hand, the switch 31 detects the end of the frame data output from the fourth memory 29, Output is selected.) Particularly, when an error is detected in the ATV signal used for normal reproduction, good still reproduction can be realized by using the special reproduction data. In the first embodiment, the data of the transport packet reproduced from the special reproduction data recording area used in the double speed, the quadruple speed, and the -2 speed reproduction having the largest recording data amount during the still reproduction is output. Shall be configured. (Thus, at the time of normal reproduction, it is sufficient to decode the data used at the time of still reproduction. Therefore, the third error correction decoding circuit 28 performs the above-described double speed, quadruple speed, and −2
It may be configured to decode only the data recording area for special reproduction used at the time of double speed reproduction. With the above configuration, A
Still playback can be realized with a simple circuit configuration without letting the TV decoder recognize the still playback mode.
When an error is detected in the reproduction signal, good still reproduction can be realized by using the data recorded in the special reproduction data recording area. With the above configuration, in the first embodiment, the memory capacity of the third memory 27 can be reduced to about 4 tracks × 2.
(In the past, a memory capacity for one frame of an intra frame was required.)

Next, the operation during high-speed reproduction will be described. In the first embodiment, the case of the configuration of the rotary head shown in FIG. FIG. 12 is a scanning trajectory diagram of the rotary head 20a at the time of reproducing at 2, 4, 8, and 16 times speed according to an embodiment of the present invention. FIG.
The scanning locus of the rotary head 20a shown in FIG. 2 takes the same locus even in the configuration of the rotary head shown in FIG. (However,
The rotary head 20b has a completely different trajectory because the head arrangement is different. FIG. 13 is an operation explanatory diagram for explaining the tracking control operation of the digital VTR according to one embodiment of the present invention. First, a tracking control method at the time of high-speed reproduction in the first embodiment will be described with reference to FIG.
This will be described with reference to FIG. During high-speed reproduction, data is intermittently reproduced as described above. FIG. 8 shows the number of sync blocks that can be reproduced from one track at each reproduction speed.

Therefore, in order to effectively acquire the special reproduction data, the tracking of the rotary head 20a is performed so that the reproduction output becomes maximum at the center of the area where the special reproduction data is recorded at each multiple speed. May be controlled. FIGS. 13A to 13C show tracking control points of the rotary head 20a at each reproduction speed. In the recording format shown in the first embodiment, 9000 r
In the pm system, the data of one error correction block shown in FIG. 7 can be formed without using the data reproduced from the rotary head 20b . Therefore, the scanning locus of the rotary head 20b is omitted in FIG.

Based on the above, the operation of the reproduction system at the time of high-speed reproduction will be described with reference to FIGS. 1 to 3, FIG. 12, and FIG. When a high-speed reproduction mode signal is input, the switch 32 selects the output of the switch 31. (Detailed timing of switch switching will be described later.) Reproduced data reproduced intermittently via the rotary heads 20a and 20b is amplified by a head amplifier 21 and then converted into reproduced digital data by a signal detection circuit 22. It is converted and digitally demodulated by the digital demodulation circuit 23. The data in which the synchronization signal is correctly detected by the signal detection circuit 22 is input to the ID detection circuit 24 and the first error correction decoding circuit 25. The ID detection circuit 24 separates the ID signal added to the head of each sync block based on the synchronization signal detected by the signal detection circuit 22, and uses the error detection code added in the ID signal. To detect an error contained in the ID signal.

On the other hand, in the first error correction decoding circuit 25,
Using the C1 check code added in the recording direction, an error occurring in the reproduced signal is corrected and detected.
(C1 decoding) The error-corrected data is input to the third error correction decoder 28. Note that the output of the first error correction decoding circuit 25 is also input to the second error correction decoding circuit 26. However, since data is intermittently reproduced as described above, C2 decoding cannot be performed. In the first embodiment, it is assumed that the C2 decoding operation is not performed during high-speed reproduction because a packet cannot be generated. Hereinafter, the third
Before describing the operation of the error correction decoding circuit 28, a general error correction decoding algorithm of the product code type error correction code shown in FIG. 7 or FIG. 38 will be briefly described. FIG.
FIG. 3 is a diagram for explaining a general C1 decoding algorithm used for a digital VTR. FIG. 15 shows a digital VT
FIG. 9 is a diagram for explaining a general C4 decoding algorithm used for R. In general, C2 decoding and C3 decoding algorithms also differ only in minimum distance or code length as shown in FIG.
5 is decoded by the same algorithm as the C4 decoding algorithm shown in FIG.

When the data is reproduced, first, an error generated in the reproduced signal is corrected to the limit of the error correction capability of the C1 check code using the C1 check code. FIG. 14 shows C
1 shows an algorithm for decoding. First, when C1 decoding is started, a syndrome is generated using data output from the digital demodulation circuit 23. When the generation of the syndrome ends, the error position and the numerical value are calculated using the generated syndrome. As a result of calculating the error position and the numerical value, if the number of errors is four or less, error correction is performed, and if it is determined that the number of errors is four or more, an error detection flag is output. (Hereinafter, the error detection flag is referred to as an erasure flag.) In the first embodiment, since the minimum distance of the C1 check code is 9, up to four errors are corrected.

An error for which error correction could not be performed with the C1 check code is corrected using the C4 check code. The error correction using the C4 check code according to the first embodiment is based on erasure correction (hereinafter, referred to as “error correction”) for errors detected by the C1 check code.
This is referred to as erasure correction. ), And also corrects errors that are missed by the C1 check code.
Hereinafter, C4 decoding will be described based on the decoding algorithm shown in FIG.

When the data of one error correction block shown in FIG. 7 is constructed in the memory 40, first, a syndrome is generated using the input data, and at the same time, the syndrome is generated based on the erasure flag detected by the C1 check code. The number of erasures is counted. If the number of erasures is equal to or less than the correction capability of the C4 check code (the minimum distance of the C4 check code of the conventional example is 6, so that up to five erasures can be corrected), the above-described syndrome is also used. At the same time, an erasure correction is performed on the error detected by the C1 check code in order to obtain the corrected syndrome. (Because the method of erasure correction differs depending on the decoding algorithm,
When using an algorithm other than Euclidean decoding,
It is assumed that erasure correction is performed by another method based on the syndrome and the erasure position without obtaining the corrected syndrome. At this time, error correction is performed up to the limit of error correction capability even for an overlooked error due to the C1 check code. On the other hand, if the number of erasures detected by the C1 check code exceeds the correction capability, the error correction is not performed and the error correction is performed without any change until the limit of the error correction capability of the C4 check code (up to two errors can be corrected). Do.) Do. This is because an error detected by the C1 check code is likely to be an empty erasure (when an error is detected by the C1 check code but is actually an accurate value), so that error correction can be performed.

The problem when error correction and detection are performed by using the above-described decoding algorithms shown in FIGS. 14 and 15 will be described by taking as an example a case of high-speed reproduction in which the problem becomes particularly noticeable. As shown in FIG. 34, during high-speed playback, the playback data is played back intermittently. First, the reproduced data is subjected to C1 decoding by the first error correction decoding circuit 25 according to the decoding algorithm shown in FIG.

On the other hand, the ID detection circuit 24 detects the ID signal based on the detection result of the synchronization signal output from the signal detection circuit 22 and uses the error detection code added to the ID signal to detect the error in the ID signal. Is detected. Then, the special reproduction data is separated using the detected ID signal to form one error correction block shown in FIG.
Specifically, the write address to the memory 40 is
It is generated based on the track number and the sync block (C1 block) number added to the signal.

In general, when performing error correction on data to which an error correction code is added in two or more different directions including the recording direction as shown in FIG. 7, when performing error correction in a direction different from the recording direction, After temporarily storing the data of one error correction block in a storage element such as a memory, it is necessary to perform error correction by changing the data reading direction. that time,
When an error is detected in the ID signal, the data of the C1 block (hereinafter, one sync block is referred to as a C1 block in the description of error correction) is transmitted to the third error correction decoding circuit 2.
No data is written to the memory 40 in the block 8. this is,
When one error correction block is formed by combining intermittently reproduced data, continuity of the ID signal is not guaranteed unlike normal reproduction. Further, in the case where the data of the C1 block in which an error is detected in the ID signal is generated by estimating an address using ID data of the previous C1 block, for example, it is determined that there is no ID error in the previous scanning period. This is because data written in the memory 40 may be overwritten and erroneous data may be written in the memory 40.

In the above manner, one error correction block shown in FIG. 7 configured in the memory 40 is subjected to C4 decoding based on the decoding algorithm shown in FIG. An error detection flag detected by the C4 or C1 check code is added to data corrected and detected by the C4 check code, and an effective digital video signal excluding the error correction code is read from the memory 40.

At the time of high-speed reproduction, since writing to the memory 40 is controlled as described above, data detected by the error detection code in the ID signal is not written to the memory 40. Therefore, when configuring one error correction block, an error is detected in the ID signal, and a C1 block that is not written in the memory 40 occurs. At this time, the address where the C1 block is stored in the memory 40 stores error-corrected data that has been rewritten last time or two times before. When performing error correction on this error correction block, the data of the C1 block is not updated, and as a result of performing the error correction using the C1 check code despite that all the data in the C1 block are erroneous, It is determined that there is none. This occurs because the error detection flag by the C1 code has been reset. Even if the C1 block data stored in the memory 40 and not rewritten is subjected to the C1 decoding again,
Alternatively, the error cannot be detected because the error was corrected at the time of the last error correction. The data of the C1 block is used for error correction by the C4 check code.
An overlook error is caused by one check code. (Especially, memory 4
0, the data of the C1 block is written based on the ID information.
When performing control such that one decoding is performed, this phenomenon appears remarkably. )

As described above, in the case where error correction using the C4 check code is performed in a state including an overlook error due to the C1 check code, not only the error correction capability using the C4 check code cannot be maximized, but also the overlook error due to the C4 decoding ( (Including erroneous corrections)), and the effect on reproduced image quality is also great. In particular, a home digital VT as described above
In the case of R, during recording, the video signal has been subjected to high-efficiency encoding, so that a missing error of one symbol causes
It propagates to the data of the T block and degrades the image quality.
Therefore, it is necessary to reliably correct or detect errors in the reproduced data.

In consideration of the above, the decoding algorithm of the error correction code according to the first embodiment is shown in FIG. 16 and FIG. FIG. 16 shows an algorithm for setting the data update flag according to the first embodiment. FIG. 17 shows an error correction decoding (C4 decoding) algorithm using an error correction code in a direction different from the recording direction of the first embodiment (vertical direction in the first embodiment). Note that the C1 decoding algorithm is the same as that shown in FIG.

Hereinafter, the error correction decoding algorithm according to the first embodiment will be described with reference to FIG. 16 and FIG. First, the algorithm of the data update flag according to the first embodiment will be described with reference to FIG. First, the ID signal is separated from the data of the C1 block reproduced intermittently from the rotary head 20 . The separated ID signal is subjected to error detection using an error detection code added in advance at the time of recording. As a result of the error detection, the data of the C1 block determined to have no error in the ID signal is subjected to C1 decoding by the first error correction decoding circuit 25, and then to the track number and line number separated from the ID signal. The special reproduction data area is separated based on the data and written to a predetermined address in the memory 40. When writing the data of the C1 block to the memory 40, the data update flag is written to a predetermined address (an address separated from the ID signal) of the data update flag memory 41. In the first embodiment, “0” is used as the data update information for the updated C1 block.
To the data update flag memory 41 (see FIG. 16). When the decoding of one error correction block is completed (C1 decoding and C4 decoding), the data update flag memory 41 resets the data update information in the memory, and all data becomes unupdated information. (Ie, all “1”
Is written into the memory. )

The data of the C1 block determined by the ID detection circuit 24 to have no error in the ID signal is subjected to C1 decoding by the first error correction decoding circuit 25 based on the C1 decoding algorithm shown in FIG. (Since the C1 decoding operation is the same as the above operation, the description is omitted.)
The data subjected to C1 decoding is output to a third error correction decoding circuit 2
8 is input. In the third error correction decoding circuit 28, ID
Based on the error detection result of the ID signal output from the detection circuit 24, the writing of the data of the C1 block to the memory 40 is controlled. Hereinafter, a control method of the memory 40 and the data update flag memory 41 will be briefly described.
The ID signal detected by the ID detection circuit 24 and the error detection result are input to the error correction control circuit 44. For the data of the C1 block in which no error is detected in the ID signal, the error correction control circuit 44 uses the memory 40 and the data based on the track number information and the sync block number information added to the ID signal. The write control signal and the write timing signal of the data of the C1 block and the data update flag to the update flag memory 41 are generated. (Note that the control signal of the data update flag memory 41 is generated by the update flag memory control circuit 42 based on the write timing signal generated by the error correction control circuit 44 and the ID information.) , A write control generated by the error correction control circuit 44 using the information detected from the ID signal.
The data of the C1 block is written to a predetermined address in the memory 40 according to the control signal . Similarly, a data update flag (“0” as described above) is stored in the data update flag memory 41. The error detection flag detected at the time of C1 decoding is also stored at a predetermined address in the C1 error detection flag storage memory 53 described later.

On the other hand, C1 in which an error is detected in the ID signal
The data of the block is discarded without being written in the memory 40. Therefore, no flags are set in the data update flag memory 41 and the C1 error detection flag storage memory 53. The detection data of the result errors C1 decoding, it stores on the basis of the ID information error detection flag at a predetermined address of C1 in an error detection flag storage memory 53 in the error correction circuit 43. In the first embodiment, data in which an error at the time of C1 decoding is detected is also written in the memory 40.

When the data of one error correction block subjected to C1 decoding is combined in the memory 40 in the manner described above, the error correction control circuit 44 outputs a data update flag reading start signal to the update flag memory control circuit 42. I do. Less than,
The update flag memory control circuit 42 sequentially reads data from the first data of the data update flag memory 41 when the data update flag read control signal is input. The data update flag read from the data update flag memory 41 is stored in the forced erasure flag storage memory 52. At that time, the number of unupdated flags (the number of forced erasure flags) is counted. In addition,
The number of error detection flags by the C1 check code is also counted at the time of C1 decoding. Hereinafter, in order to distinguish the unupdated flag information of the C1 block from an erasure flag indicating an error detected by the C1 check code, the unupdated flag information is referred to as a forced erasure flag for convenience.

FIG. 18 is an operation explanatory diagram for explaining a C4 decoding algorithm of a digital VTR according to one embodiment of the present invention.
8 will be described as an example. FIG.
In the cases shown in FIGS. 8 (b) and 8 (c), errors detected in C1 decoding are 2 blocks, and forced erasures are 3 blocks, so that a total of 5 blocks are counted as the number of erasure flags. When the error detection flag is set in the C1 block in which the forced erasure flag is set, the number of erasures is counted assuming that an error is detected in one C1 block.

Next, the number of erasure flags is set to a predetermined number n.
(N = 6 in the first embodiment) and n or more (in the first embodiment, erasure correction in C4 decoding is performed up to the limit of the error correction capability of the C4 check code, as in the conventional example. The erasure correction is performed up to 5 erasures.) Then, the number of forced erasures is compared with a predetermined number R (R = 6 in the first embodiment). When the number is equal to or larger than R, the error correction operation is terminated without performing C4 decoding.

Since all data in the C1 block where the forced erasure flag is set are erroneous as described above, even if error correction is performed ignoring the erasure flag during C4 decoding as shown in FIG. Error correction cannot be performed for the number of forced erasures equal to or greater than the error correction capability of the check code (up to two errors can be corrected). Further, when error correction is forcibly performed using the C4 check code, an error detection flag is added to all blocks, so that even data that has been error corrected by C1 decoding is output as an error. And the probability of erroneous correction increases. Therefore, in the first embodiment, when the number of forced erasures is R or more, the error correction operation is forcibly terminated.

On the other hand, when the number of forced erasure flags is less than R (the number of erasure flags is n or more), C4 decoding is performed according to the algorithm shown in FIG. (In the first embodiment, as shown in FIG. 17, the forced erasure performs error correction as erasure.) Similarly, when the number of erasures is less than n, error correction using the C4 check code is performed as shown in FIG. The details of the error correction using the C4 check code will be described later.

When the C4 decoding of one error correction block is completed, the update flag memory control circuit 42 resets the data update flag in the data update flag memory 41.
Specifically, "1" is written to a predetermined address in the data update flag memory 41. After the reset of the data update flag memory 41, an error detection flag is generated using an error detection flag using a C1 check code, an error detection flag using a C4 check code, and a forced erasure flag.
The error correction operation of one error correction block ends. In addition,
The reset timing of the data update flag memory 41 and the timing of setting the error detection flag are not limited to the above-described timings. Further, the C4 error detection flag storage memory 54, C1
The error detection flag storage memory 53 and the forced erasure flag storage memory 52 are reset after the error detection flag is set.

Based on the above, FIG. 16 and FIG.
The operation of the reproduction system at the time of high-speed reproduction using the decoding algorithm shown in FIG. 7 will be described with reference to FIGS. 1 to 3, 16 and 17. As described above, when the high-speed reproduction mode signal is input, the switch 32 selects the output of the switch 31. Reproduced data reproduced intermittently via the rotary heads 20a and 20b is amplified by a head amplifier 21 and then converted into reproduced digital data by a signal detection circuit 22 and digitally demodulated by a digital demodulation circuit 23. . The signal detection circuit 22 also detects a synchronization signal. The data in which the synchronization signal is correctly detected by the signal detection circuit 22 is input to the ID detection circuit 24 and the first error correction decoding circuit 25. The ID detection circuit 24 separates the ID signal from the reproduction signal using the synchronization signal,
An error included in the ID signal is detected using the error detection code added to the D signal.

On the other hand, in the first error correction decoding circuit 25,
ID error information (ID
C1 decoding is performed based on whether there is an error in the signal). In the first embodiment, at the time of high-speed reproduction, C1 where an ID error is detected
It is assumed that C1 decoding is not performed on data of a block (C1 block in which an error is detected in the ID signal). (In the first embodiment, C1 decoding is not performed on the data of the C1 block in which an ID error is detected during high-speed reproduction. This is reproduced because data is reproduced across a plurality of tracks during high-speed reproduction. There is a possibility that the cycle of the C1 block becomes discontinuous at the time of the track jump and the control is broken, so to prevent this, the C1 decoding is stopped for the data of the C1 block where the ID error is detected. It is needless to say that if a protection circuit for preventing the error is added, the block in which the ID error is detected may be subjected to the C1 decoding.) The data of the C1 block in which the ID error is not detected is shown in FIG.
C1 decoding is performed based on the decoding algorithm shown in FIG. The data subjected to the C1 decoding is input to the third error correction decoder 28. As described above, C2 decoding is not performed during high-speed playback.

Next, writing of the data of the C1 block subjected to C1 decoding into the memory 40 and writing of the data update flag 41 of the data update flag in FIG.
This will be described briefly using FIG. In the ID data detection circuit 24, I
The data of the C1 block where the D error is detected is not written to the memory 40 as described above. Therefore, the memory 40 and the data update flag memory 41 are in a standby state until the next synchronization signal is detected.

On the other hand, if the ID data detection circuit 24 determines that there is no ID error, the update flag memory control circuit 42
Then, the data update flag is set at a predetermined address of the data update flag memory 41 based on the ID signal (track number and C1 block number). (In the first embodiment, “0” is written to the data update flag memory 41.) At the same time, the error correction control circuit 44
A write address to the memory 40 is generated based on the D signal, and the data of the C1 block subjected to the C1 decoding is stored in the memory 4.
Write to a predetermined address within 0. The above operation is shown in FIG.
Is repeated until the data of one error correction block shown in (1) can be combined. The error detected at the time of C1 decoding is written to a predetermined address in the C1 error detection flag storage memory 53 indicated by the ID information. At that time, the number of error detection flags by the C1 code is counted in the error correction circuit 43.

When the data of one error correction block shown in FIG. 7 is constructed in the memory 40, first, the data update flag is read out from the data update flag memory 41 as described above and stored in the forced erasure flag storage memory 52. Is done. At this time, the number of forced erasure flags is counted. When the reading of the data update flag is completed, the error correction core circuit 50 sets the number of forced erasure flags and C1
The number of error detection flags is added to determine the number of erasures.

The error correction core control circuit 51 determines a decoding algorithm for C4 decoding according to the number of erasures. The C4 decoding algorithm will be described with reference to FIG.
When the number of erasure flags is input, the error correction core control circuit 51 sets the number of erasure flags to a predetermined number n.
(N = 6). If the number of erasure flags is less than n (in the first embodiment, C4
Erasure correction in decoding is performed up to the limit of the error correction capability of the C4 check code, and erasure correction is performed up to five erasures. 2) Erasure correction is performed using the forced erasure flag and the C1 error detection flag as erasures. At this time, an overlooked error at the time of C1 decoding is performed to the limit of the error correction capability of the C4 check code.

Next, when the number of erasure flags is n or more, the number of forced erasures is compared with a predetermined number R (R = 6 in the first embodiment). I do.

On the other hand, when the number of forced erasure flags is less than R (the number of erasure flags is n or more), the number of forced erasures is again compared with a predetermined number P (P = 4). And performs erasure correction. At this time, error correction is not performed for an overlooked error at the time of C1 decoding. On the other hand, if the number of forced erasures is less than P, erasure correction is performed using only the forced erasure flag as an erasure. in this case,
Even for an overlooked error at the time of C1 decoding, error correction is performed up to the limit of the error correction capability of the C4 check code.

On the other hand, the error correction core control circuit 51 outputs a data request signal to the error correction control circuit 44 when the calculation of the number of erasures is completed. Error correction control circuit 44
Is input to the memory 40 when the data request signal is input.
And a control signal are generated. First, a syndrome is generated from the data read from the memory 40 by the error correction core circuit 50.
When the generation of the syndrome is completed, a corrected syndrome is generated based on the decoding algorithm, and an error position and a numerical value are calculated. When the calculation of the error position and the numerical value is completed, the error correction core circuit 50 outputs the calculation result of the error position to the error correction core control circuit 51. In the first embodiment, the case where decoding is performed using the Euclidean algorithm is considered. Therefore, the correction syndrome is obtained at the time of erasure correction. However, in the case of another algorithm, the correction syndrome is not generated, and the correction syndrome is not generated. Erasure correction is performed according to the erasure position.

When the calculation result of the error position is inputted, the error correction core control circuit 51 transmits the error position data together with the error data read request signal to the error correction control circuit 44.
Output to The error correction control circuit 44 reads out the erroneous data stored at the address indicated by the error position data from the memory 40. The error correction core circuit 50 performs error correction by adding the error value to the erroneous data read from the memory 40. The error-corrected data is rewritten to a predetermined address in the memory 40 indicating the error position. The above operation is repeated for the number of detected errors. On the other hand, for data in which an error has been detected in C4 decoding, flag data is written to a predetermined address in the C4 error detection flag storage memory 54. The above operation is repeated for one error correction block.

When the C4 decoding of one error correction block is completed, the update flag memory control circuit 42 resets the data update flag memory 41 as described above. After the reset of the data update flag memory 41, the error detection flag is generated by the error detection flag generation circuit 56 using the error detection flag using the C1 check code, the error detection flag using the C4 check code, and the forced erasure flag. The flag is stored at a predetermined address of the error detection flag memory 57, and the error correction operation of one error correction block is completed.

The data corrected by the third error correction decoding circuit 28 in the above manner is read out from the memory 40 together with the detected error detection flag and stored in the fourth memory 29. The fourth memory 29 outputs a data output request signal to the still image packet generation circuit 30 when all of the special reproduction data of one frame is reproduced.

In the first embodiment, at the time of high-speed reproduction, when the one-frame special reproduction data (intra-coded) is reproduced, it is output from the fourth memory 29, and the next one-frame special reproduction data is output. Until the reproduction data is reproduced, the still picture packet generation circuit 3 freezes (stills) the screen on the ATV decoder side in the same manner as the still reproduction.
0 generates a still picture packet and a no data packet. With the above control, the ATV decoder can decode data without being aware of the high-speed reproduction mode, as in the case of still reproduction. Hereinafter, the data control method at the time of high-speed reproduction will be described focusing on the operation of the still image packet generation circuit 30.

When the data output request signal is input from the fourth memory 29, the still picture packet generation circuit 30 checks the status of the still picture packet that is currently occurring. Hereinafter, FIG.
The operation will be described with reference to FIG. FIG. 19 is a timing chart of special reproduction of a digital VTR according to one embodiment of the present invention. In the figure, (a) shows an input signal of the fourth memory 29 (it is actually reproduced intermittently),
(B) is a data output request signal output from the fourth memory 29, (c) is a data read start signal output from the still image packet generation circuit 30, and (d) is a switch 31.
(E) is an output signal of the fourth memory 29, and (f) is an output signal of the still image packet generation circuit 30.

First, the still picture packet generation circuit 30
, The fourth memory 29 is in a standby state until the output of one frame of packets is completed (see point A in the figure). When the last packet of one frame of the still image packet being output is output, the still image packet generation circuit 30 outputs a data reading start signal to the fourth memory 29. If the no data packet has been generated, the data read start signal is output after the output of the currently generated packet is completed (see point B in the figure). In the fourth memory 29, when the data read start signal is input, data packets for special reproduction are sequentially read from the memory.

On the other hand, the data read start signal is also supplied to the switch 31 so that the switch 31
The connection is switched so as to select the output of. In addition,
In the figure, the switching signal of the switch 31 is "H" to select the output of the fourth memory 29, and "L" is to select the output of the still picture packet generation circuit 30. When the still picture packet is generated by the still picture packet generating circuit 30 as described above, the output of the fourth memory 29 is in the standby state because the inter-frame data is interrupted by the ATV decoder and the intra This is because a malfunction may occur when frame data is input, and it is necessary to manage reproduced frames to avoid this.

When the last packet of the special reproduction data is detected from the output of the fourth memory 29, the fourth memory 2
In step 9, a special reproduction data output completion signal is supplied to the still image packet generation circuit 30 and the switch 31. When the above signal is input, the switch 31 switches the output to the output of the still image packet generation circuit 30. On the other hand, the still image packet generation circuit 30 switches packets to be output according to the code amount up to the present. More specifically, if the amount of data (the number of frames) transmitted to the ATV decoder is too large and the memory in the ATV decoder is likely to overflow, a no-data packet is output to control the code amount. Conversely, if the amount is too small (underflow) or just right, the still image packet is output. The still picture packet is output in units of one frame, and the no-data packet is inserted between the still picture packets to control the code amount of the ATV bit stream (the memory in the ATV decoder overflows or underflows as described above). The number of output frames is controlled so as not to cause the occurrence.). In the first embodiment, the count of the data amount (the number of frames) is counted at the output stage of the switch 32, and the count result is output to the still image packet generation circuit 30. Further, the data amount is obtained by counting the number of frame data transmitted and not yet decoded and the code amount thereof. In addition, for simplicity, the number of the frame data which has not been decoded may be used.

As described above, by controlling the fourth memory 29, the still picture packet generation circuit 30, the switch 31, and the switch 32, the ATV decoder can form a reproduced image without considering the high-speed reproduction mode. And a good high-speed reproduced image can be generated. In addition, by adopting a combination of the above-mentioned still image packet and no data packet, it is possible to prevent overflow and underflow of the memory in the ATV decoder, thereby making it possible to form a good special reproduction image.

The operation of the still picture packet generation circuit 30 at the time of mode transition will be described below. Still image packet generation circuit 3
At 0, when the special reproduction mode signal is input, the generation of the still image packet (a still image packet having a motion vector of 0 and a prediction error of 0) and a no data packet is started. On the other hand, in the third memory 27, the currently output ATV
Detect the last packet of frame data in the bit stream. When the last packet of the frame data is detected, the last packet detection signal is supplied to the still picture packet generation circuit 30 and the switch 32. The switch 32 controls to select the output of the switch 31 when the signal is input.

When the final packet detection signal is input, the still picture packet generation circuit 30 first generates a still picture packet for one frame, and then generates a no data packet. The still image packet generation circuit 30 generates no data packets to prevent the memory in the ATV decoder from overflowing or underflowing. In the first embodiment, the number of inserted no-data packets is controlled in accordance with the output result of the data amount obtained by counting the data amount at the output stage of the switch 32.

FIG. 20 is a timing chart showing a transition from normal reproduction to special reproduction of a digital VTR according to one embodiment of the present invention. In the figure, (a) is an output of the third memory 27, (b) is a special reproduction mode signal, (c) is a frame last packet detection signal, and (d) is a switch 32.
(E) is a still image packet generation circuit 30
The output data of FIG. As shown in the figure, the still image packet is output from the still image packet generation circuit 30 following the last packet of the data frame output from the third memory 27. In the first embodiment, it is assumed that the change of the tape feed or the like is performed at the same timing as the switching signal of the switch 32.

By the above operation, control can be performed even when the mode shifts to the special reproduction mode, without making the ATV decoder aware of the state after the mode. Further, by this operation, the still image packet is generated and output at the time of the mode transition to the special reproduction, so that the reproduction screen at the time of the mode transition becomes a still image and the mode transition can be smoothly performed without disturbing the screen. In particular, a digital VTR that records the ATV signal is a conventional analog recording VT.
Unlike the R, even if the data reproduced at the time of mode transition is used, the ATV signal is composed of the bit stream of the intra frame and the inter frame as described above. Since a reproduced image cannot be formed, the above-described control is very effective.

The switch 31 selects the output of the still picture packet generation circuit 30 when the special reproduction mode signal is input. Although not shown, the switching of the switch 31 is controlled so as to select the output of the still picture packet generation circuit 30 until the tape playback system (servo system) is locked (steady state) by shifting to the special reproduction mode. . When the tape running system enters a steady state and the special reproduction data for one frame is synthesized in the fourth memory 29, a data output request signal is output from the fourth memory 29 as described above. The subsequent control of the still image packet generation circuit 30, the switch 31, the switch 32, and the fourth memory 29 is the same as that described at the time of the high-speed reproduction, and thus the description is omitted. (See FIG. 19)

Next, a control method for shifting from the special reproduction mode to the normal reproduction mode will be described. When shifting from the special reproduction mode to the normal reproduction mode, when the normal reproduction mode signal is input, the fourth memory 29 checks the current data output state. If the data packet for the special reproduction is currently being read from the fourth memory 29, a data output completion signal is output to the still image packet generation circuit 30 after reading one frame of data, and 4 stops writing data to the memory 29. At the same time, a normal reproduction mode start signal is output to the tape traveling system (servo system). When the data read completion signal is input, the still image packet generation circuit 30 generates and outputs a still image packet and a no data packet so that the memory on the ATV decoder side does not overflow or underflow as described above. Is done. The switching control signal for the switch 31 is also output at the above timing. (See Fig. 19A point)

If the data packet for the special reproduction is not read out from the fourth memory 29, the fourth memory 29 stops writing the data and sends the data to the tape traveling system (servo system). Outputs a playback mode start signal. The still image packet generation circuit 30 generates and outputs a still image packet and a no data packet so that the memory of the ATV decoder does not overflow or underflow as described above, and the switch 31 operates the still image packet generation circuit. Thirty outputs are selected. (Refer to Fig. 17B point)

In the tape running system (servo system), the fourth
When the normal reproduction mode start signal is input from the memory 29 of the above, the mode shifts to the normal reproduction mode. Then, when the tape running system enters a steady state, the fact that normal reproduction has been performed is output to the third memory 27 and the fourth memory 29. At the time of normal reproduction, the third memory 27 writes the reproduced ATV data for normal reproduction in the memory. Similarly, in the fourth memory 29, data for special reproduction is written into the fourth memory 29 again.

ATV written in third memory 27
After the trick play data is removed from the memory, an ATV transport packet is formed and output. Then, in the subsequent stage of the third memory 27, the switch 32 selects the output of the switch 31 until the first packet of the intra frame is detected first. When the head of the intra frame is detected at the output end of the third memory 27, the detection result is supplied to the switch 32. The switch 32 selects the output of the third memory 27 when the above signal is input. With the above control, it is possible to smoothly perform the mode transition without disturbing the reproduced image at the transition from the normal reproduction to each mode signal or at the transition from the special reproduction mode to the normal reproduction mode, and obtain a good reproduction image quality. With respect to the ATV decoder, a reproduced image can be formed without being aware of the mode transition.

The output of the switch 32 is output to the ATV decoder. At the time of high-speed reproduction, the digital VTR is controlled as described above, so that the ATV decoder can form a special reproduction image by the same control as normal reproduction without being conscious of the reproduction mode of the digital VTR. The memory capacity of the fourth memory 29, which is sometimes used, can be reduced. This is because the fourth memory 29 does not need to repeatedly read the same data in the memory a plurality of times by the above control as shown in FIG. This indicates that the memory is open after the data has been read once. Therefore, high-speed reproduction can be realized only by adding a buffer memory before the fourth memory 29. If the above control is not performed, it is necessary to repeatedly read out the reproduced special reproduction data until the next special reproduction data is reproduced, which requires at least two frames of special reproduction memory and reduces the memory capacity. However, according to the configuration of the first embodiment, as described above, the special reproduction can be realized with the memory for one frame, and the memory capacity can be reduced to almost half.

In the first embodiment, one frame of data is temporarily stored in the fourth memory 29 and then output. However, the present invention is not limited to this. For example, as shown in FIG. The data written in the fourth memory 29 is read out, the no data packet is output as a packet between slices in the same frame, and the still image packet and the no data packet are switched and output between frames. Has the same effect. In addition,
FIG. 21 shows a case where data obtained by dividing one frame into a plurality of slices is collected into a plurality of slices n times (a special reproduction image of one frame is divided into n blocks in units of slices).
And the case of outputting to the ATV decoder. In addition,
n is an integer of 2 or more. Also, the number of slices included in the n blocks need not be the same. With the above configuration, the memory capacity of the fourth memory 29 can be reduced.

Further, in the first embodiment, the still picture packet and the no data packet are previously combined in the still picture packet generation circuit 30 so as not to cause overflow and underflow to the ATV decoder, and the code amount and the number of frames are controlled. However, the present invention is not limited to this. In particular, a packet indicating a mode other than the video signal, for example, a packet to which header information indicating an audio signal is added may be inserted for a no data packet. In this case, since audio is muted by the ATV decoder, when a packet is generated and output as predetermined DC data as a result of audio decoding, audio mute can be performed and good special reproduction can be realized.

In the first embodiment, the third memory 27, the fourth memory 29,
The control method of the still image packet generation circuit 30, the switch 31, and the switch 32 has been described. However, the control method is not limited to the high-speed reproduction, and the mode transition to the still reproduction or the mode transition from the still reproduction to the normal reproduction. The same effect can be obtained by using the mode from high-speed reproduction to still reproduction or vice versa, or from normal reproduction to slow reproduction or vice versa. Although the first embodiment does not refer to the slow reproduction, the slow reproduction can be realized by repeating the still reproduction. Therefore, the reproduction data and the still image packet (including the no data packet) are switched and used as described above. Needless to say, this can be realized in the same manner as in the first embodiment.

In the first embodiment, a digital VTR for recording an ATV signal, which is being discussed in the United States, has been described. However, the present invention is not limited to this. For example, a special digital VTR for recording an MPEG2 bit stream may be used. The above-described still image packet and no data packet may be used for control during reproduction. The signal recording / reproducing apparatus is not limited to the digital VTR. For example, only the intra-coded data at the time of special reproduction such as a disk apparatus for reproducing or recording / reproducing an ATV bit stream or an MPEG bit stream is used. The same effect can be obtained even when used to form a reproduced image.

In the first embodiment, the decoding algorithm shown in FIG. 17 is used when decoding C4 decoding. However, the present invention is not limited to this. If the decoding algorithm uses the above-mentioned forced erasure flag, the above-mentioned C2 code or C3 code is used. As described above, even when used in decoding an error correction block adopting a product code format, error correction can be performed effectively, and the same effect can be obtained. Also, it goes without saying that error correction can be effectively performed even when decoding is performed using the above-described forced erasure flag when decoding a block that is encoded more than twice.

In the first embodiment, the case where the above-mentioned forced erasure flag is used at the time of high-speed reproduction has been described. However, the present invention is not limited to this. Play. The same effect can be obtained by using the above-mentioned forced erasure flag during normal reproduction. (Especially, decoding can be performed effectively when a long dropout occurs.)

Further, the writing to the memory 40 is controlled by the error detection result of the ID information added to the ID signal, but the present invention is not limited to this. For example, it goes without saying that a C1 decoding result or the like may be used.

Further, the thresholds n, R, and P of the decoding algorithm shown in FIG. 17 may be controlled to be switched in each of the normal reproduction mode and the special reproduction mode. In particular, in high-speed reproduction in which data is intermittently reproduced or in slow reproduction, the maximum number of erasure corrections may be set smaller than that in normal reproduction so as to suppress an oversight error due to the C4 code. (For example, n = 6, R = 6, P = 4 during normal playback, while n = 5, R = 5, P = 3 during high-speed playback)

The C4 decoding algorithm is not limited to the algorithm shown in FIG. 17. If the forced erasure flag is treated as an erasure, and if the C4 decoding algorithm is switched according to the number of the forced erasure flags, the error of the C4 code is obtained. Error correction using the maximum correction capability can be realized.

In the first embodiment, the operation has been described by separating the data update flag memory 41 and the forced erasure flag storage memory 52 for the sake of simplicity. However, the present invention is not limited to this. It goes without saying that it is good. In the first embodiment, decoding is performed by distinguishing the forced erasure flag from the C1 error detection flag. However, the present invention is not limited to this. In comparison, decoding can be performed by making full use of the error correction capability of the error correction code. In this case, the forced erasure flag storage memory 52 and the C1 error correction flag storage memory may be shared.

In the first embodiment, data in which an error is detected as a result of C1 decoding is written to the memory 40 (or the memory in the second error correction decoding circuit). However, the present invention is not limited to this. The same effect can be obtained even if control is performed so that data of the C1 block in which an error is detected is not written in the memory 40. (In this case, control is performed without distinguishing the forced erasure flag and the C1 error detection flag as described above.)
Although the configuration in which the data subjected to the C1 decoding is written in the memory is not limited to this, the C1 decoding and the C4 decoding (the C2 decoding at the time of normal reproduction) are performed after the reproduced data is once stored in the memory. The same effect can be obtained by the configuration.

In the first embodiment, when the error is corrected by the C4 code, the error correction is performed up to the limit of the error correction capability of the C4 code. However, the present invention is not limited to this. When the number of the forced erasure flags is large, Needless to say, in order to improve the error detection capability, the error correction capability or the number of erasure corrections may be set to a small value to control the error detection capability.

In the first embodiment, as shown in FIG. 7, a Reed-Solomon code of (85, 77, 9) is used as a code in the recording direction, and (20, 15, 6) is used as a code in the vertical direction.
However, the present invention is not limited to this case, and the same effect can be obtained with other product code type error correction codes if decoding is performed using the forced erasure flag.

When performing iterative error correction decoding using the above-described error correcting code in the recording direction (iterative error correction decoding means that C1 decoding is performed, then C4 decoding is performed, and data that has been C4 decoded is further processed. A decoding method in which error correction is performed again using the C1 code), and the error correction capability in the recording direction when performing iterative decoding is switched depending on the presence or absence of the update flag. As described above, since the decoding algorithm is switched depending on the presence or absence of the update flag, especially for the data of the unupdated C1 block, an overlooked error at the time of repeated decoding can be suppressed, and a good reproduced image can be synthesized.

When performing repeated error correction decoding using the error correction code in the recording direction, when decoding the reproduced digital data whose update flag is in the reset state (data of the unupdated C1 block), Since the erasure correction using the error detection flag detected with the error correction code (C4 code) in the direction different from the direction is controlled so as not to be performed, the data of the above-mentioned unupdated C1 block is particularly overlooked at the time of iterative decoding. Errors can be suppressed and a good reproduced image can be synthesized.

In the first embodiment, the case of the Reed-Solomon code which is a linear error correction code has been described. However, the present invention is not limited to this. For example, a BCH code or a BCH code may be used.
Even when an error correction code is composed of the CH code and the Reed-Solomon code, the same effect can be obtained by using the forced erasure flag when performing erasure correction.

Further, in the first embodiment, the decoding algorithm of the error correction code using the above-mentioned forced erasure flag has been described for the reproduction of the video signal. However, the present invention is not limited to this. Also,
In the first embodiment, the case of a digital VTR has been described as an example. However, the present invention is not limited to this case. It goes without saying that the above-mentioned effect is achieved.

When an error correction flag is added by an error correction circuit employing a decoding algorithm using the above-mentioned forced erasure flag, if the number of forced erasure flags is less than a predetermined number (for example, 3), only the forced erasure flag is corrected as an erasure. (In the case of FIG. 17, the number of erasures is 6 or more.) For the data of the error correction block in which the total number of erasures is smaller than a predetermined number (for example, 9), both the C1 error detection flag or both the forced erasure flag and the C4 error detection flag are set. The data in the error correction block other than the above is controlled so that all errors detected by the C4 code are added as errors and an error detection flag is added (B correction). With the above configuration, the error detection flag can be reliably added when the error detection flag is added, the overlooked error can be suppressed as much as possible, and the number of error detection flags can be sufficiently suppressed.

The memory for storing the erasure flag is separately provided as shown in FIGS. 2 and 3, but is not limited to this. For example, when the memory 40 is configured using a commercially available memory When an error correction block shown in FIG. 7 is constructed, an empty area is generated in the memory 40. The error detection flag or the data update flag may be written in the area. Further, since most commercially available memories used for error correction are composed of 8 bits, the data update flag and the C1 error detection flag are configured to be stored in different bits at the same address. Is also good. With the above-described configuration, the data update flag (forced erasure flag) and the C1 error detection flag can be read out at the time of C4 decoding, so that the circuit size can be reduced.

Further, the reset timing of the flag data in the data update flag memory 41, the forced erasure flag storage memory 52, the C1 error detection flag storage memory 53, and the C4 error detection flag storage memory 54 is not limited to the above timing. For example, the data update flag memory 41 may reset the data while reading the flag data during C4 decoding. (Lead after light)

Embodiment 2 FIG. FIG. 22 is a block diagram of a reproduction system of a digital VTR according to an embodiment of the present invention.
In the figure, the same parts as those in FIG. 1 are denoted by the same reference numerals, and the configuration and operation are the same as those in FIG. Reference numeral 34 denotes a header changing circuit for changing the header of the input transport packet. The recording format of the digital VTR in the second embodiment is the same as that in the first embodiment.

In the second embodiment, the ATV bit stream is recorded in the above-described manner (specifically, the special reproduction data is separated from the bit stream, and the separated special reproduction data is recorded in a predetermined area of a recording track). This is to reduce the capacity of a memory used for high-speed reproduction in a digital VTR (recording data).

Hereinafter, the digital VT according to the second embodiment will be described.
The operation of the reproduction system during high-speed reproduction of R will be described with reference to FIG. In the second embodiment, as in the first embodiment, FIG.
The case of the configuration of the rotary head shown in FIG. Further, the scanning trajectory of the rotary head 20a in the case of performing the 2x, 4x, 8x and 16x speed reproduction is as shown in FIG. 12 as in the first embodiment. Also, as in the first embodiment, the tracking control method at the time of high-speed reproduction is such that the rotation output is maximized at the center of the area where the special reproduction data is recorded at each multiple speed.
It is assumed that the tracking of 20a is controlled. (FIG. 13
(See (a) to (c))

Based on the above, the operation of the reproduction system at the time of high-speed reproduction will be described with reference to FIG. 22, FIG. 12, and FIG. When a high-speed playback mode signal is input, switch 3
2 selects the output of the switch 31. (It should be noted that the fine timing of switch switching is the same as in the first embodiment.) Rotating heads 20a and 20
The reproduced data intermittently reproduced via b is amplified by a head amplifier 21, converted into reproduced digital data by a signal detection circuit 22, and subjected to digital demodulation by a digital demodulation circuit 23. The data in which the synchronization signal is correctly detected by the signal detection circuit 22 is input to the ID detection circuit 24 and the first error correction decoding circuit 25. The ID detection circuit 24 separates the ID signal added to the head of each sync block based on the synchronization signal detected by the signal detection circuit 22, and uses the error detection code added in the ID signal. To detect an error contained in the ID signal.

On the other hand, in the first error correction decoding circuit 25,
Using the C1 check code added in the recording direction, an error occurring in the reproduced signal is corrected and detected.
The data subjected to the C1 decoding is output to a third error correction decoder 28.
Is input to Note that the output of the first error correction decoding circuit 25 is also input to the second error correction decoding circuit 26, but since the data is intermittently reproduced as described above, C2 decoding cannot be performed. Since no packet can be generated, in the second embodiment, the C2 decoding operation is not performed during high-speed reproduction, as in the first embodiment.

The special reproduction data subjected to C1 decoding by the first error correction decoding circuit 25 is subjected to C4 decoding by the third error correction decoding circuit. Note that the C4 decoding operation is the same as that in the first embodiment, and thus a detailed description is omitted.
The data subjected to C4 decoding in the third error correction decoding circuit 28 is stored in the fourth memory 29.

In the second embodiment, when a bit stream represented by MPEG2 is recorded on a digital VTR, an intra image is extracted from the bit stream in order to realize special reproduction, and a special reproduction provided in a recording track in advance is performed. The intra-frame data is recorded in the data recording area for use. At this time, the capacity of the memory used for high-speed reproduction is reduced.

Hereinafter, the fourth memory 29, the still picture packet generation circuit 30, and the switch 3 during forward high-speed reproduction will be described.
1 and the operation of the header change circuit 34 in FIG.
1 will be described. Normally, during special reproduction, intra-coded data is transmitted in units of one frame. Therefore, a memory for storing one frame of data is required as a memory for special reproduction as shown in the first embodiment. In the second embodiment, as shown in FIG. 21, one or a plurality of slices are collected in a fourth memory 29, and one frame of an intra image is divided into n blocks (hereinafter, referred to as slice blocks) and output. . The fourth memory 29 counts the amount of code for reproducing the special reproduction data in slice units, and forms slice blocks. In the second embodiment, the fourth
When the code amount of the special reproduction data stored in the memory 29 reaches a predetermined value, a slice block is formed, and the data is read from the fourth memory 29.

When the output of the data of one slice block is completed, the fourth memory 29 outputs a data output request signal to the still picture packet generation circuit 30. The still image packet generation circuit 30 outputs the no data packet as a packet between the slice blocks in the same frame, and outputs the still image packet and the no data packet in a predetermined number of frames between frames. In the second embodiment, the transport packet is transmitted as an inter-frame mode (inter-field or inter-frame prediction mode) as an output mode. In this case, control is performed so that the special reproduction data in slice units, which is intermittently reproduced during high-speed reproduction, is transmitted as a forced intra-frame mode. FIG. 21 shows a case where one frame is divided into n slice blocks. (N
Is an integer of 2 or more)

Hereinafter, the data control method at the time of high-speed reproduction according to the second embodiment will be described focusing on the operation of the still picture packet generation circuit 30 and the header replacement circuit 34. In the second embodiment, the transport packet is
Even if the data for special reproduction is handled and transmitted as an intra-frame image, the same effect can be obtained.

As described above, at the time of forward high-speed reproduction in the second embodiment, the transport packet to be output is transmitted as an inter-frame mode packet. Further, in order to freeze (still) the screen on the ATV decoder side during the special reproduction, a still image packet and a no data packet are generated by the still image packet generation circuit 30 between the special reproduction data packets of one frame (FIG. 21). As a result, the ATV decoder can output a good high-speed playback image as in the first embodiment without being conscious of the special playback mode. Hereinafter, the operation after the fourth memory 29 will be described with reference to FIG.

The special reproduction data reproduced through the rotary head 20 is subjected to digital demodulation, error correction, etc., and then temporarily stored in the fourth memory 29 to form a slice. The slice constituted by the fourth memory 29 is output to the header change circuit 34 via the switch 31. The header replacement circuit 34 detects a header portion indicating the transmission mode of the image in the packet header (picture header in MPEG2) and replaces it with a header indicating an interframe (or interfield). (The decoding mode of a block is switched on a macroblock basis.)), And a header portion indicating the decoding mode is detected, and this header is replaced with a header of the intra-frame mode. The special reproduction data packet with the header replaced is supplied to the output terminal 33 via the switch 32. As a result, the transport packet for transmitting the trick play data is transmitted as an inter-frame packet, and the data of each macroblock is decoded by the ATV decoder in the forced intra-frame mode.

On the other hand, when the output of the transport packet for special reproduction for one frame is completed, the still picture packet is output from the still picture packet generation circuit 30. Similarly, the switch 31 selects the output of the still image packet generation circuit 30 when the output of the transport packet for special reproduction for one frame is completed. (Note that the generation timing of the still image packet and the switching timing of the switch 31 are the same as those in the first embodiment.) The output (still image packet) of the switch 31 is supplied to the switch 32 via the header changing circuit 34. Is done. Note that the header portion of the still image packet is generated in the still image packet generation circuit 30. In the second embodiment, the header replacement is not performed by the header replacement circuit 34.

In the second embodiment, since the output transport packets are controlled as described above, the memory capacity of the fourth memory 29 can be significantly reduced as compared with the first embodiment. Specifically, it is sufficient to arrange a memory capable of storing data for one slice (several slices depending on the slice configuration), and it is not necessary to arrange a memory for one frame on the reproduction system side as shown in the first embodiment. . In particular, a reproduction-only device does not need to have a memory for one frame, so that the circuit scale can be reduced. Also, the ATV decoder can decode the transport packet without being aware of the special reproduction mode.

Embodiment 3 FIG. In a third embodiment, another data transmission method will be described. The transmission method is configured such that the still image packets for a predetermined number of frames are generated and transmitted by the still image packet generation circuit 30 after the special reproduction data for one frame is once transmitted to the ATV decoder. In the third embodiment, a case will be described in which the trick play data is divided into a plurality of frames and transmitted. It is assumed that the configuration of the reproduction system of the digital VTR in the third embodiment is the same as that shown in FIG.

FIG. 23 is a diagram for explaining the state of reproduced data during special reproduction in the forward direction of the digital VTR according to one embodiment of the present invention, and FIG. 26 is a diagram illustrating a digital VTR according to one embodiment of the present invention. FIG. 10 is a diagram for explaining a state of reproduction data at the time of special reproduction in the reverse direction. In the third embodiment, the slice block is configured by combining the special reproduction data intermittently reproduced during the high-speed reproduction, and the slice block is combined with the still image packet generated by the still image packet generation circuit 30. To generate a one-frame transport packet and output it to the ATV decoder.
(Hereinafter referred to as a partial refresh method.)

The above-mentioned partial refresh method in the case where forward high-speed reproduction is performed will be described below with reference to FIGS. 23 and 24. FIG. 23A shows special reproduction data reproduced from the rotary head 20 when performing high-speed reproduction in the forward direction. (Actually, it is reproduced intermittently.) FIG. 3B shows an output transport packet output from the switch 32. It should be noted that one frame shown in the figure indicates a transport packet for one frame. FIG. 3C shows a switching signal of the switch 31. FIG.
FIG. 4 is a diagram showing a partial refresh on the screen during special reproduction in the forward direction of the digital VTR according to one embodiment of the present invention. In the figure, the data in the hatched portion indicates the data for special reproduction forcibly transmitted in the intra mode, and the other portion indicates the transmission portion of the still image packet output from the still image packet generation circuit 30. In the third embodiment, FIG.
As shown in (1), one frame of the special reproduction image is divided into n slice blocks and transmitted.

Hereinafter, the operation of the reproducing system at the time of high speed reproduction in the forward direction will be described with reference to FIGS. 22, 23 and 24. The operation up to the third error correction decoding circuit 28 is the same as that of the second embodiment.
Therefore, the description is omitted. The data subjected to the reproduction signal processing as described above and subjected to the C4 decoding by the third error correction decoding circuit 28 is stored in the fourth memory 29.

In the third embodiment, the memory capacity of the special reproduction memory (fourth memory 29) used at the time of high-speed reproduction when performing high-speed reproduction with a digital VTR adopting the above-described recording method as in the second embodiment. Is to reduce.

Hereinafter, the fourth memory 29, the still picture packet generation circuit 30, and the switch 3 during forward high-speed reproduction will be described.
1 and the operation of the header change circuit 34 in FIG.
2 will be described. Normally, during special playback, data is transmitted in units of one frame that has been intra-coded. Therefore, a memory for storing one frame of data is required as a memory for special playback as shown in the first embodiment. In the third embodiment, as shown in FIG. 23 or FIG. 24, a plurality of slices are collected in the fourth memory 29 to form a slice block, and the slice block and a still image packet output from the still image packet generation circuit 30 are formed. And constructs and outputs a transport packet of one frame. 4th
In the memory 29, the code amount of the special reproduction data is counted in slice units to form a slice block. In the third embodiment, as in the second embodiment, a slice block is formed when the code amount of the special reproduction data stored in the fourth memory 29 reaches a predetermined value, and the data is read from the fourth memory 29. Soup

When the data structure of one slice block is completed, the fourth memory 29 outputs a data output request signal and a macro block address included in the slice block to the still picture packet generation circuit 30.
According to the MPEG2 standard, when transmitting a packet, a macroblock of one frame is divided into slices and transmitted. The transmission order is defined such that the macroblock is transmitted in the order of raster scan from the macroblock at the upper left on the screen. Therefore, in the third embodiment, the address of the first macroblock and the address of the last macroblock in the slice block are transmitted as the macroblock address information. When the still image packet generation circuit 30 receives the above signal, first, the header information (picture header in MPEG2) indicating that it is an interframe (field) is followed by the macroblock immediately preceding the first macroblock. Generate and output a still image packet. If the special reproduction data is at the beginning of the frame, the header (picture header in MPEG2) is added in advance, so that the header is not added. At this time, switch 3
1 selects the output of the still picture packet generation circuit 30. When the output of the still image packet up to the first macroblock address is completed, the still image packet generation circuit 3
0 outputs a data read start signal to the fourth memory 29.

In the fourth memory 29, when the above signal is received, the slice block thus constructed is read from the beginning. At this time, the switch 31 selects the output of the fourth memory 29. When the reading of the slice block ends, a control signal indicating that the reading of the data is completed is output to the still image packet generation circuit 30. Upon receiving the signal, the still image packet generation circuit 30 generates and outputs a still image packet from the macroblock next to the last macroblock of the slice block to the last macroblock of one frame. At this time, the switch 31 selects the output of the still picture packet generation circuit 30 again. When the generation of the still image packet up to the last macroblock of one frame is completed, the still image packet generation circuit 30 outputs the no data packet until the configuration of the next slice block is completed.

On the other hand, the output of the switch 31 is input to the header change circuit 34. In the third embodiment, as in the second embodiment, the transport packet is transmitted in an inter-frame mode (inter-field or inter-frame prediction mode). In this case, control is performed so that slice-specific special reproduction data that is intermittently reproduced during high-speed reproduction is transmitted as a forced intra-frame mode. As in the second embodiment, the header reordering circuit 34 detects a header portion indicating the image transmission mode in the packet header (picture header in MPEG2) for the special reproduction data packet, and performs a header indicating the interframe (or interfield). At the same time, the header part indicating the decoding mode of the macroblock is detected, and this header is replaced with the header of the intra-frame mode. The special reproduction data packet with the header replaced is supplied to the output terminal 33 via the switch 32. As a result, the transport packet for transmitting the trick play data is transmitted as an inter-frame packet, and the data of each macroblock is decoded by the ATV decoder in the forced intra-frame mode.

On the other hand, the still picture packet output from the still picture packet generating circuit 30 is supplied to the switch 32 via the header changing circuit 34. It should be noted that the header portion of the still image packet is generated in the still image packet generation circuit 30, and the header replacement is not performed by the header replacement circuit 34 in the third embodiment as in the second embodiment.

FIGS. 23 and 24 are timing charts when one frame of special reproduction data packet is divided into n-frame transport packets and transmitted.
Also, the state of refreshing the screen of the transmitted frame data is shown. As shown in the figure, by transmitting data, the screen of one frame is updated for a plurality of slices per frame, and all the special reproduction images are updated (partially refreshed) in n frames.

As described above, in the third embodiment, at the time of high-speed reproduction in the forward direction, the transport packet to be output is transmitted as an interframe mode packet. Also, in order to freeze (still) the screen on the ATV decoder side during the special reproduction, the still image packet generation circuit 30 generates a still image packet and a no data packet for the unrefreshed screen information in one frame (see FIG. 2
3), the ATV decoder can output a good high-speed reproduced image similarly to the first embodiment without being aware of the special reproduction mode.

Next, at the time of high-speed reproduction in the reverse direction, the fourth memory 2
Next, a method for reducing the capacity of No. 9 will be described. In the second embodiment, at the time of high-speed reproduction in the forward direction, a plurality of reproduction slices are collected in the fourth memory 29 to form a slice block, and a special reproduction data packet is output from the fourth memory 29 in units of the configured slice blocks. Then, a no-data packet is inserted between slice blocks in the same frame, and a transport packet for high-speed playback is generated by inserting a still image packet between each frame, thereby performing special playback. The memory capacity of the application memory has been reduced. This is because the trick play data is recorded in the order of the slice to which the bit stream is input. Therefore, even if a slice block is configured as described above and the playback data is output in slice block units, the data is recorded in the forward direction. In high-speed reproduction, there is no need to change the order of the slices to be reproduced. Therefore, it was possible to sequentially output data in slice units before composing data of one frame.

On the other hand, when performing high-speed reproduction in the reverse direction, the slices are reproduced in the reverse order of recording. However, according to the MPEG2 standard, the macroblocks must be transmitted in the raster scan order from the macroblock arranged at the upper left of the screen as described above. Therefore, when the intra-frame data is input, the ATV decoder starts decoding the image data from the first slice. At this time, if the transmission order of the slices in the input bit stream is different from the predetermined order, the ATV decoder cannot form a reproduced image. this is,
When the order of the reproduced slices is different from that of the ATV decoder (MPEG2 standard), the function of deshuffling the slices decoded at a predetermined position on the screen is not supported. In such a case, in order to realize high-speed reproduction in the reverse direction, it is necessary to prepare a memory capable of storing at least one frame of the special reproduction data in the reproduction system and rearrange the reproduced data. is there.

FIG. 25 is a diagram for explaining the operation of a digital VTR according to one embodiment of the present invention at the time of special reproduction in the reverse direction. FIG. 25 (a) shows a configuration example of a slice block in one frame. FIG. 7B shows the scanning trajectory of the rotary head 20a at the time of performing the double speed reproduction. FIG. 2C shows a reproduced signal output from the rotary head 20a . In addition,
In this embodiment, it is assumed that the slice block can be constituted by one-track special reproduction data. Since the data of the slice block is reproduced in reverse as described above, the transmission method as described in the second embodiment (a predetermined number of still image packets are transmitted after outputting one frame of special reproduction data) is used. Can't do it. Therefore, the fourth memory 2
It is necessary to rearrange the data in step 9. Hereinafter, the above rearrangement memory is not required even at the time of high-speed reproduction in the reverse direction,
A description will be given of a data control method in the case where the above partial refresh method is used in high-speed reproduction in the reverse direction in order to correctly decode a reproduction signal.

Therefore, even in the case of high-speed reproduction in the backward direction, transport packets to be output are transmitted as packets in the inter-frame mode (inter-field or inter-frame prediction mode) in the same manner as in high-speed reproduction in the forward direction. At this time, control is performed so that the special reproduction data intermittently reproduced at the time of reverse high-speed reproduction is transmitted as a forced intra-frame mode. The data control method at the time of high-speed reproduction in the reverse direction of the third embodiment will be described below with reference to FIG.
The operations of the fourth memory 29, the still image packet generation circuit 30, and the header replacement circuit 34 will be mainly described with reference to FIGS. 25, 26, and 27.

FIG. 26 is a diagram for explaining the state of reproduction data during special reproduction in the reverse direction of the digital VTR according to one embodiment of the present invention. FIG. 27 is a diagram showing a partial refresh on the screen at the time of special reproduction in the reverse direction of the digital VTR according to one embodiment of the present invention. FIG. 26A shows special reproduction data reproduced from the rotary head 20 when high-speed reproduction in the reverse direction is performed (actually, data is reproduced intermittently). FIG. 3B shows an output transport packet output from the switch 32. It should be noted that one frame shown in the figure indicates a transport packet for one frame. FIG. 3C shows a switching signal of the switch 31. FIG. 27 shows data of each inter frame output from the digital VTR. In the figure, the data in the hatched portion indicates the data for special reproduction transmitted in the forced intra mode, and the other portion indicates the transmission portion of the still image packet output from the still image packet generation circuit 30. In the reverse high-speed reproduction, as in the case of the forward direction, one frame of the special reproduction image is divided into n slice blocks and transmitted as shown in FIG.

Hereinafter, the operation of the reproducing system will be described. As described above, the operation up to the third error correction decoding circuit 28 is the same as that of the second embodiment, and the description is omitted. The data subjected to the reproduction signal processing as described above and subjected to the C4 decoding by the third error correction decoding circuit 28 is stored in the fourth memory 29. The fourth memory 29 separates slices from the input special reproduction data, counts the code amount of the special reproduction data in slice units, and forms a slice block. In the fourth memory 29, when the code amount of the stored special reproduction data reaches a predetermined value, a slice block is formed, and the data is read from the fourth memory 29.

When the structure of the data of one slice block is completed, the fourth memory 29 outputs a data output request signal to the still picture packet generation circuit 30 and the macros of the first and last macro blocks included in the slice block. Output block address. (Note that, similarly to the case of the forward high-speed reproduction, header information indicating that the data for special reproduction data does not come at the beginning is an inter frame (field) is added to the beginning.) Still image Upon receiving the above signal, the packet generation circuit 30 first generates and outputs a still image packet up to the macroblock immediately before the first macroblock. At this time, the switch 31 selects the output of the still picture packet generation circuit 30. When the output of the still image packet up to the top macroblock address is completed, the still image packet generation circuit 30 outputs the fourth memory 2.
9, a data read start signal is output.

In the fourth memory 29, upon receiving the above signal, the slice block generated earlier is read from the beginning. At this time, the switch 31 selects the output of the fourth memory 29. When the reading of the slice block ends, a control signal indicating that the reading of the data is completed is output to the still image packet generation circuit 30. Upon receiving the signal, the still image packet generation circuit 30 generates and outputs a still image packet from the macroblock next to the last macroblock of the slice block to the last macroblock of one frame. At this time, the switch 31 selects the output of the still picture packet generation circuit 30 again. When the generation of the still image packet up to the last macroblock of one frame is completed, the still image packet generation circuit 30 outputs the no data packet until the configuration of the next slice block is completed.

On the other hand, the output of the switch 31 is input to the header changing circuit 34. In the third embodiment, as in the second embodiment, the transport packet is transmitted in an inter-frame mode (inter-field or inter-frame prediction mode). In this case, control is performed so that slice-specific special reproduction data that is intermittently reproduced during high-speed reproduction is transmitted as a forced intra-frame mode. As in the second embodiment, the header replacement circuit 34 detects a header portion indicating the image transmission mode of the image in the packet header (picture header in MPEG2) for the special reproduction data packet, and indicates the inter frame (or inter field). At the same time, the header part indicating the decoding mode of the macroblock is detected, and this header is replaced with the header of the intra frame mode. The special reproduction data packet with the header replaced is supplied to the output terminal 33 via the switch 32. As a result, the transport packet for transmitting the data for trick play is transmitted as an inter-frame packet, and the data of each macroblock is transmitted in the AT mode as the forced intra-frame mode.
It is decoded by the V decoder.

On the other hand, the still picture packet output from the still picture packet generating circuit 30 is supplied to the switch 32 via the header changing circuit 34. It should be noted that the header portion of the still image packet is generated in the still image packet generation circuit 30, and the header replacement is not performed by the header replacement circuit 34 in the third embodiment as in the second embodiment.

FIGS. 26 and 27 show timing charts when transmitting one frame of special reproduction data packet into n-frame transport packets during high-speed reproduction in the reverse direction, and a screen of transmitted frame data. Refreshed. As shown in the figure, by transmitting data, the screen of one frame is updated for a plurality of slices per frame, and all the special reproduction images are updated (partially refreshed) in n frames.

As described above, in the third embodiment, at the time of high-speed reproduction in the reverse direction, the transport packet to be output is transmitted as an inter-frame mode packet. Further, in order to freeze (still) the screen on the ATV decoder side during the special reproduction, the still image packet generation circuit 30 generates a still image packet for the slice in which the special reproduction data packet in one frame is not transmitted. FIG.
6), the ATV decoder can output a good high-speed playback image as in the first embodiment without being aware of the special playback mode.

At the time of high-speed reproduction as described above, the reproduction data is not stored in the memory for high-speed reproduction in units of one frame as in Embodiment 1, but is stored in the memory for high-speed reproduction in units of one slice block. As a result, the memory capacity can be reduced. At the time of high-speed reproduction in the reverse direction, slices are reproduced in the reverse order of recording, so that at least one frame of high-speed reproduction data must be stored in order to form a reproduced image with the ATV decoder. It was necessary to prepare a possible rearrangement memory in the reproduction system and rearrange the reproduced data.However, at the time of high-speed reproduction, the mode was switched to the inter-frame mode, and the reproduction was performed in units of slices. By switching the mode of the data to the forced intra-frame mode, the reordering memory becomes unnecessary. Also, as in the case of high-speed reproduction in the forward direction, the reproduction data is stored in the memory for high-speed reproduction in units of one slice, so that the memory capacity can be reduced. (Depending on the size of the slice block and the refresh cycle of the data for special reproduction, for example, when data of one frame is divided into ten slice blocks and transmitted, the memory capacity can be reduced to about 1/10. )

In the third embodiment, since the output transport packets are controlled as described above, the memory capacity of the fourth memory 29 can be significantly reduced as compared with the first embodiment. Specifically, it is sufficient to arrange a memory capable of storing data for one slice (several slices depending on the slice configuration), and it is not necessary to arrange a memory for one frame on the reproduction system side as shown in the first embodiment. . In particular, a reproduction-only device does not need to have a memory for one frame, so that the circuit scale can be reduced. Also, the ATV decoder can decode the transport packet without being aware of the special reproduction mode.

Embodiment 4 FIG. In the fourth embodiment, a method of forming a still image packet will be described. In MPEG2, macroblock skip is defined only for transmission of interframe packets. The macroblock skip means that any macroblock in the same slice may be skipped and transmitted. (However, skipping is not possible for the first and last macroblocks of the slice.) The size of the slice is not limited as long as the slice is composed of macroblocks in the same horizontal macroblock as described above. Therefore, in the fourth embodiment, a still image packet is transmitted using this skip. FIG. 28 is a diagram showing the configuration of a still image packet in slice units according to one embodiment of the present invention. As shown in the figure, the slice is composed of two macroblocks, and the data in each macroblock is composed of data having a motion vector of 0 and a prediction error of 0. FIG. 28 shows a case where all macroblocks in the same horizontal direction are still picture packets. When a still image packet is composed of macroblocks in the middle of the screen, the macroblock addresses in the macroblocks may be changed. Specifically, the relative address of the succeeding macroblock may be changed. When the still image packet is configured as described above, the circuit scale of the circuit that stores the still image packet can be reduced, and the amount of generated data of the still image packet can be reduced, so that there is an effect that the circuit control becomes very simple.

Embodiment 5 FIG. In the first, second, and third embodiments, the still image packet is transmitted with a motion vector of 0 and a prediction error of 0. However, the present invention is not limited to this.
For example, when the data at the time of trick play is not transmitted, the same effect can be obtained if the packet is one that is interpolated with the image of the previous frame (or the previous field). In particular, if one frame of the special reproduction image is divided into a plurality of frames and transmitted as used in the third embodiment, it goes without saying that the memory capacity in the reproduction system can be reduced and the circuit scale can be reduced. No.

Embodiment 6 FIG. In the above embodiment, the still image packet is generated in units of transport packets. However, the present invention is not limited to this. For example, when a slice block is formed in the second or third embodiment, the slice block is formed in units of transport packets. Although such a case has been described, the present invention is not limited to this, and the same applies to a case where a macroblock having the motion vector of 0 and a prediction error of 0 is inserted from the middle of a reproduced transport packet to generate a transport packet. It works. The same effect can be obtained even if a transport packet is configured by inserting special reproduction data (in units of slices) reproduced following the macroblock indicating the still image.

Embodiment 7 FIG. In this embodiment, the trick play data has been treated as frame image data. However, the present invention is not limited to this. If the transmitted transport packet is a field image, the transport packet is treated as a field image and similar processing is performed. For example, the same effect can be obtained. Further, in the above embodiment, the case where the data recording format is shown in FIG. 11 has been described. However, the present invention is not limited to this, and the high efficiency coding method using the motion compensation prediction represented by MPEG2 is performed. In a digital VTR for recording the obtained digital signal, the data subjected to intra-encoding is separated from the digital signal as special reproduction data, and the separated special reproduction data is stored in a predetermined area on a recording medium. It is needless to say that a similar effect can be obtained by the above control if the digital signal reproducing device has a format in which is recorded.
In the above embodiment, the digital VTR was described as an embodiment of the digital signal reproducing apparatus. However, the present invention is not limited to this. A similar effect is achieved.

[0184]

Since the present invention is configured as described above, it has the following effects.

According to the digital signal reproducing apparatus of the first aspect of the present invention, a digital video signal and a digital audio signal which are input in the form of a packet and which are coded within a frame or a field, or between a frame or an interfield, are input. Are recorded transparently, and special reproduction data to be used at the time of special reproduction is generated from the digital video signal subjected to frame or intra-field encoding from the packet , and the generated special reproduction data is stored at a predetermined position. A digital signal reproducing apparatus for reproducing a recording medium recorded in the digital reproduction device; a data separation unit for separating the special reproduction data from the reproduction signal during the special reproduction; and a data storage unit for storing the separated special reproduction data. , All macroblocks in the slice And a still image slice data generating means for generating slice data having a prediction vector of 0 and a prediction error of 0, and outputting the special reproduction data for one frame or one field separated from the data storage means. Later, since the still image slice generating means is controlled so as to output the output of the still image slice generating means for a predetermined number of frames, the memory capacity can be reduced, and the circuit scale can be reduced. AT
There is an effect that special reproduction can be realized without making the V decoder aware of the special reproduction mode.

Further, according to the digital signal reproducing apparatus of the second aspect of the present invention, the digital signal reproduced in the form of a packet,
A digital video signal coded in a frame or a field, or between a frame or an inter-field, and a digital audio signal are recorded transparently, and the packet is more special than the digital video signal coded in a frame or a field. In a digital signal reproducing device for reproducing a recording medium in which special reproduction data used at the time of reproduction is generated and the generated special reproduction data is recorded at a predetermined position, the special reproduction data is reproduced from the reproduction signal at the time of special reproduction. Data separating means for separating the data for special reproduction, and a still image in which all macro blocks in the slice generate slice data having a motion vector of 0 and a prediction error of 0 With slice data generation means The one or more slices of the special reproduction data separated by the data separation means from the intermittently reproduced data and the output of the still picture slice data generation means are used to form a transport packet for one frame. Since the transport packet is configured to be a field or an inter-frame prediction mode packet, and the intermittently reproduced special reproduction data is configured to be transmitted in a forced intra-frame mode, the packet is configured to be transmitted. This has the effect that the memory capacity can be reduced, and the circuit scale can be reduced.

According to the digital signal reproducing apparatus of the third aspect of the present invention, at the time of still reproduction, the output of the still picture packet generating means is used to output the frame or the last data of the frame reproduced at the time of normal reproduction. After output,
Since it is configured to always output, there is no need to provide a memory for storing one frame of intra information on the digital VTR side even in still reproduction without using data for special reproduction. The use of this has an effect that a good reproduced image can be formed.

According to the digital signal reproducing apparatus of the fourth aspect of the present invention, in the high speed reproduction mode and thereafter, the servo system is locked and the data of the special reproduction intra frame is read from the high speed reproduction area. The data switching means is controlled so that the output of the still picture packet generating means is selected until the playback of the still picture packet is performed. Has the effect that can.

According to the digital signal reproducing apparatus of the fifth aspect of the present invention, the control system is used at least at the time of special reproduction in the reverse direction, so that the memory capacity at the time of high-speed reproduction can be reduced. In addition to this, there is no need for a memory for rearranging data to be provided for reverse reproduction, so that the circuit size can be further reduced.

According to the digital signal reproducing apparatus of the sixth aspect of the present invention, the digital signal reproduced in the form of a packet is
A digital video signal coded in a frame or a field, or between a frame or an inter-field, and a digital audio signal are recorded transparently, and the packet is more special than the digital video signal coded in a frame or a field. In a digital signal reproducing apparatus that reproduces a recording medium on which special reproduction data used for reproduction is generated and the generated special reproduction data is recorded at a predetermined position, the special reproduction data is separated from a reproduction signal. Data separating means and specific area fixed packet generating means for generating a packet for stopping a signal in a specific area on the screen when decoding data output from the digital signal recording and reproducing apparatus and restoring reproduced image data are provided. And during special playback, intermittent When composing a reproduced image using the data reproduced in the above, the output of the specific packet fixing means and the reproduction data are switched to transmit the special reproduction data of one frame into a plurality of frames. Therefore, there is an effect that the memory capacity at the time of high-speed reproduction can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a reproduction system of a digital VTR according to an embodiment of the present invention.

FIG. 2 is a block diagram of a third error correction decoding circuit according to an embodiment of the present invention.

FIG. 3 is a block diagram of an error correction circuit 43 according to an embodiment of the present invention.

FIG. 4 shows one embodiment of the present invention based on the SD standard.
FIG. 3 is a diagram showing an arrangement of data in a track.

FIG. 5 is a layout diagram of rotary heads 20a and 20b on a typical rotary drum 19 used in the SD mode.

6A and 6B are diagrams illustrating a data packet according to an embodiment of the present invention, wherein FIG. 6A is a diagram of a transport packet included in an input bit stream, and FIG. 6B is a diagram of a recorded data packet recorded on a magnetic tape. It is.

FIG. 7 is a diagram illustrating a code configuration of an error correction code added to special reproduction data of a digital VTR according to an embodiment of the present invention.

FIG. 8 is a diagram showing the number of sync blocks from which data can be acquired during high-speed playback.

FIG. 9 is a diagram showing a layout of a special reproduction data recording area in a track of a digital VTR according to an embodiment of the present invention, and a diagram showing a layout of data to be recorded in the special reproduction data recording area.

FIG. 10 is a digital VTR according to an embodiment of the present invention.
FIG. 6 is a diagram showing a method of dividing one error correction block of 16 × speed data (-14 × speed).

FIG. 11 is a digital VTR according to an embodiment of the present invention.
FIG. 3 is a diagram showing a track format.

FIG. 12 is a digital VTR according to an embodiment of the present invention.
FIG. 9 is a head scanning trajectory diagram of the rotary head 20a when high-speed reproduction at 2, 4, 8, and 16 times speed is performed.

FIG. 13 shows a digital VTR according to an embodiment of the present invention.
FIG. 5 is an operation explanatory diagram for describing a tracking control operation of FIG.

FIG. 14 shows a general C used for a digital VTR.
It is a figure explaining 1 decoding algorithm.

FIG. 15 shows a general C used for a digital VTR.
It is a figure explaining a 4 decoding algorithm.

FIG. 16 shows a digital VTR according to an embodiment of the present invention.
FIG. 8 is a diagram for explaining an algorithm for adding a data update flag.

FIG. 17 is a digital VTR according to an embodiment of the present invention.
FIG. 9 is a diagram for explaining a C4 decoding algorithm of FIG.

FIG. 18 is a digital VTR according to an embodiment of the present invention.
FIG. 35 is an operation explanatory diagram for describing the C4 decoding algorithm of FIG.

FIG. 19 is a digital VTR according to an embodiment of the present invention.
3 is a timing chart of special reproduction.

FIG. 20 is a digital VTR according to an embodiment of the present invention.
5 is a timing chart at the time of shifting from normal reproduction to special reproduction.

FIG. 21 is a digital VTR according to an embodiment of the present invention.
FIG. 7 is an operation explanatory diagram showing an output form of data for one frame during special reproduction.

FIG. 22 is a digital VTR according to an embodiment of the present invention.
FIG. 3 is a block diagram of a reproduction system of FIG.

FIG. 23 is a digital VTR according to an embodiment of the present invention.
FIG. 7 is a diagram for explaining a state of reproduction data at the time of special reproduction in the forward direction.

FIG. 24 is a digital VTR according to an embodiment of the present invention.
FIG. 6 is a diagram showing a partial refresh on the screen during special reproduction in the forward direction of FIG.

FIG. 25 is a digital VTR according to an embodiment of the present invention.
It is an operation explanatory diagram at the time of special reproduction in the reverse direction.

FIG. 26 is a digital VTR according to an embodiment of the present invention.
FIG. 10 is a diagram for explaining a state of reproduction data at the time of special reproduction in the reverse direction.

FIG. 27 is a digital VTR according to an embodiment of the present invention.
FIG. 11 is a diagram showing a partial refresh on the screen during trick play in the reverse direction of FIG.

FIG. 28 is a diagram illustrating a configuration example of a still image packet when a macroblock skip is used in a slice according to an embodiment of the present invention.

FIG. 29 is a track pattern diagram of a general home digital VTR.

FIG. 30 is a diagram showing head scanning trajectories of a rotary head during normal reproduction and high-speed reproduction of a conventional digital VTR.

FIG. 31 is a block diagram of a conventional bit stream recording device capable of high-speed reproduction.

FIG. 32 is a diagram showing an outline of a conventional digital VTR at the time of normal reproduction and at the time of high-speed reproduction.

FIG. 33 is a head scanning locus diagram during general high-speed reproduction.

FIG. 34 is a diagram illustrating an overlap area at the time of a plurality of conventional high-speed reproduction speeds.

FIG. 35 is a diagram of a head scanning locus at 5 × speed and 9 × speed in a conventional digital VTR.

FIG. 36 is a diagram illustrating two head scanning trajectories during 5 × speed reproduction in a conventional digital VTR.

FIG. 37 is a track layout diagram in a conventional digital VTR.

FIG. 38 is a data format diagram of a video signal recording area in one track of a video signal in the SD standard.

FIG. 39 is a diagram showing a configuration of one sync block in the SD standard.

[Explanation of symbols]

27 third memory, 29 fourth memory, 30 still picture packet generation circuit, 31, 32 switch, 34 header change circuit.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-8-79700 (JP, A) JP-A-7-222094 (JP, A) JP-A-8-32929 (JP, A) JP-A-8-79 46914 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04N 5/91-5/956 G11B 20/10-20/12 H04N 5/782-5/783

Claims (6)

(57) [Claims] 1. A entered in the form of packets, a frame or a field, or a digital video signal coded inter-frame or field, together with the a digital audio signal is transparently recorded, frame or field from the packet A digital signal reproducing apparatus for generating, from the digitally encoded digital video signal, special reproduction data to be used for special reproduction, and reproducing a recording medium on which the generated special reproduction data is recorded at a predetermined position. At
A data separation unit for separating the special reproduction data from the reproduction signal during the special reproduction, a data storage unit for storing the separated special reproduction data, and a prediction error when all the macroblocks in the slice have a motion vector of 0. And a still image slice data generating means for generating slice data having a value of 0. After outputting the special reproduction data for one frame or one field separated from the data storage means, A digital signal reproducing apparatus having data control means for controlling the still picture slice generating means so as to output the output of the means for a predetermined number of frames. 2. A input in the state of the packet, a frame or a field, or a digital video signal coded inter-frame or field, together with the a digital audio signal is transparently recorded, frame or field from the packet A digital signal reproducing apparatus for generating, from the digitally encoded digital video signal, special reproduction data to be used for special reproduction, and reproducing a recording medium on which the generated special reproduction data is recorded at a predetermined position. At
At the time of trick play, data separation means for separating the trick play data from the playback signal, data storage means for storing the trick play data separated, and prediction of all macroblocks in the slice with a motion vector of 0 A still image slice data generating means for generating slice data having an error of 0, wherein one or more slices of the special reproduction data separated by the data separation means from the reproduction data reproduced intermittently; And using the output of the still picture slice data generating means to make a transport packet for one frame, making the transport packet a field or a packet in the inter-frame prediction mode, and using the intermittently reproduced special reproduction data. Configure packets to be transmitted in forced intra-frame mode Digital signal reproducing apparatus characterized by having a packet generation unit. 3. During still playback, the data switching control means performs selection so that the output of the still picture packet generation means is always selected after the output of the last data of the frame or frame reproduced during normal playback. 2. The digital signal reproducing apparatus according to claim 1, wherein: 4. When the mode shifts to high-speed reproduction, the output of the still picture packet generation means is selected until the servo system is locked and the data of the intra-frame for special reproduction is reproduced from the high-speed reproduction area. 2. The digital signal reproducing apparatus according to claim 1, wherein said data switching control means is performed so as to perform the data switching control. 5. The digital signal reproducing apparatus according to claim 2, wherein said control method is used at least in a special reproduction in a reverse direction. 6. entered in the form of packets, a frame or a field, or a digital video signal coded inter-frame or field, together with the a digital audio signal is transparently recorded, frame or field from the packet A digital signal reproducing apparatus for generating, from the digitally encoded digital video signal, special reproduction data to be used for special reproduction, and reproducing a recording medium on which the generated special reproduction data is recorded at a predetermined position. At
A data separation unit for separating the special reproduction data from the reproduction signal; and a packet for stopping a signal in a specific area on the screen when decoding data output from the digital signal recording / reproduction device and restoring reproduction image data. Has a specific area fixed packet generating means for generating the data, and at the time of special reproduction, when composing a reproduced image using intermittently reproduced data, switching between the output of the specific packet fixing means and the reproduction data. A digital signal reproducing apparatus which controls so as to transmit one frame of the special reproduction data in a plurality of frames.