KR0150954B1 - Error correction encoding/decoding method and device of digital record reproducing apparatus - Google Patents

Abstract

The present invention relates to a method and apparatus for error correction encoding / decoding in a digital recording / reproducing apparatus. In particular, the present invention relates to a method and apparatus for minimizing loss of valid data during variable speed reproduction and efficiently performing error correction.

The error correcting and decoding method of the present invention is a method for recording and reproducing a digital VCR. In the case of variable speed playback, the error correction decoding method uses only the minimum data for maintaining the critical resolution. It not only minimizes the loss of valid data due to mismatch, but also has the advantage of simplifying the error correction process.

Description

Error correction encoding / decoding method of digital recording and reproducing apparatus, and apparatus suitable therefor

1 is a diagram showing the configuration of a recorder in a digital VCR.

2 is a block diagram showing a detailed configuration of an error correction encoding apparatus according to the present invention.

FIG. 3 is a diagram showing the form of the data recorded in the first memory shown in FIG. 2 and the recording / reading state.

FIG. 4 is a diagram showing the form of the data recorded in the second memory shown in FIG. 2 and the write / read state.

5A to 5B are diagrams showing data types of first data and second data to which an internal code is added by the internal code encoder shown in FIG.

FIG. 6 is a diagram showing the form of the data recorded in the third memory shown in FIG. 2 and the recording / reading state.

7 is a diagram showing the configuration of a reproduction system of a digital VCR.

8 is a block diagram showing a detailed configuration of an error correction decoder according to the present invention.

The present invention relates to a method and apparatus for error correction encoding / decoding of a digital recording / reproducing apparatus such as a digital video recorder (VCR). In particular, the present invention relates to a method for minimizing loss of valid data and efficiently correcting errors during variable-speed reproduction. Relates to a device.

The digital VCR converts and records video information into a digital signal, and shows much better performance in signal-to-noise ratio (S / N), resolution, and editing than a conventional analog VCR. These digital VCRs have evolved with advances in data compression, high density recording and error correction techniques. On the other hand, in variable speed reproduction, which is one of the functions that a VCR must have, there is a problem that the error occurrence rate is higher than that of normal reproduction because data is not continuously reproduced because the head transverses a plurality of tracks.

In Korean Patent 91-200052 filed by the present applicant (title: Method and apparatus for facilitating variable speed reproduction of a digital VCR), fewer sync blocks are recorded to overcome the above problems. A method of dividing and recording into a plurality of blocks having a size is disclosed.

In addition, Patent Application No. 92-4227, filed with the same patent in parallel with the present application as an improvement on the above application, excludes IDC (Independent Decodable Code) and IDC having most of information for reproducing the original image of the sync block. Disclosed is a method and apparatus for reducing and reducing the possibility of loss of recorded data by dividing into discrete decodale codes (DDCs) having redundant information and simplifying the variable speed reproducing process by reproducing only the IDC portion during variable speed reproducing. In the above-described method and apparatus, even when misalignment of the sync block occurs because the head traverses several tracks during variable-speed playback, an image close to the original image can be reproduced if only IDC, which is a part of the sync block, is detected.

An object of the present invention is to provide an error correction encoding and decoding method of a digital recording / reproducing apparatus which can minimize the loss of valid data during variable speed reproduction and simplify the error correction.

Another object of the present invention is to provide an apparatus suitable for the error correction encoding and decoding method described above.

Air correction encoding method according to the present invention to achieve the above object

In the error correction encoding method of a digital recording and reproducing apparatus for block-dividing video data of one screen, converting and encoding the video data in units of blocks, and recording the converted coded data,

Dividing the image data in the block unit into a first data code that can be independently decoded and a second data code that can be decoded dependently by a first data code; And

And adding a first internal code to the first data code, and adding a second internal code to the second data code.

The error correction decoding method according to the present invention to achieve the above object

The video data of one screen is divided into blocks, and the image data is separated and decoded into independent decodeable second data codes and dependently decoded second data codes on a block basis, and transform-coded first data codes and second An error correction decoding method of a digital recording and reproducing apparatus for reproducing digital video data recorded by adding a first internal code error and a second internal code error correction code to each data code,

In normal reproduction, the first data code and the second data code are error corrected and decoded by a first internal code error correction code and a second internal code error correction code respectively, and in the case of variable speed reproduction, only the first data code is decoded. (1) Error correction decoding is performed by an internal error correction code.

The error correction encoding apparatus according to the present invention achieves the above-described object block block division of image data of one screen, transform encoding of image data in units of each block, and error correction of the digital recording / reproducing apparatus for recording the converted encoding data. In the encoding device,

Separation means for separating the first data code having the minimum coefficients for maintaining the threshold resolution among the coded block data into the second data code having the independently decodable data coefficients and the redundant coefficients;

A first internal encoder that adds a first internal code for error checking and correction to the first data code output from the separating means;

A second internal encoder that adds a second internal code for error checking and correction to the second data code output from the separating means; And

And combining means for outputting the output of the first internal encoder and the output of the second internal encoder in a block unit.

According to another aspect of the present invention, there is provided an error correction decoding apparatus for block-dividing image data of one screen, and independently decoding first image code in each block unit and second data code that can be decoded dependently. A digital recording and reproducing apparatus for reproducing digital image data recorded by converting and encoding the first code code and the second code code, respectively, An error correction decoding apparatus, comprising: separating means for separating the read data into the first data code and the second data code;

A first internal code decoder which performs error checking and correction by a first internal code on the first data code separated by the separating means;

A second internal code decoder for performing error checking and correction by a second internal code on the second data code separated by said separating means;

And combining means for combining the first data coder and the second data code decoded by the first and second inner code decoders. Hereinafter, the configuration and operation of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of a recorder in a digital VCR. In FIG. 1, the color signal (RGB or luminance / color difference signal) input to the recording system is subjected to data compression through the video compression port 10, an error correction code is added in the error correction encoder 12, and the channel encoder ( 14, the color difference signals between the tracks are controlled alternately and recorded on the tape 16. FIG.

2 is a block diagram showing the configuration of an error correction encoding apparatus according to the present invention. In FIG. 2, reference numeral 20 denotes an ID generator for adding a block identification code (ID) to each sync block, and 22 denotes a vector for converting the input data into a power of α of a raw polynomial of a Reed-Solonom (RF) code. Alpha converter, 24 and 26 are a first memory and a first memory address controller for rearranging and outputting data for external code encoding of RS code through alpha-vector converter 22, 28 is a first memory ( 24 is an external code encoder for adding an external code to the RS code output from the code, and 30 and 32 are second memories for rearranging and outputting data for internal code encoding of the RS code through the external code encoder 28; A second memory address controller, 34 is a demultiplexer for separating the sync block output from the second memory 30 into a first data code IDC and a second data code DDC, and 36 and 38 are first data. IDC and second data code (D DC and the first and second internal call encoders respectively for adding an internal call in DC), 40 is a multiplexer for combining the codes of RSs through the first and second internal call encoders 36 and 38, 42 And 44 are second memory and third memory address controllers for rearranging and outputting sync blocks recorded on the tape 16, and 46 are sync signal generators for adding a sync code to each sync block. .

The operation of the apparatus shown in FIG. 2 will be described in detail. The compressed sync block (hereinafter referred to as SB) output from the image compression unit 10 of FIG. 1 is divided into a first data code IDC0 part and a second data code DDC part. The portion is data for variable-speed reproduction, for example, DC and some low frequency components in the DCT (Discrete Cosine Transform) encoding scheme, and may be the result of the first-order vector quantization in the vector quantization scheme. The (DDC) part includes the remaining part of the image data except for the first data code IDC, and the input SB is given a block identification code (ID) for distinguishing each SB by the ID generator 20. The vector-alpha converter 22 converts the power to the first memory 24 in the form of a power of α, which is the root of the original polynomial of the RS code.

The operation of the first memory 24 will be described with reference to FIG.

Under the control of the SB SMS WP1 memory address controller 26, which is input to the first memory 24, it is written in the X-axis direction, read in bytes in the Y-axis direction, and externally read. It is supplied to the call encoder 28.

The operation of the external code encoder 28, the second memory 30 and the second memory address controller 32 will be described with reference to FIG. The external encoder 28 performs external code encoding on the M bytes read by the control of the first memory address controller 26, and adds OP outer codes as shown in FIG. Supply to (30). Data input to the second memory 30 is written in the Y direction by the control of the second memory address controller 32 and read out in SB units in the X-axis direction and demultiplexer 34. The block identification code (ID), the first data code (IDC) and the second data code (DDC) are divided into and supplied to the first internal encoder 36 and the second internal encoder 38, respectively.

The operation of the internal encoder encoders 36 and 38 will be described with reference to FIGS. 5A-5B.

The first inner code encoder 36 performs inner code encoding on the block identification code ID and the first data code IDC, and adds an inner parity of one IP1 as shown in FIG. 5A. The second internal code encoder 38 performs internal code encoding on the second data code DDC to add IP2 internal codes as shown in FIG. 5B. The output of the encoder of each internal arc is alternately selected by the multiplexer 40 and supplied to the third memory 42.

An operation of the third memory 42 and the third memory address controller 44 will be described with reference to FIG. Through the multiplexer 40, the third memory 42 controls the first internal encoder 36 and the second internal encoder 38 as shown in FIG. 6 under the control of the third memory address controller 44. The output is read out in units of SB in the X-axis direction recorded alternately, and a synchronization signal is added by the synchronization signal generator 46 and supplied to the channel encoder 14 of FIG.

7 is a block diagram showing the configuration of a reproduction system in a digital VCR. In FIG. 7, the signal recorded on the tape 76 is channel decoded through the channel decoder 74, and the error correction and correction by the internal and external codes are performed through the error correction decoder 72, and then the image. The decompression unit 70 demodulates the original color signal (RGB or luminance / color difference signal).

8 is a block diagram showing the configuration of an error correction code and an apparatus according to the present invention. In FIG. 8, reference numeral 80 denotes a synchronization signal detector, and 82 and 84 denote data for separating a block identification code (ID) and an first code code (IDC) and a second data code (DDC) to which an internal code is added. A fourth memory and a fourth memory address controller for rearranging and outputting the data, and 86 denotes a block identification code (ID) and a first data code (IDC) and a first code added with an internal code in the data output from the fourth memory (83). A demultiplexer for separating two data codes (DDC), 88 and 90 are internal code decoders, 92 are two-dimensional error flag memories, 94 are set by two error signals from the internal code decoders 88 and 90; An address generator for generating a display address to the dimensional error flag memory 92, and 96 selectively outputs an internally decoded block identification code (ID) and a first data code (DC) and a second data code (DDC) Multiplexer, 98 and 100 are internal A fifth memory and a fifth memory address controller for rearranging and outputting the decoded block identification code ID, the first data code IDC, and the second data code DDC in combination, and 102 is an external code decoder. . Reference numeral 104 is a switch controlled to block the editor delivery path by the error signal ERR1 of the first internal decoder decoder 88, and 106 is a queue-type buffer. Reference numeral 108 denotes a selector for selecting and outputting the outputs from the external code decoder 102 and the queue buffer 106 by a signal indicating a variable speed reproduction provided from the outside, and 110 denotes a vector obtained by converting the data converted to the power of a power of α. Alpha-vector converter to convert.

In the operation of the apparatus shown in FIG. 8, the synchronization signal detector 80 detects the synchronization signal included in the input binary data string, blocks it in units of SB, and supplies it to the fourth memory 82. The fourth memory 82 is controlled by the fourth memory address controller 84 to record the input SB unit data as shown in FIG. 6, read in the X-axis direction, and supply it to the demultiplexer 86. As shown in FIG.

The demultiplexer 86 alternately selects a block ID (ID), a first data code (IDC), and a second data code (DDC) from among SB-unit data to be input to the first internal decoder 88 and The second internal code decoder 90 is supplied to the second internal code decoder 90.

The first and second internal code decoders 88 and 90 respectively provide the internal code IP1 and IP2 for the block identification code ID and the first data code IDC and the second data code DDC to which the internal code is added. Error correction is performed and supplied to the multiplexer 96. The multiplexer 96 alternately selects the outputs of the second and second internal code decoders 88 and 90 and supplies them to the fifth memory 98.

The fifth memory 98 stores the internal code decoded block identification code ID and the first data code IDC and the second data code DDC in the multiplexer 96 by the sixth memory address controller 100. As shown in FIG. 4, it is controlled to record in the X-axis direction, read out in the Y-axis direction in units of SB, and supply it to the outer code decoder 102.

The inner code decoders 88 and 90 generate the error signals ERR1 and ERR2 and supply them to the two-dimensional error flag memory 92 when an error outside the limit of error correction by the inner code occurs. The two-dimensional error flag memory 92 records the position of the SB in which the error occurs with reference to the error signals ERR1 and ERR2 and the address signal ADDR in the address generator 94. The external call decoder 102 refers to the SB in the fifth memory 98 by referring to the two-dimensional error flag memory 92 and performs error correction by an external call on the SB in which an uncorrectable internal code error has occurred. Supplies). The output of the selector 108 is supplied to the alpha-vector converter 110 and is converted into an original vector form from a power expression of α which is the root of the original polynomial of the RS code.

On the other hand, in the case of variable speed reproduction, the selector 108 is controlled to select the queue buffer 106 side by the variable speed reproduction signal so that the switch 104, the queue buffer 106, the selector 106 and the alpha-vector converter 110 are selected. Only the block ID (ID) and the first data code (IDC) output from the first internal code decoder are reproduced through the path formed as follows. The switch 104 controls to output to the queue buffer 106 only when data supplied from the first internal decoder decoder 88 is not defective by the error signal ERR1. In this case, since the data output from the switch 104 may not be data having a continuous ID, a buffer of a queue method is required. The selection of the error correction path corresponding to the normal reproduction operation and the variable speed reproduction operation is performed by controlling the selector 108 by a signal indicating the variable speed reproduction.

As described above, according to the present invention, at the time of variable speed reproduction, only the minimum data portion for maintaining the critical resolution is used for error correction, thereby not only minimizing the loss of valid data due to mismatch of sync blocks generated during variable speed reproduction but also error correction. This has the advantage of simplifying the process.

Claims (8)

In the error correction encoding method of a digital recording / reproducing apparatus for block-dividing video data of one screen, converting and encoding the video data in units of blocks, and recording the encoded data, the video data in the block unit can be independently decoded. Separating into a first data code and a second data code that can be decoded dependently by the first data code; And adding a first internal code to the first data code, and adding a second internal code to the second data code. The error correction encoding method according to claim 1, wherein the first data code is data reproduced at variable speed reproduction. The video data of one screen is divided into blocks, and the image data is transformed and encoded in each block unit into a first data code that can be independently decoded and a second data code that can be independently decoded, and transform-coded. An error correction decoding method of a digital recording and reproducing apparatus for reproducing digital video data recorded by adding a first internal code error and a second internal code error correction code to each of the two data codes, wherein the first data code and Error correcting and decoding the second data code by means of a first internal code error correcting code and a second internal code error correcting code, respectively. In variable-speed reproduction, only the first data code is corrected by the first internal code error correcting code. Error correction decoding method characterized in that the correction decoding. An error correction encoding apparatus of a digital recording / reproducing apparatus for block-dividing image data of one screen, converting and encoding the image data in units of blocks, and recording the transform-coded data. Separating means for separating the first data code independently having the minimum coefficients to maintain and the second data code having the second coefficients independently having the decodeable coefficients; A first internal encoder that adds a first internal code for error checking and correction to the first data code output from the separating means; A second internal encoder that adds a second internal code for error checking and correction to the second data code output from the separating means; And combining means for outputting the output of the first internal encoder and the output of the second internal encoder in combination. The video data of one screen is divided into blocks, and the image data is transformed and encoded in each block unit into a first data code that can be independently decoded and a second data code that can be independently decoded, and transform-coded. An error correction decoding apparatus of a digital recording / reproducing apparatus for reproducing digital video data recorded by adding a first internal code error and a second internal code error correcting code to each of the two data codes, wherein the read data is converted into the first data code. Separating means for separating into second data codes; A first internal code decoder which performs error checking and correction by a first internal code on the first data code separated by the separating means; A second internal code decoder for performing error checking and correction by a second internal code on the second data code separated by the separating means; And combining means for combining the first data coder and the second data code decoded by the first and second inner code decoders. The method of claim 5, wherein the first internal decoder generates an error flag signal indicating that an uncorrectable error has occurred as a result of error correcting the first data code, and decoding the first internal decoder by the error flag signal. A switch for interrupting the output; And a selector for selecting the output of the switch or the output of the combining means. 7. The error correction and decoding device according to claim 6, further comprising buffer means for buffering the output of said switch between said switch and said selector. 8. The error correction decoding apparatus as claimed in claim 7, wherein the buffer means is a queue buffer.