JPH0555728A - 半導体装置用パツケージの製造方法および構造 - Google Patents

半導体装置用パツケージの製造方法および構造

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Publication number
JPH0555728A
JPH0555728A JP3214917A JP21491791A JPH0555728A JP H0555728 A JPH0555728 A JP H0555728A JP 3214917 A JP3214917 A JP 3214917A JP 21491791 A JP21491791 A JP 21491791A JP H0555728 A JPH0555728 A JP H0555728A
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Japan
Prior art keywords
electrical connection
pattern
semiconductor device
metallized
device package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3214917A
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English (en)
Other versions
JP2967621B2 (ja
Inventor
Hiroyuki Uchida
浩享 内田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3214917A priority Critical patent/JP2967621B2/ja
Priority to US07/936,271 priority patent/US5240588A/en
Publication of JPH0555728A publication Critical patent/JPH0555728A/ja
Application granted granted Critical
Publication of JP2967621B2 publication Critical patent/JP2967621B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Abstract

(57)【要約】 【目的】パッケージ内部の配線パターンを形成するメタ
ライズパターンの延長部分であるめっき引出線を不要と
し、配線間容量を低減することにより集積回路の高周波
動作時における信号漏洩や雑音発生を抑圧して特性を向
上させる。 【構成】メタライズパターン２の電気接続用のリード４
の取付面にニケッル膜８等の金属膜を蒸着する。この金
属膜を電解めっき用の電極１０とする。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体装置用パッケージ
の製造方法および構造に関し、特にピングリッドアレイ
（ＰＧＡ）型の半導体装置用パッケージの製造方法およ
び構造に関する。
【０００２】
【従来の技術】従来のこの種の半導体装置用パッケージ
の製造方法および構造は、図５の部分破断斜視図に示す
ように、電気接続用のリード４は、導電部であるスルー
ホール３を介してセラミック基板１に内臓された配線パ
ターンを形成したメタライズパターン１４に接続され、
メタライズパターン１４はセラミック基板１の側面に達
するように延長して形成されており、ここでタングステ
ン等からなる電解めっき用の電極１５に接続されている
という構成であった。
【０００３】メタライズパターン１４は、図６に示すよ
うに、それぞれスルーホール３を介してリード４に接続
する電極部分であるランド６と、ランド６からセラミッ
ク基板１の側面に達する延長部分であり電極１５に接続
されるめっき引出線１６とを有する配線パターンを有し
ている。
【０００４】次に、従来のＰＧＡ型の半導体装置用パッ
ケージの製造方法について説明する。
【０００５】セラミック基板の焼成作業までは、本発明
に直接間連するもの以外は冗長とならないよう説明を省
略し、焼成作業以降の工程について説明する。
【０００６】まず、セラミック基板１の外部に露出した
メタライズパターン１４に、電極１５およびめっき引出
線１６を介して通電し、ニッケルを電解めっきにより被
着する。次に、リード４を銀銅ろう材によりメタライズ
パッド７に接着する。次に、ニッケルコバルト合金およ
び金を電解めっきにより被着する。最後に電極１５を研
削により除去することにより、メタライズパターン１４
が電気的および物理的に個々に分離され、ＰＧＡ型の半
導体装置用パッケージが完成するというものであった。
【０００７】
【発明が解決しようとする課題】上述した従来の半導体
装置用パッケージの製造方法および構造は、メタライズ
パターンをセラミック基板の側面まで延長しためっき引
出線をこの側面に形成した電解めっき用の電極に接続
し、所要の通電を行なって電解めっきを実施している
が、この延長部分であるめっき引出線により配線パター
ン間の浮遊容量が増加し、集積回路の高周波動作時にお
ける信号漏洩や雑音発生の原因となることにより特性が
劣化するという欠点があった。
【０００８】
【課題を解決するための手段】第一発明の半導体装置用
パッケージの製造方法は、積層した複数のセラミック板
により形成された基板の一主面に設けられた開口部の前
記一主面の反対面に格子状に配列された電気接続用リー
ドを有するピングリッドアレイ型の半導体装置用パッケ
ージの製造方法において、前記電気接続用リードを接続
する配線パターンを形成するメタライズパターンの前記
電気接続用リードの取付面に金属膜を蒸着し、前記金属
膜を電解めっき用の電極とし前記メタライズパターンの
表面および前記電気接続用リードに電解めっきすること
を特徴とするものである。
【０００９】また、第２の発明の半導体装置用パッケー
ジの構造は、積層した複数のセラミック板により形成さ
れた基板の一主面に設けられた開口部の前記一主面の反
対面に格子状に配列された電気接続用リードを有するピ
ングリッドアレイ型の半導体装置用パッケージの構造に
おいて、前記電気接続用リードを接続する配線パターン
を形成するメタライズパターンは前記基板の側面に達し
ていない前記配線パターンを有するものである。
【００１０】
【実施例】次に、本発明の実施例について図面を参照し
て説明する。
【００１１】図１は本発明の半導体装置用パッケージの
製造方法および構造の一実施例を示す部分破断斜視図で
ある。
【００１２】本実施例の半導体装置用パッケージの構造
は、図１に示すように、電気接続用のリード４が、導電
部であるスルーホール３を介して、セラミック基板１に
内臓された配線パターンを形成するメタライズパターン
２に接続されて構成されている。
【００１３】図２は、メタライズパターン２の一部を模
式的に示した模式部分平面図である。
【００１４】メタライズパターン２は、図２に示すよう
に、半導体チップが搭載される開口部５の周辺から、ス
ルーホール３が接続されるランド６に至る範囲に配線パ
ターンが形成され、従来例における側面までの延長部分
であるめっき引出線を有していない。
【００１５】次に、本実施例の製造方法について説明す
る。
【００１６】図３は、本実施例におけるセラミック基板
１のリード４の取付け面を示す部分平面図である。ま
た、図４は電気接続用のリード４のろう付け後の状態を
示す模式部分断面図である。
【００１７】図３において、まず、セラミック基板１の
リード４の取付け面に格子状に設けられたメタライズパ
ッド７を含み、リード４の取付け面全面にニッケル膜８
を蒸着する。この結果、メタライズパッド７は電気的に
短絡状態となる。次に、メタライズパッド上面およびセ
ラミック基板１のコーナ部を除きガラス膜９を被着す
る。セラミック基板１のコーナ部において、ガラス膜９
から露出したニッケル膜の部分が電解めっき用の電極１
０となる。
【００１８】次に図４に示すように、コバール等からな
るリード４を、銀銅等からなるろう材１１によりろう付
けする。次に、電極１０に、めっき浴中で所要の通電の
ための電圧を印加して電解めっきを行なうことにより、
ニッケルコバルトめっき１２、金めっき１３を被着す
る。
【００１９】めっき処理の終了後、弗酸によりガラス膜
９を除去し、希塩酸等によりニッケル膜８を除去するこ
とによりＰＧＡ型の半導体装置用パッケージが完成す
る。
【００２０】なお、弗酸や希塩酸等による処理に対して
は、金めっき１３により保護されるので、特性等に影響
を与えることはない。
【００２１】以上、本発明の実施例を説明したが、本発
明は上記実施例に限られることなく種々の変形が可能で
ある。
【００２２】たとえば、信号伝達用の配線パターン以外
の電源用や接地用の配線パターンにのみめっき引出線を
設けて本実施例と同様に電解めっきすることも、本発明
の主旨を逸脱しない限り適用できることは勿論である。
【００２３】
【発明の効果】以上説明したように、本発明の半導体装
置用パッケージの製造方法および構造は、メタライズパ
ターンの電気接続用リードの取付面に金属膜を蒸着し、
この金属膜を電解めっき用の電極とすることにより、配
線パターンをセラミック基板の側面まで延長しためっき
引出線が不要となるので、配線パターン間の浮遊容量を
低減し、集積回路の高周波動作時における信号漏洩や雑
音発生が抑圧されることにより特性が向上するという効
果を有している。
【図面の簡単な説明】
【図１】本発明の半導体装置用パッケージの製造方法お
よび構造の一実施例を示す部分破断斜視図である。
【図２】本実施例の半導体装置用パッケージの製造方法
および構造におけるメタライズパターンの一部を模式的
に示した模式部分平面図である。
【図３】本実施例におけるセラミック基板のリードの取
付け面を示す部分平面図である。
【図４】電気接続用のリードのろう付け後の状態を示す
模式部分断面図である。
【図５】従来の半導体装置用パッケージの製造方法およ
び構造の一例を示す部分破断斜視図である。
【図６】従来の製造方法および構造におけるメタライズ
パターンの一部を模式的に示した模式部分平面図であ
る。
【符号の説明】
１ セラミック基板 ２，１４ メタライズパターン ３ スルーホール ４ リード ５ 開口部 ６ ランド ７ メタライズパッド ８ ニッケル膜 ９ ガラス膜 １０，１５ 電極 １１ ろう材 １２ ニッケルコバルトめっき １３ 金めっき １６ めっき引出線

Claims (2)

    【特許請求の範囲】
  1. 【請求項１】 積層した複数のセラミック板により形成
    された基板の一主面に設けられた開口部の前記一主面の
    反対面に格子状に配列された電気接続用リードを有する
    ピングリッドアレイ型の半導体装置用パッケージの製造
    方法において、 前記電気接続用リードを接続する配線パターンを形成す
    るメタライズパターンの前記電気接続用リードの取付面
    に金属膜を蒸着し、 前記金属膜を電解めっき用の電極とし前記メタライズパ
    ターンの表面および前記電気接続用リードに電解めっき
    することを特徴とする半導体装置用パッケージの製造方
    法。
  2. 【請求項２】 積層した複数のセラミック板により形成
    された基板の一主面に設けられた開口部の前記一主面の
    反対面に格子状に配列された電気接続用リードを有する
    ピングリッドアレイ型の半導体装置用パッケージの構造
    において、 前記電気接続用リードを接続する配線パターンを形成す
    るメタライズパターンは前記基板の側面に達していない
    前記配線パターンを有することを特徴とする半導体装置
    用パッケージの構造。
JP3214917A 1991-08-27 1991-08-27 半導体装置用パッケージの製造方法 Expired - Fee Related JP2967621B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3214917A JP2967621B2 (ja) 1991-08-27 1991-08-27 半導体装置用パッケージの製造方法
US07/936,271 US5240588A (en) 1991-08-27 1992-08-27 Method for electroplating the lead pins of a semiconductor device pin grid array package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3214917A JP2967621B2 (ja) 1991-08-27 1991-08-27 半導体装置用パッケージの製造方法

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JPH0555728A true JPH0555728A (ja) 1993-03-05
JP2967621B2 JP2967621B2 (ja) 1999-10-25

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