CN100426477C - 扁平塑封球栅阵列封装所用的载板的制造方法及其载板 - Google Patents

扁平塑封球栅阵列封装所用的载板的制造方法及其载板 Download PDF

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CN100426477C
CN100426477C CNB2004100157220A CN200410015722A CN100426477C CN 100426477 C CN100426477 C CN 100426477C CN B2004100157220 A CNB2004100157220 A CN B2004100157220A CN 200410015722 A CN200410015722 A CN 200410015722A CN 100426477 C CN100426477 C CN 100426477C
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张浴
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Riyueguang Packaging & Test (shanghai) Co., Ltd.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明提供一种扁平塑封球栅阵列封装所用的载板的制造方法。传统的载板存在着载板在进行封装之前无法进行电性测试的问题。本发明的制造方法包含下列步骤：准备一双面覆铜板；利用化学蚀刻工艺在该双面覆铜板上形成基片表面线路、焊盘和电镀总线；在所述基片表面线路和所述电镀总线上形成第一保护膜，曝露出需要电镀金的所述焊盘区域；然后放入到电镀液中进行电镀，在所述焊盘上形成电镀层；去除所述第一保护膜；在所述载板表面上形成第二保护膜，曝露出所述电镀总线；利用化学蚀刻工艺除去所述电镀总线。利用本方法制造的载板在封装之前可以进行电性方面的测试，从而确人所有用于封装的载板在电性方面都是合格的。

Description

扁平塑封球栅阵列封装所用的载板的制造方法及其载板
技术领域
本发明涉及集成电路封装工艺，具体地说，涉及扁平塑封球栅阵列封装所用的载板的制造方法。
背景技术
扁平塑封球栅阵列封装是近几年来发展十分迅速的一种半导体封装方式，该封装方法具有外形尺寸小，重量轻，生产效率高，单位成本底的优点，在半导体制造业中有着十分广泛的应用。
下面对现有的扁平塑封球栅阵列封装技术的结构及制造程作一下简述：
首先制备一载板，其结构发图1A和1B所示，该载板包括多个并列的基片100，每个基片100上，被分割成多个器件单元101，器件单元101上设置有与待封装的芯片相适应的焊盘106(如图1B所示)，图中107为基片表层导线。由于金丝键合工艺的需要，每个基片上的表层导线107均延伸到每一个独立单元外的电镀总线104上，再由电镀总线104延伸到基片外缘，以便在载板的制造过程中对焊盘106进行电镀。
如图1A所示，在载板上还设置有定位孔102、注胶口105和释放制造过程中高温所导致的残余应力的切槽103。
在载板制造完成之后，首先将相应的需要进行封装的芯片108(参见图1C)贴装于每一个独立的器件单元101上，然后利用金线键合的技术，用金线109将芯片108与焊盘106相联，完成芯片108的电性连接。
当上述步骤完成之后，自注胶口105注入液状环氧树脂，加热并施加一定压力，使之在高温下固化，这样芯片108就被塑封于固化后的环氧树脂中(如图1D所示)。之后，在基片背面利用高温回流焊植上锡球，最后再利用砂轮切割的方法将上述步骤完成后的半成品延切割道111切开，分割成粒(如图1E所示)，形成封装完毕的单颗器件101，至此完成整个芯片封装。
可以看出这样的封装方法，据有生产效率高，单位成本低的优点。但是，由于基片上金丝键合工艺所需要的焊盘107有电镀金的工艺需要，所以每一根与焊盘106相连的导线都必须延伸到单个器件单元101的外缘，并与单元外的电镀总线104相连，而这样的作法使得整个载板，在切粒完成之前无法进行电性测试，也就是说，在芯片封装完成之前无法确认载板与引线键合后是否有缺陷。虽然在品质管理系统高度发达的今天，太多数的半导体加工企业，可以将生产过程中的变异降低到非常小的程度，但是要达到100％的良率几乎是不可能的，这样就产生了下述问题，倘若由于载板在封装前无法确认是否有缺陷的存在，将造成一个功能没有问题的芯片贴装在一片有缺陷的载板上，这样一种情况的发生，从而导致次品的出现。
众所周知，在半导体器件的生产过程中，芯片的成本要比整个封装的成本高出许多倍，这种缺陷的发生造成了不必要的浪费从而导致生产成本的大幅攀升。
发明内容
因此，本发明的目的在于提供一种扁平塑封球栅阵列封装所用的载板的制造方法，通过这种方法制造的载板可以在完成芯片封装之前，对载板进行电性测试，以减少由于载板的电性问题造成封装后的集成片的损耗。
本发明的另一个目的在于提供一种利用本发明的扁平塑封球栅阵列封装所用的载板的制造方法制造的载板，这种载板可以在完成芯片封装之前，对其进行电性测试，以减少由于载板的电性问题造成封装后的集成片的损耗。
根据上述目的，本发明的扁平塑封球栅阵列封装所用的载板的制造方法包含下列步骤：
准备一双面覆铜板；
利用化学蚀刻工艺在该双面覆铜板上形成基片表面线路、焊盘和电镀总线；
在所述基片表面线路和所述电镀总线上形成第一保护膜，曝露出需要电镀金的所述焊盘区域；
然后放入到电镀液中进行电镀，在所述焊盘上形成电镀层；
去除所述第一保护膜；
在所述载板表面上形成第二保护膜，曝露出所述电镀总线；
利用化学蚀刻工艺除去所述电镀总线。
在上述的扁平塑封球栅阵列封装所用的载板的制造方法中，还包含在基板上涂覆阻焊剂的步骤。
本发明还提供一种扁平塑封球栅阵列封装所用的载板，包含多个并列的基片，每个基片上具有多个器件单元，每个器件单元上设置有与待封装的芯片相适应的焊盘和基片表层导线；在基片上还设置有定位孔、注胶口和释放制造过程中高温所导致的残余应力的切槽。
如上所述，由于本发明制造的载板除去了电镀所用的电镀总线，使得载板上各个器件单元中的基片表层导线和焊盘不再通过电镀总线相连，因此，可以对载板进行电性方面的测试，从而确保所有用于封装的载板在电性方面都是合格的，从而避免了由于载板上的电性缺陷造成整个一颗集成电路产品失效的情况发生。
附图说明
图1A是传统的载板的示意图；
图1B是图1A所述的载板的局部放大图；
图1C-1E示出了芯片封装的各个过程；
图2示出了本发明的载板的示意图；
图3A-3I示出了本发明的载板的制造方法的各个过程的示意图。
具体实施方式
如图2所示，图2示出了本发明的扁平塑封球栅阵列封装所用的载板的结构示意图。与图1所示的传统的载板相比，两者之间的差异本发明的载板完全去除了电镀总线。其它的结构与传统的基本相同。也包含有多个并列的基片200，每个基片200上，被分割成多个器件单元201，器件单元201上设置有与待封装的芯片相适应的焊盘206和基片表层导线207。在载板上还设置有定位孔202、注胶口205和释放制造过程中高温所导致的残余应力的切槽203。
下面将详细描述图2所示的载板的制造方法，有关本发明的载板的进一步结构将通过下面的描述变得更为清楚。
首先，准备一制造载板所用的双面覆铜板，如图3A所示，图中221为该双面覆铜板的芯材，222为芯材两面所覆的铜簿。
然后，参见图3B所示，在双面覆铜板两面覆以显影用的干膜223，之后进行曝光显影，将光罩224上的图像转移到干膜223上，由于干膜223是一种光固化的化学物质，在受到紫光照射的部分发生光固化的化学变化，形成固化图形225，而没有受到光线照射的部分则被化学药水洗去。之后将覆有固化图形的双面覆铜板，浸泡于化学蚀刻剂中(如图3C所示)。由于图化的干膜225据有抗蚀性，这样没有干膜225覆盖的铜就会被化学蚀刻液腐蚀掉。这样就形成了基片表面线路207、焊盘206和电镀总线204(如图3D和3E所示)。这里所采用工艺即为传统的化学蚀刻的方法。
待上述步骤完成之后，去除了上述的干膜223，然后与制作表面线路207一样，在不需电镀金的区域(即基片表面线路207和电镀总线204)上形成一层保护膜226，而把需要电镀金的区域(即焊盘206)曝露出来，再放入电镀液里电镀镍金(如图3F和3G所示)。
电镀镍金完成之后，再在载板表面上形成一层保护膜，在电镀总线204上开出窗口208，将单个器件单元边缘的电镀总线204曝露出来(如图3H)，同上述步骤一样，采用化学蚀刻的方法将电镀总线去除(如图3I所示)从而完成本发明的载板的制作。另外，还可以在完成的载板上下表面涂上阻焊剂。

Claims (2)

1、一种扁平塑封球栅阵列封装所用的载板的制造方法包含下列步骤：
准备一双面覆铜板；
利用化学蚀刻工艺在该双面覆铜板上形成基片表面线路、焊盘和电镀总线；
在所述基片表面线路和所述电镀总线上形成第一保护膜，曝露出需要电镀金的所述焊盘区域；
然后放入到电镀液中进行电镀，在所述焊盘上形成电镀层；
去除所述第一保护膜；
在所述载板表面上形成第二保护膜，曝露出所述电镀总线；
利用化学蚀刻工艺除去曝露出的电镀总线。
2、如权利要求1所述的扁平塑封球栅阵列封装所用的载板的制造方法，其特征在于，还包含在载板上涂覆阻焊剂的步骤。
CNB2004100157220A 2004-01-09 2004-01-09 扁平塑封球栅阵列封装所用的载板的制造方法及其载板 Expired - Fee Related CN100426477C (zh)

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US5729894A (en) * 1992-07-21 1998-03-24 Lsi Logic Corporation Method of assembling ball bump grid array semiconductor packages
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Publication number Priority date Publication date Assignee Title
US5240588A (en) * 1991-08-27 1993-08-31 Nec Corporation Method for electroplating the lead pins of a semiconductor device pin grid array package
US5729894A (en) * 1992-07-21 1998-03-24 Lsi Logic Corporation Method of assembling ball bump grid array semiconductor packages
US5635671A (en) * 1994-03-16 1997-06-03 Amkor Electronics, Inc. Mold runner removal from a substrate-based packaged electronic device
US6372553B1 (en) * 1998-05-18 2002-04-16 St Assembly Test Services, Pte Ltd Disposable mold runner gate for substrate based electronic packages
US6214645B1 (en) * 1998-05-27 2001-04-10 Anam Semiconductor, Inc. Method of molding ball grid array semiconductor packages
US20020109219A1 (en) * 2001-02-13 2002-08-15 Yang Chung Hsien Semiconductor package with heat sink having air vent

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