JPH0555367A - シリコン基板の埋め込み選択酸化方法およびこの方法による集積回路 - Google Patents

シリコン基板の埋め込み選択酸化方法およびこの方法による集積回路

Info

Publication number
JPH0555367A
JPH0555367A JP4020246A JP2024692A JPH0555367A JP H0555367 A JPH0555367 A JP H0555367A JP 4020246 A JP4020246 A JP 4020246A JP 2024692 A JP2024692 A JP 2024692A JP H0555367 A JPH0555367 A JP H0555367A
Authority
JP
Japan
Prior art keywords
trench
silicon
etching
nitriding
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4020246A
Other languages
English (en)
Japanese (ja)
Inventor
Alain Straboni
アラン・ストラボニ
Kathy Barla
キヤツシー・バーラ
Bernard Vuillermoz
ベルナール・ヴイユルモズ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CENTRE NAT ETD TELECOMM
Orange SA
France Telecom R&D SA
Original Assignee
CENTRE NAT ETD TELECOMM
France Telecom SA
Centre National dEtudes des Telecommunications CNET
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CENTRE NAT ETD TELECOMM, France Telecom SA, Centre National dEtudes des Telecommunications CNET filed Critical CENTRE NAT ETD TELECOMM
Publication of JPH0555367A publication Critical patent/JPH0555367A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/318—Inorganic layers composed of nitrides
    • H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
JP4020246A 1991-02-07 1992-02-05 シリコン基板の埋め込み選択酸化方法およびこの方法による集積回路 Withdrawn JPH0555367A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9101381A FR2672731A1 (fr) 1991-02-07 1991-02-07 Procede d'oxydation localisee enterree d'un substrat de silicium et circuit integre correspondant.
FR9101381 1991-02-07

Publications (1)

Publication Number Publication Date
JPH0555367A true JPH0555367A (ja) 1993-03-05

Family

ID=9409445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4020246A Withdrawn JPH0555367A (ja) 1991-02-07 1992-02-05 シリコン基板の埋め込み選択酸化方法およびこの方法による集積回路

Country Status (4)

Country Link
US (1) US5229318A (US20080293856A1-20081127-C00150.png)
EP (1) EP0498717A1 (US20080293856A1-20081127-C00150.png)
JP (1) JPH0555367A (US20080293856A1-20081127-C00150.png)
FR (1) FR2672731A1 (US20080293856A1-20081127-C00150.png)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920022380A (ko) * 1991-05-18 1992-12-19 김광호 반도체장치의 소자분리방법
KR960005553B1 (ko) * 1993-03-31 1996-04-26 현대전자산업주식회사 필드산화막 형성 방법
US5494857A (en) * 1993-07-28 1996-02-27 Digital Equipment Corporation Chemical mechanical planarization of shallow trenches in semiconductor substrates
KR970003731B1 (ko) * 1993-10-14 1997-03-21 엘지반도체 주식회사 반도체 장치의 소자 격리막 제조방법
KR0136518B1 (en) * 1994-04-01 1998-04-24 Hyundai Electroncis Ind Co Ltd Method for forming a field oxide layer
US5470783A (en) * 1994-06-06 1995-11-28 At&T Ipm Corp. Method for integrated circuit device isolation
DE19525072C2 (de) * 1995-07-10 2002-06-27 Infineon Technologies Ag Integrierte Schaltungsanordnung, bei der ein erstes Bauelement an einer Hauptfläche eines Halbleitersubstrats und ein zweites Bauelement am Grabenboden angeordnet sind, und Verfahren zu deren Herstellung
US5661073A (en) * 1995-08-11 1997-08-26 Micron Technology, Inc. Method for forming field oxide having uniform thickness
BR9611124A (pt) * 1995-10-26 1999-05-11 Sanofi Sa Utilização da 1-(2-naft-2-iletil)-4- (3-trifluorometifenil) -1,2,3,6-tetraidropiridina ou um dos seus sais de adição com ácidos farmaceuticamente aceitáveis composição farmacéutica e método de tratamento da esclerose lateral amiotrófica
US5672538A (en) * 1995-12-04 1997-09-30 Taiwan Semiconductor Manufacturing Company, Ltd Modified locus isolation process in which surface topology of the locos oxide is smoothed
US5726093A (en) * 1995-12-06 1998-03-10 Taiwan Semiconductor Manufacturing Company Ltd. Two-step planer field oxidation method
US5789305A (en) * 1997-01-27 1998-08-04 Chartered Semiconductor Manufacturing Ltd. Locos with bird's beak suppression by a nitrogen implantation
US5721174A (en) * 1997-02-03 1998-02-24 Chartered Semiconductor Manufacturing Pte Ltd Narrow deep trench isolation process with trench filling by oxidation
US6080665A (en) * 1997-04-11 2000-06-27 Applied Materials, Inc. Integrated nitrogen-treated titanium layer to prevent interaction of titanium and aluminum
US6033997A (en) * 1997-12-29 2000-03-07 Siemens Aktiengesellschaft Reduction of black silicon in semiconductor fabrication
US5940718A (en) * 1998-07-20 1999-08-17 Advanced Micro Devices Nitridation assisted polysilicon sidewall protection in self-aligned shallow trench isolation
US6521959B2 (en) * 1999-10-25 2003-02-18 Samsung Electronics Co., Ltd. SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same
US6613651B1 (en) * 2000-09-05 2003-09-02 Lsi Logic Corporation Integrated circuit isolation system
JP2005183783A (ja) * 2003-12-22 2005-07-07 Seiko Epson Corp 半導体装置の製造方法
DE102004044222A1 (de) * 2004-09-14 2006-03-16 Robert Bosch Gmbh Mikromechanisches Bauelement und entsprechendes Herstellungsverfahren
US8772902B2 (en) 2012-04-19 2014-07-08 International Business Machines Corporation Fabrication of a localized thick box with planar oxide/SOI interface on bulk silicon substrate for silicon photonics integration
US9236287B2 (en) 2012-11-02 2016-01-12 GLOBALFOUNDIES Inc. Fabrication of localized SOI on localized thick box lateral epitaxial realignment of deposited non-crystalline film on bulk semiconductor substrates for photonics device integration
US10410798B2 (en) * 2014-10-17 2019-09-10 Teknologian Tutkimuskeskus Vtt Oy Blank suitable for use as a body of a supercapacitor, a supercapacitor, and a method of manufacturing a porous silicon volume

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1437112A (en) * 1973-09-07 1976-05-26 Mullard Ltd Semiconductor device manufacture
EP0052948A1 (en) * 1980-11-24 1982-06-02 Motorola, Inc. Oxide isolation process
US4563227A (en) * 1981-12-08 1986-01-07 Matsushita Electric Industrial Co., Ltd. Method for manufacturing a semiconductor device
JPS58169935A (ja) * 1982-03-30 1983-10-06 Matsushita Electronics Corp 半導体装置の製造方法
NL187373C (nl) * 1982-10-08 1991-09-02 Philips Nv Werkwijze voor vervaardiging van een halfgeleiderinrichting.
JPS59214237A (ja) * 1983-05-20 1984-12-04 Toshiba Corp 半導体装置の製造方法
WO1988010510A1 (en) * 1987-06-15 1988-12-29 Ncr Corporation Semiconductor field oxide formation process
US4986879A (en) * 1987-06-15 1991-01-22 Ncr Corporation Structure and process for forming semiconductor field oxide using a sealing sidewall of consumable nitride
FR2648956A1 (fr) * 1989-06-23 1990-12-28 Commissariat Energie Atomique Procede de fabrication de l'oxyde de champ d'un circuit integre sur du silicium

Also Published As

Publication number Publication date
US5229318A (en) 1993-07-20
FR2672731B1 (US20080293856A1-20081127-C00150.png) 1997-03-07
FR2672731A1 (fr) 1992-08-14
EP0498717A1 (fr) 1992-08-12

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