JPH0553977A - Information processing system - Google Patents

Abstract

PURPOSE:To easily detect the fault of a bus adapter by providing a storage circuit and a comparator circuit so as to compare data on a memory bus with data on an input/output bus in the case of data transfer between a main storage device and an input/output device. CONSTITUTION:A bus adapter 6 is equipped with a storage circuit 63 to temporarily store the data on the bus and a comparator circuit 64 to compare the stored data with the data on the other bus, and selectors 61 and 62 are provided to input the data on the bus to both circuits 63 and 64. Namely, the bus adapter 6 monitors the operation of exchanging the data between a main storage device 5 on a memory bus 1 and an input/output device 9 on an additive input/output bus 3 through an additive bus adapter 8, and the fault of the additive bus adapter 8 is easily cut off by comparing both values of the data on the memory bus 1 and the data on the additive input/output bus 3.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an information processing system, and more particularly to an information processing system in which a memory bus and an input / output bus are connected via a bus adapter.

[0002]

2. Description of the Related Art Generally, when a memory bus to which a main storage device is connected and an input / output device such as a magnetic disk device or a printer are connected, they are connected via a bus adapter. A conventional information processing system including the bus adapter will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of a conventional information processing system.

In the figure, an arithmetic processing unit 4 and a main storage unit 5 are connected to a memory bus 1. An input / output device 7 is connected to the basic input / output bus 2. Then, the buses 1 and 2 are connected via the bus adapter 6, whereby data is exchanged between the main storage device 5 and the input / output device 7.

On the other hand, in this system, an additional input / output bus 3 is connected to the bus 1 via an additional bus adapter 8 in addition to the basic input / output bus 2. As a result, data is exchanged between the main storage device 5 and the input / output device 7.

That is, in the conventional information processing system,
Data is transferred between the main storage device and each input / output device by relaying the buses with each other by a bus adapter. However, in the above-described conventional system, when the arithmetic processing unit activates the input / output device on the additional input / output bus, information is transferred between the main storage device and the input / output device. At that time, since there was no function of monitoring these series of operations, there was a drawback that it was difficult to investigate the cause when a failure occurred.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and an object thereof is to provide an information processing system capable of detecting a fault due to a bus adapter.

[0007]

An information processing system according to the present invention is an information processing system in which a memory bus to which a main storage device is connected and an input / output bus to which an input / output device is connected are connected via a bus adapter. A means for comparing the data on the memory bus with the data on the input / output bus at the time of data transfer between the main memory device and the input / output device. Is detected.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of an information processing system according to the present invention, and the same portions as those in FIG. 2 are designated by the same reference numerals. In the figure, in the system of the present embodiment, a configuration for monitoring the extension bus adapter 8 is added in the bus adapter 6. That is, a storage circuit 63 for temporarily storing the data on the bus and a comparison circuit 64 for comparing the stored data with the data on another bus are provided in the bus adapter 6, and both circuits are further provided. Selectors 61 and 62 for inputting data on the buses to 63 and 64 are also provided. That is, in the system of this embodiment, the operation of transmitting and receiving data between the main storage device 5 on the memory bus 1 and the input / output device 9 on the additional input / output bus 3 via the additional bus adapter 8 is performed. The bus adapter 6 is monitoring, and by comparing the values of both the data on the memory bus 1 and the data on the additional input / output bus 3, it is easy to isolate a fault by the additional bus adapter 8.

To perform such monitoring, the bus adapter 6
Has a built-in memory circuit 63. The storage circuit 63 can select and store the data on the memory bus 1 or the additional input / output bus 3 by the selector 61. On the contrary, the comparison circuit 64 compares the data on the additional input / output bus 3 or the memory bus 1 selected by the selector 62 with the storage circuit 6
3 is a circuit for comparing the stored data.

In such a configuration, when the arithmetic processing unit 4 activates the I / O device 9 on the additional I / O bus 3, the I / O device 9 on the additional I / O bus 3 and the main storage device are passed through the additional bus adapter 8. Data is transferred to and from. First, a case where data flows from the main storage device 5 to the input / output device 9 on the additional input / output bus 3 via the additional bus adapter 8 will be described. The data output from the main storage device 5 is
The data enters the additional bus adapter 8 via the memory bus 1. At this time, the data on the memory bus 1 is selected by the selector 61 incorporated in the bus adapter 6 and stored in the memory circuit 63. On the other hand, when the data relayed by the expansion bus adapter 8 enters the input / output device 9 via the expansion input / output bus 3, the selector 62 in the bus adapter 6 selects the data of the expansion input / output bus 3 and the comparison circuit 64 The data stored in the memory circuit 63 is compared with the data selected by the selector 62. As a result, when the compared data are different,
The comparison circuit 64 issues an error signal to a host device (not shown).

Next, the input / output device 9 on the additional input / output bus 3
A case where data flows from the main storage device 5 to the main storage device 5 via the extension bus adapter 8 will be described. The data exits the input / output device 9 on the extension I / O bus 3 and enters the extension bus adapter 8 via the extension I / O bus 3. At this time, the data on the extension I / O bus 3 is transferred to the selector 61 in the bus adapter 6. It is selected and stored in the storage circuit 63.

On the other hand, the data output from the extension bus adapter 8 enters the main storage device 5 via the memory bus 1. At this time, the data on the memory bus 1 is transferred to the selector 6 in the bus adapter 6.
2 selects, and the comparison circuit 64 compares the data stored in the storage circuit 63 with the data selected by the selector 62. As a result of the comparison, if the two data do not match, that is, if they are different, the comparison circuit 64 sends an error signal to a host device (not shown). When the comparison result shows a match, the extension bus adapter 8 is normal.

That is, the conventional system (FIG. 2) does not have means for monitoring the extension bus adapter 8, and therefore, even if a fault occurs in the extension bus adapter 8, it is difficult to investigate the cause. In the present system, by comparing the data of both the memory bus 1 and the additional input / output bus 3 during which the bus adapter 6 is transferring data, the failure due to the additional bus adapter 8 can be easily identified. Further, by monitoring the additional bus adapter 8, it is possible to improve maintainability.

Even if the circuits 63, 64 for comparing data on the buses are provided outside the bus adapter 6, the same effect can be obtained. Further, in order to detect the failure of the bus adapter 6, a similar comparison circuit 64 or the like may be provided, which makes maintenance easier.

[0016]

As described above, according to the present invention, by comparing the data of the memory bus and the data of the input / output bus,
There is an effect that it is possible to easily isolate a failure by the extension bus adapter and improve maintainability.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an information processing system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional information processing system.

[Explanation of symbols]

 1 Memory Bus 2 Basic Input / Output Bus 3 Expansion Input / Output Bus 5 Main Storage Device 7, 9 Input / Output Device 61, 62 Selector 63 Storage Circuit 64 Comparison Circuit

Claims (1)

[Claims] 1. An information processing system comprising a memory bus connected to a main storage device and an input / output bus connected to an input / output device via a bus adapter, wherein the main storage device and the input / output device are connected to each other. A means for comparing the data on the memory bus and the data on the input / output bus at the time of data transfer with the output device is provided, and the failure of the bus adapter is detected based on the comparison result. A characteristic information processing system.