JP3297515B2 - Multiplex transmission equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex transmission device mounted on a vehicle such as an automobile for transmitting an electric signal.

[0002]

2. Description of the Related Art Conventionally, a multiplex transmission apparatus mounted on a vehicle such as an automobile includes a transmission apparatus for transmitting desired data as a multiplex signal and a multiplex path for transmitting the multiplex signal transmitted by the transmission apparatus. Temporarily storing the data transmitted from the multiple paths in a reception buffer, and then transmitting the data to the CPU;
There is a device having a receiving device (for example,
-182132). Such a conventional multiplex transmission apparatus has a CPU as shown in FIG.
1, a transmission device 2 that reads transmission data from the transmission device 1, converts the transmission data into a multiplexed signal X, and receives the multiplexed signal transmitted by the transmission device 2 and transmits the multiplexed signal to the CPU 1.
It comprises a multiplex path 4 connecting the transmitting device 2 and the receiving device 3. The transmission device 2 includes a transmission buffer 5, a control circuit 6, a CRC
The receiving device 3 includes a control circuit 8, a CR
It has a C checker 9 and a reception buffer 10. FIG. 2 shows the communication IC constituting the receiving device 3 in more detail. The communication IC is usually a serial / parallel converter 1
1, an error detection circuit 12, a reception control circuit 13, and
It has a pair of receiving buffers 10a and 10b arranged in series. The reason why the pair of receiving buffers 10a and 10b are provided is to increase the capacity of the receiving buffer. For example, when two pieces of information are transmitted almost simultaneously, if there are two reception buffers 10a and 10b, both pieces of information can be held until the CPU 1 reads these pieces of information.

[0003]

In the multiplex transmission apparatus having such a configuration, it can be checked by the CRC checker 9 whether or not the data flowing through the multiplex path 4 is a predetermined data. The CPU 1 can check whether the data read by the transmission node 2 is correct or not. However, when the data is received by the reception buffer 10a,
While the data is held at 10b, radio noise or the like may be mixed and the contents of the data may change. The data once input to the receiving buffers 10a and 10b is directly taken into the CPU 1 and processed, so that
If the data held in 0a and 10b is not the expected data, the CPU 1 processes erroneous data, and the reliability of the entire multiplex transmission system may be reduced. Therefore, an object of the present invention is to determine whether or not data held in a reception buffer is the desired data without reducing the processing performance of the CPU, and to determine whether the data is the desired data. It is an object of the present invention to provide a multiplex transmission device which can transmit only this data to a CPU.

[0004]

In order to achieve the above object, a multiplex transmission apparatus according to the present invention comprises a transmitting apparatus for transmitting desired data as a multiplex signal and transmitting the multiplex signal transmitted by the transmitting apparatus. After temporarily storing the multi-path to be transmitted and the data transmitted from the multi-path in a reception buffer,
A multiplex transmission device having a reception device for transmitting to a PU, wherein at least two reception buffers are provided in parallel, and when the data received by the reception buffers respectively match, the data is transmitted to the CPU. Features.

[0005]

As described above, desired data is simultaneously inputted to a plurality of reception buffers provided in parallel with each other, and the data held in the individual reception buffers are compared. Since the data is transmitted to the CPU, the possibility that erroneous data is read and processed by the CPU can be reduced. If the data held in the reception buffer does not match, the data is fetched again into the reception buffer, and if the data matches, the data can be transmitted to the CPU. Further, when the data in at least three reception buffers do not match, a failed reception buffer can be detected by comparing the data in each reception buffer. Therefore, transmission to the failed reception buffer is prohibited, and Malfunction can be prevented.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 3 to 6 show a first embodiment of the present invention. In this embodiment, as shown in FIG. 3, a serial / parallel converter 11 and an error detection Circuit 12, reception control circuit 1
3, a receiving buffer 14 is connected to the serial / parallel converter 11, and a pair of receiving buffers 15 and 16 are arranged in parallel on the downstream side.
These receiving buffers 15 and 16 are individually connected to the receiving buffer 14. On the downstream side of the reception buffers 15 and 16, a match detection circuit 17 is provided.
5 and 16 are individually connected to the coincidence detection circuit 17.
The match detection circuit 17 is connected to the CPU 1 so that the data held in the reception buffers 14, 15, and 16 cannot be transmitted to the CPU 1 unless the data passes through the match detection circuit 17.

Hereinafter, the operation of the first embodiment will be described separately for a case where the data taken into the reception buffer is normal and a case where the data is abnormal. If the data is normal: As shown in FIG. 4, (1) if the reception buffer 14 is writable at the time of data reception, the data is written to the reception buffer 14. Then, the reception buffer 14 is write-protected. (2) Receive buffer 1
If 5 and 16 are writable, receive buffer 1
4 is transmitted to the reception buffers 15 and 16, and the reception buffer 14 is enabled for writing. At this time, the reception buffers 15 and 16 are write-protected. (3) CPU1
If the data is read out of the receiving buffers 15 and 16 from these, these data are compared by the coincidence detecting circuit 17, and if both data coincide, the data is transmitted to the CPU 1. Then, the reception buffers 15 and 16 are permitted to be written.

When the data is abnormal, the operation is as follows. As shown in FIG. 5, (4) when the data in the receiving buffers 15 and 16 do not match in the comparison in the above (3), the receiving buffers 15 and 16 are permitted to write, and
The abnormality is notified to PU1. (5) The communication IC transmits a transmission request frame to the transmission nodes of the reception buffers 15 and 16 according to an instruction from the CPU 1. At this time, the reception buffer 14
If the data is also transferred, the transmission request frame is also transmitted to the transmission node of this data. (6) The next reception frame is transferred to the reception buffers 14, 15, and 16, and the coincidence detection circuit 17 compares the data in each of the reception buffers 14, 15, and 16. If the data matches, the data is transmitted to the CPU 1, the receiving buffers 14, 15, and 16 are permitted to write, and the normal data transfer method is returned. If the data does not match, a failed receiving buffer (the receiving buffer 15 in FIG. 5) is detected, and normal data is transmitted to the CPU 1. At this time, as shown in FIG. 6, data is not transmitted to the failed receiving buffer 15 and data matching of the receiving buffer 15 is not performed, and data is received only by the normal receiving buffers 14 and 16. (7) If there is a mismatch here, a transmission request may be made again, and if both do not match, the data reception of (6) may be performed. However, in this case, a warning is issued that the reception buffer 15 is out of order.
When the importance of the data is high, the control of the transmission node may be prohibited when a failed reception buffer 15 is detected, and a warning may be issued.

Next, a second embodiment of the present invention will be described with reference to FIGS. The feature of this embodiment is that the reception buffer 14 and the reception buffer 1 are provided between the serial / parallel converter 11 and the coincidence detection circuit 17 as shown in FIG.
8 and the receiving buffer 15 and the receiving buffer 16 are arranged in parallel. The reception buffer 14 and the reception buffer 15 are arranged in series, and the reception buffer 18 and the reception buffer 16 are also arranged in series.

Hereinafter, the operation of the second embodiment will be described separately for a case where the data taken into the reception buffer is normal and a case where the data is abnormal. If the data is normal,
As shown in FIG. 7, (8) at the time of data reception, if the reception buffers 14 and 18 are writable, data is written into the reception buffers 14 and 18 and the reception buffer 1
4 and 18 are write protected. (9) Next, if the reception buffers 15 and 16 are writable, the reception buffer 1
The data of Nos. 4 and 18 are transmitted to the receiving buffers 15 and 16, respectively, and the receiving buffers 14 and 18 are permitted to write, and the receiving buffers 15 and 16 are prohibited from writing. (10) If the CPU 1 reads data, the data in the reception buffers 15 and 16 are read from the match detection circuit 1
If the data match, the data is transmitted to the CPU 1 as normal data. Then, the receiving buffers 15 and 16
Write permission.

When the data is abnormal, the operation is as follows. As shown in FIG. 8, (11) if the data in the reception buffers 15, 16 does not match in the comparison in the above (10), the reception buffers 15, 16, 14, 18 are permitted to write, and the CPU 1 is notified of the abnormality. I do. (12) CPU
In response to the instruction 1, the communication IC transmits a transmission request frame to the data transmission nodes of the reception buffers 15 and 16. At this time, if the data is also transferred to the reception buffers 14 and 18, the transmission request frame is also transmitted to the transmission node of the data. (13) The next reception frame is transferred to the reception buffers 15, 16, 14, and 18, and the match detection circuit 17 compares the data. If the data match, CPU 1
To each buffer 15, 16, 14, 18
Is enabled for writing, and the normal data transmission method is returned.
However, if the data does not match, the failed reception buffer (the reception buffer 15 in the case of FIG. 8) is detected, and normal data is transmitted to the CPU 1 as shown in FIG. No data is transmitted to the 15 side, and no match is detected. Normal receive buffer 1
Data reception is performed only by 6 and 18. At this time, if the data does not match, a transmission request may be made again, and when the mismatch is determined twice, the above-described data reception may be performed. However, a warning that the reception buffer 15 has failed is issued. When the importance of the data is high, the control of the transmission node may be prohibited when a failed reception buffer 15 is detected, and a warning may be issued.

[0012]

As described above, according to the multiplex transmission apparatus of the present invention, desired data is simultaneously input to a plurality of reception buffers provided in parallel with each other, and the data held in each reception buffer is input. Is compared, the data is transmitted to the CPU when the data match, so that the possibility that erroneous data is read and processed by the CPU can be reduced. Further, when the data held in the reception buffer does not match, the data is fetched into the reception buffer again, and if the data matches, the data can be transmitted to the CPU. This has a great effect on accurate data processing by the CPU. Further, when the data in at least three reception buffers do not match, a failed reception buffer can be detected by comparing the data in each reception buffer. Therefore, transmission to the failed reception buffer is prohibited, and Malfunction can be prevented. Therefore, the reliability of the multiplex transmission system can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration of a multiplex transmission device.

FIG. 2 is a configuration diagram of a conventional receiving device.

FIG. 3 is a configuration diagram of a receiving device according to the first embodiment of the present invention.

FIG. 4 is a flowchart when the receiving device of FIG. 3 sends normal data.

5 is a flowchart when the receiving apparatus of FIG. 3 detects a data abnormality.

FIG. 6 is another flowchart when the receiving apparatus of FIG. 3 detects a data abnormality.

FIG. 7 is a schematic configuration diagram of a receiving device according to a second embodiment of the present invention, and is a flowchart when the receiving device sends normal data.

8 is a flowchart when the receiving apparatus of FIG. 7 detects a data abnormality.

9 is another flowchart when the receiving apparatus of FIG. 7 detects a data abnormality.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... CPU 2 ... Transmitting device 3 ... Receiving device 4 ... Multipath 11 ... Serial / parallel converter 12 ... Error detection circuit 13 ... Receiving control circuit 14, 15, 16 ... Receiving buffer 17 ... Matching detecting circuit 18 ... Receiving buffer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 29/14 H04L 1/00 H04L 13/08 H04L 12/24 H04L 12/26 H04L 12/28

Claims (3)

(57) [Claims] 1. A transmitting apparatus for transmitting desired data as a multiplex signal, a multiplex path for transmitting the multiplex signal transmitted by the transmitting apparatus, and temporarily storing the data transmitted from the multiplex path in a receiving buffer. And then transmit it to the CPU,
A multiplex transmission device having a reception device, wherein at least two reception buffers are provided in parallel, and when the data received by the reception buffers match, the data is transmitted to the CPU. Transmission equipment. 2. The multiplex transmission apparatus according to claim 1, wherein when the data in the reception buffer does not match, the transmission apparatus is instructed to transmit the data again, and the data transmitted again is received by the reception apparatus. The multiplex transmission device that receives data in at least three reception buffers including a buffer, and transmits the data to the CPU when the data in the at least three reception buffers match. 3. The multiplex transmission apparatus according to claim 2, wherein when the data in the at least three reception buffers do not match, a failure reception buffer is detected from the reception buffers, and the data is transmitted to the failure reception buffer. The multiplex transmission device for inhibiting transmission.