JPH0779240A - Buffer with comparator - Google Patents

Abstract

PURPOSE:To facilitate the constitution of a multiplexed data processing system for comparing the values of the output signals of respective modules while a data processing system is operated, defining that an error is present when a difference is present and performing a processing by providing the plural modules for a certain target related to the improvement of the reliability of the data processing system. CONSTITUTION:By a comparator 108 provided in a bus buffer for connecting the modules and a bus inside a system, the values of signals 103 inside the modules and the values of the signals 102 on the bus are compared. The respective plural modules provided for multiplexing simultaneously output the results on the bus, compare the values of the signals of their own with the values of the signals on the bus, define that the error is present when the difference is present and perform the processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus buffer for a data processing system and a system configuration system using the same.

[0002]

2. Description of the Related Art In a conventional data processing system,
Multiplexes the system by simultaneously using multiple modules with similar functions for increased reliability, collects the results output by those modules and compares them against each other to make sure that the results match It uses modules.

Therefore, the multiplexed data processing system has a problem in that the structure is complicated and the cost is increased.

[0004]

SUMMARY OF THE INVENTION It is an object of the invention to realize a multiplexing of data processing systems in a simple and inexpensive manner.

[0005]

The present invention achieves the above object by providing a comparator in a bus buffer connecting a module and a bus.

[0006]

In the system multiplexed by using the bus buffer of the present invention, the value of the signal in the module and the value of the corresponding signal on the bus are compared by the comparator provided in the bus buffer connecting the module and the bus. , Each module provided for multiplexing outputs the result on the bus at the same time, and each compares the value of its own signal with the value of the corresponding signal on the bus. In some cases, it is treated as if there was an error.

Since it is possible to detect that the results output by a plurality of modules match each other by detecting that the value of the signal on the bus and the value of the signal inside the module match, it has been conventionally required. Multiplexing of the system is realized without using a comparison module that collects the output results of the modules and compares them with each other to confirm that the results match.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a logic circuit of a bus transceiver with a comparator which is an embodiment of the present invention. FIG. 2 shows a logic circuit of a bus buffer with a comparator which is an embodiment of the present invention. All of these are integrated into an IC, and FIG. 3 shows an output equivalent circuit of the bus buffer and the comparator used in this embodiment.

In this embodiment, as shown in FIG. 1, the bus transceiver with comparator is a 1-bit data transceiver 10.
Eight ICs 1 are packaged in one IC package 1000. The 1-bit data transceiver 101 has a bus signal 102, a module signal 103, and a reception permission signal 10.
4 and a transmission permission signal 105.

Reference numeral 106 is a bus receiver for receiving the value of the signal on the system bus, and 107 is a bus transmitter for sending out the signal in the module to the bus. These are activated / deactivated by the reception permission signal of 104 and the transmission permission signal of 105, respectively, and when they are inactive, their outputs are in a high impedance state and are electrically equivalent to not being connected to a circuit. .

Reference numeral 108 denotes a comparator, which outputs a logical value of 1 only when the signal value on the system bus and the logical value in the module match. This operation is the same as the exclusive OR negation gate. The comparator 108 is active when either the reception permission signal 104 or the transmission permission signal 105 is true, and when it is inactive, its output is in a high impedance state and is not connected to the circuit like a bus receiver or a bus transmitter. Is electrically equivalent to.

In the case of the bus buffer with comparator shown in FIG. 2, 1
Bit buffer 201 in one IC package 2000
It is a set of 8 pieces. 1-bit buffer 20
1 has a bus signal 202, a module signal 203, and a transmission permission signal 204.

Reference numeral 205 is a bus transmitter that sends out signals in the module to the bus. This is controlled to be active / inactive by the transmission permission signal 204, and when inactive, the output is in a high impedance state and is electrically equivalent to not being connected to the circuit.

Reference numeral 206 denotes a comparator, which outputs a logical value of 1 only when the value of the signal on the system bus and the logical value in the module match. This operation is the same as the exclusive OR negation gate. When the transmission enable signal 204 is true, the comparator 206 is active, and when it is inactive, the output is in a high impedance state like the bus transmitter and is electrically equivalent to not being connected to the circuit.

In the present embodiment, the outputs of all the comparators are integrated inside the IC and output from one signal pin. Of course, it is also possible to assign an independent signal pin to the output of each comparator.

FIG. 3 shows an output equivalent circuit of the bus buffer and the comparator used in this embodiment. This circuit is known as an open collector circuit, and has a configuration in which a collector 303 of an output transistor 302 is directly connected to an output terminal 301 as shown in the figure. When an appropriate base current 304 flows through the output transistor 302, the collector 303 and the emitter 305 become conductive, and the signal current 306 can be absorbed from the output terminal. In this embodiment, this state is used as a logical value 0. On the other hand, when the base current 304 is set to 0, the collector 303 and the emitter 305 are also not in a conductive state, which is equivalent to the collector 303 being electrically connected to nowhere. At this time, the output terminal is also equivalent to being electrically connected to nowhere, and this state is used as the logical value 1 in this embodiment.

As is well known, a gate having such an open collector circuit as an output can be directly connected to the output to form a circuit having a logic equivalent to a logical sum gate called a wired OR. In the present embodiment, all the outputs of the respective comparators are directly connected to each other, and a wired logical sum that outputs the logical value 1 only when the outputs of all the comparators have the logical value 1 is formed. We have an output that shows if the values of all the signals that should match match. Needless to say, it is possible to collect the outputs of the respective comparators by using a normal OR gate without using the wire OR, or to mix the wire OR and the normal OR gate.

FIG. 4 shows a block diagram of a data processing system in which memories are multiplexed according to an embodiment of the present invention. 401 is an arithmetic processing unit, 402 is an input / output processing unit,
Reference numerals 403 and 404 are primary and secondary of a memory device used for storing programs and data, and 405 is a system bus for exchanging data and control signals between these devices. The memory device is duplicated by 403 and 404, and it is expected that the same value is always written when writing data and the same value is output when reading data.

FIG. 5 shows a block configuration of the memory devices 403 and 404. Reference numeral 501 is a memory element array, and 502 is an address buffer / decoder. 5
Reference numeral 03 is a bus transceiver with a comparator of the present invention, which exchanges data between the memory element array 501 and the system bus 105. A control unit 504 generates a timing signal necessary for the operation of each block.

FIG. 6 shows the configuration of this embodiment, paying particular attention to the bus and the bus transceiver. In order to avoid making the figure complicated, address lines and control lines not related to the following description are omitted.

The data bus transceivers of the primary and secondary memory devices 403 and 404 are in accordance with the present invention, and the output of the comparator for each data bit is connected to the error detection line 601 to form a wired OR.

When writing data, the arithmetic processing unit 40
1 outputs data on the data bus 602, and the bus transceivers 603 and 604 of the memory devices 403 and 404 receive and capture the data in the device. At this time, the comparator of the bus transceiver determines whether the data on the data bus 602 has been correctly fetched in the memory device. The determination results are collected by the logical OR of the wirings formed by the error detection line 601, and are taken into the arithmetic processing unit 401.

On the other hand, at the time of reading data, the memory devices 403 and 404 output the read data to the data bus 602 via the bus transceivers 603 and 604 in response to a command from the arithmetic processing unit 401. As described above, since the output circuits of the bus transmitters of the bus transceivers 603 and 604 are open collector circuits, a wiring OR is formed for each bit line of the data bus. When both memory devices output the logical value 1, the logical value of the bit line also becomes 1, and the logical value 1 is also fetched into the arithmetic processing unit. When at least one of the memory devices outputs a logical value 0, the logical value of the bit line also becomes 0, and the logical value 0 is also taken into the arithmetic processing unit. That is,
Only when both memory devices output the logical value 1, the logical value 1 and the arithmetic processing unit recognize the bit.

Now, let us consider a case where the memory device 603 has failed and the logical value of a certain bit of an address is fixed to 0. The arithmetic processing unit 4 is assigned to this bit.
When 01 reads 0 and then the memory at the same address is read, the normally operating memory device sub 604 and the faulty memory device main 603 output a logical 0 for this bit to the data bus. At this time, also in the comparators, since the logical value on the data bus and the logical value in the memory device become the same, the output of all the detectors becomes the logical value 1 and no error occurs.

Next, after writing 1 to this defective bit and then reading the memory of the same address, the normal memory device sub-604 outputs a logical 1 on the data bus, and the defective memory device normal. 603 outputs a logical value 0. In this case, since a wiring OR is formed on the bit line of the data bus, this bit is recognized as a logical value 0 by the arithmetic processing unit. Also, at this time, in the comparator of the defective memory device main 603,
Although the values in the data bus and the device match, in a normal memory device normal 604 comparator, the values in the data bus and device do not match, and the comparator outputs a logical value 0 to the error detection line. To do. Therefore, the logical value of the error detection line becomes 0, and the arithmetic processing unit 401 can detect the occurrence of a failure.

In this way, the two memory devices 60
When 3 and 604 output different values on the data bus, the logic value of the error detection line detected by the comparator becomes 0, so that the arithmetic processing unit 401 can detect the occurrence of a failure.
However, if both memory devices output the wrong value to the data bus, resulting in the same value, it will not be detected.
However, it goes without saying that such a failure cannot be dealt with by failure detection by multiplexing.

It should be noted that even if an error is detected, it does not immediately mean that the defective memory device can be identified. For example, also in the present embodiment, the reason why the values in the data bus and the memory device do not match is not only the defect of the memory element but also the defect of the bus transceiver. Therefore, it is needless to say that when an error is detected, it is necessary to execute a diagnostic process for identifying a failure point and a mechanism for electrically disconnecting a module which is considered to be temporarily defective from the bus.

[0029]

According to the present invention, a comparison module is used which confirms that the results output by a plurality of modules are the same and that the results output by the modules are collected and compared with each other to confirm that the results are the same. Instead, it is possible to detect that the signal value on the bus and the signal value inside the module match, so it is possible to realize system multiplexing without introducing a new comparison module. Become.

[Brief description of drawings]

FIG. 1 is a logic circuit diagram of a bus transceiver with a comparator which is an embodiment of the present invention.

FIG. 2 is a logic circuit diagram of a bus buffer with a comparator which is an embodiment of the present invention.

FIG. 3 is a diagram showing an output circuit in an embodiment.

FIG. 4 is a block diagram of a data processing system in which memory devices according to an embodiment of the present invention are multiplexed.

FIG. 5 is a block configuration diagram of a memory device according to an embodiment.

FIG. 6 is a configuration diagram focusing on the bus of the embodiment and a bus transceiver with a comparator.

[Explanation of symbols]

101 ... 1-bit transceiver, 102 ... Bus signal, 1
03 ... Module signal, 104 ... Reception permission signal, 105
... transmission permission signal, 106 ... bus receiver, 107 ... bus transmitter, 108 ... comparator, 201 ... 1-bit buffer, 202 ... bus signal, 203 ... module signal,
204 ... Transmission permission signal, 205 ... Bus transmitter,
205 ... Comparator, 301 ... Output terminal, 302 ... Output transistor, 303 ... Collector, 304 ... Base current, 3
Reference numeral 05 ... Emitter, 306 ... Signal current, 401 ... Arithmetic processing device, 402 ... Input / output processing device, 403 ... Memory device primary, 404 ... Memory device secondary, 405 ... System bus,
501 ... Memory element array, 502 ... Address buffer / decoder, 503 ... Bus transceiver with comparator,
504 ... Control unit, 601 ... Error detection line, 602 ... Data bus, 603 ... Bus transceiver, 604 ... Bus transceiver.

Claims (4)

[Claims] 1. A buffer for signal transmission used in a data processing system, wherein a comparator for the value of one signal with the buffer and the value of the other signal in the buffer is provided in the same chip or package, and these two comparators are provided. A buffer device for signal transmission, which has an output terminal indicating that the values are different. 2. A wired OR circuit can be constructed by connecting the outputs of a plurality of comparators to one signal line, wherein the output of the comparator has two states of open and ground potential. The buffer device of claim 1, wherein the buffer device is a buffer device. 3. An arithmetic processing unit, an input / output processing unit, a plurality of independent memory devices used for storing programs and data, and a system bus for each of these devices to exchange data and control signals. Is
System having a comparator for one signal value and another signal value in the same chip or package, and a buffer device for signal transmission having an output terminal indicating that the two values are different Connected to the bus,
The comparator compares the value of a signal on the bus with the value of a corresponding signal in the memory device, and sends a positive or incorrect signal of signal transmission between the memory device and the bus to the bus. Processing system. 4. A plurality of memory devices are capable of simultaneously outputting signals on a system bus, and the comparator of the buffer is used to compare the value of the signal on the bus with the value of the corresponding signal in the memory device. 4. The data processing system according to claim 3, wherein the coincidence or non-coincidence of the output of the other memory device outputting a signal on the system bus at the same time as the output of the memory device can be known.