JPH0553374U - Electronic shutter speed control circuit for video camera - Google Patents

Abstract

(57) [Summary] [Object] To provide an electronic shutter speed control circuit for a video camera, which can obtain a clearer image quality by adaptively varying the shutter speed according to the illuminance. [Arrangement] Illuminance detecting means for detecting high illuminance and low illuminance, first generating means for generating a comparison value proportional to the high illuminance and low illuminance detection periods, and up and down the horizontal clock pulse signal. And a second generating means for generating a reference value for each vertical period, and a comparison for controlling the light accumulation time of the solid-state image sensor by cutting off the supply of the horizontal clock pulse signal to the solid-state image sensor. A control means is provided. [Effect] With this, by controlling the electronic shutter speed adaptively according to the change of the illuminance of the subject, a clear image quality without the blooming phenomenon can be obtained.

Description

[Detailed description of the device]

[0001]

[Industrial application]

 The present invention relates to a video camera, and in particular, when detecting an aperture drive voltage of the video camera and shooting an object with a certain illuminance or more, a clearer image quality can be obtained by adaptively changing the shutter speed according to the illuminance. The invention relates to an electronic shutter speed control circuit for a video camera.

[0002]

[Prior Art]

 An ordinary video camera uses a CCD (charge coupled device) as an image sensor to store light for a certain period and then reads it out. In the case of NTSC, the light storage time is one vertical cycle (1 V: 1/60 second). ), And in the case of PAL, the light accumulation time is 1/50 second. Therefore, since the diaphragm is always open and the shutter speed is fixed, the amount of light incident on the image sensor changes depending on the driving of the diaphragm.

That is, in the case of a bright subject, the aperture of the diaphragm is narrowed, and in the case of a dark subject, the aperture of the diaphragm is widened so that the amount of incident light is adjusted to be constant. However, if the light storage time of the image sensor is reduced, a clearer image can be obtained as well as increasing the shutter speed of a general still camera, and this will be used as a high-speed electronic shutter.

[0004]

[Problems to be solved by the device]

 Therefore, an object of the present invention is to provide an electronic shutter speed control circuit for a camera, which is capable of capturing a clearer image by incorporating a high-speed electronic shutter function in a video camera using a CCD.

[0005]

[Means for Solving the Problems]

 In order to achieve the above-mentioned object, the electronic shutter speed control circuit of the video camera of the present invention, in a video camera using a solid-state image sensor, inputs the diaphragm drive voltage and sets the diaphragm drive voltage to the lower and upper reference illuminances. The illuminance detection means for detecting high illuminance and low illuminance by comparison, and up / down counting of the horizontal clock pulse signal according to the output of the illuminance detection means are compared with the high illuminance and low illuminance detection periods. First generating means for generating a comparison value, second generating means for raising and lowering the horizontal clock pulse signal to generate a reference value for each vertical period, and the first and second generating means described above. When the reference value is larger than the compared value, the horizontal clock pulse signal of the solid-state image sensor is blocked from being supplied to the solid-state image sensor. Controlling the shutter speed by positively varying the light storage time of the solid-state image sensor according to the illuminance of the subject at every vertical time by providing comparison control means for controlling the light storage time of the body image sensor Is characterized by.

[0006]

[Action]

 The present invention detects the illuminance in the image pickup state with the diaphragm drive voltage and sets the appropriate electronic shutter speed in advance, so that when capturing an image of a subject with a certain illuminance or higher, the electronic shut speed can be varied to obtain clearer image quality. can get.

[0007]

【Example】

 Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of the present invention. In a video camera including a diaphragm driving voltage generating circuit 1 for detecting a driving voltage and driving a diaphragm, a CCD is used, and the diaphragm of the diaphragm driving voltage generating circuit 1 is used. An illuminance detection circuit 2 that senses the illuminance being imaged using a drive voltage, and a count value is held by counting up / down the horizontal clock pulse signal CLK by the output of the illuminance detection circuit 2 which is reset by a reset signal RS. An up counter that up-counts the horizontal clock pulse signal CLK and is reset according to the vertical drive pulse signal VD for each vertical cycle by up-down counter 3 that performs a holding operation according to the signal HOLD and up-down counter 3. Second generating means composed of 4 and the up / down counter -3 and the output of the up counter 4 are compared to output a pulse for adjusting the light accumulation period, and an AND gate 6 for logically ANDing the output of the comparison control means 5 and the horizontal drive pulse signal HD. And an amplifier 7 for amplifying the output of the AND gate 6. The output of the amplifier 7 is biased by the CCD substrate voltage V _SUB and supplied to the CCD.

FIG. 2 is a circuit diagram of an embodiment of the present invention, in which the illuminance detection circuit 2 compares the diaphragm drive voltage with the reference voltage set by the resistors R _{1 to} R ₃ , that is, the comparators 21 and 22. An output lower limit and an upper limit detector, a NOR gate 24 that logically combines the outputs of the comparators 21 and 22 to generate a hold signal to be input to a microcomputer (not shown), and outputs of the comparators 21 and 22. It is comprised from the comparator 23 which compares. Then, the output of the octal up / down counter 3 and the output of the up counter 4 are configured to be converted into analog signals through digital-analog converters 51 and 52, respectively, and then compared with a comparator 54.

An analog switch SW is provided so that the output of the up / down counter 3 and the output of a third generation means (EVR: Electric Variable Register) 53 to which microcomputer data is applied are selected according to a mode selection signal of the microcomputer. Is configured.

FIG. 3 shows another embodiment of the present invention, in which the output of the illuminance detection circuit 2 is applied to the up / down counter 3, and the output of the up / down counter 3 and the up / down counter 4 are compared. The output is configured to be subtracted by the subtractor 9 and then applied to the AND gate 6.

The difference between the light accumulation in the NTSC electronic shutter mode and the normal mode and the readout for reading the light in the present invention having such a configuration will be briefly described with reference to FIGS. 4, 5 and 6.

In the normal mode, light is stored for one field (one vertical period) and then read out. In the electronic shutter mode, however, if the stored charge is reset immediately after the light is stored, By re-accumulating the light from that time, only the re-accumulated light (the shaded portion) is output at the time of read-out, which is the same as controlling the shutter speed to high speed.

Focusing on this, if 1/60 seconds is divided into about 256 pieces using 8 bits and the reset period is determined, a maximum electronic shutter operation of 1/15360 seconds can be obtained, and the shutter operation is actually performed in the camera. Since 1/10000 seconds is sufficient, there is no practical problem.

That is, as in the schematic diagram shown in FIG. 4, the solid line indicates the state when the illuminance is high, and the points indicate the state when the illuminance is low.

The operation of the present invention will be described with reference to FIG. 1. The diaphragm drive voltage generating circuit 1 detects the luminance signal input level to generate the diaphragm drive voltage, and detects the generated diaphragm drive voltage for illuminance detection. The up / down control signal detected by the circuit 2 and output by the illuminance detection circuit 2 is applied to the 8-bit up / down counter 3, the counter holding control signal is applied to the microcomputer, and in the case of the appropriate electronic shutter mode by the microcomputer. Make a judgment.

At this time, the up / down counter 3 counts up / down the horizontal clock pulse signal CLK according to the output of the illuminance detection circuit 2 and applies it to the comparison control means 5, but the microcomputer outputs the reset signal RS. The up / down counter 3 is reset by applying it to the up / down counter 3, and a hold signal H OLD for holding the up / down counter 3 by a microcomputer is applied to the counter when the electronic shutter mode is appropriate.

Then, the up counter 4, which is reset in response to the vertical drive pulse signal HD every vertical period, counts up the horizontal clock pulse signal CLK and applies it to the comparison control means 5.

The comparison control means 5 compares the outputs of the up / down counter 3 and the up counter 4 to change the pulse width of the pulse signal corresponding to the period for accumulating the optical signal when performing the electronic shutter mode and output the pulse signal.

The output waveform of the comparison control means 5 and the horizontal drive pulse signal HD are ANDed by the AND gate 6 and amplified sufficiently by the amplifier 7 so that the CCD can be reset, and then placed on the substrate voltage V _SUB of the CCD. And applied to the CCD.

The present invention will be described in detail with reference to the drawing of the embodiment of FIG. 3 and then the embodiment of FIG.

FIG. 3 is a circuit diagram of an embodiment of the present invention, in which the diaphragm drive voltage detected by the diaphragm drive voltage generating circuit 1 is supplied to the non-inverting terminal (+) of the comparator 21 of the illuminance detecting circuit 2. , The inverting terminal (−) of the comparator 22 and the reference set by the resistors R ₁ , R ₂ , and R ₃ to the inverting terminal (−) of the comparator 21 and the non-inverting terminal (+) of the comparator 22. The voltages V ₁ and V ₂ are applied.

At this time, the reference voltage V ₁ is

[0024]

[Equation 1]

And the reference voltage V ₂ is

[0026]

[Equation 2]

It becomes

Therefore, when the diaphragm drive voltage is higher than the reference voltage V ₁ (that is, when the illuminance is low), the comparator 21 outputs a high potential signal, and when the diaphragm drive voltage is lower than the reference voltage V ₂ (that is, the illuminance is high). When the comparator 22 outputs a high potential signal, the output of the comparator 21 is applied to the inverting terminal (−) of the comparator 23, and the output of the comparator 22 is applied to the non-inverting terminal (+) of the comparator 23. Therefore, the output of the comparator 23 outputs a high potential signal when the illuminance is high and a low potential signal when the illuminance is low.

At this time, a truth table for the operating states of the up / down counter 3 by the outputs of the comparators 21, 22, 23 and the NOR gate 24 is as follows.

[0030]

[Table 1]

That is, when the diaphragm driving voltage is higher than the reference voltage V ₂ or lower than the reference voltage V ₁ , the output of the NOR gate 24 becomes high level and the up / down counter 3 holds the value after stopping counting. When the diaphragm drive voltage is lower than the reference voltage V ₂ (high illuminance), the output of the comparator 23 becomes low level and the up / down counter 3 counts down.

At this time, the horizontal clock pulse signal CLK is applied to the up / down counter 3 as shown in C of FIG. 5, and such a clock signal CLK is also applied to the up counter 4, and the up counter 4 of FIG. After being reset for each field by a vertical drive pulse signal VD such as B, only up-down counting is performed.

The up / down counter counts the horizontal clock pulse signal CLK, and since one horizontal cycle is 63.5 μs, it can be changed by 63.5 μs in 1-bit increments and becomes 8 bits. ⁸ = 256 bits can be arbitrarily changed.

On the other hand, the output of the 8-bit up / down counter 3 was applied to one terminal (+) of the subtractor 9, and the output of the up counter 4 was applied to the other terminal (−) of the subtractor 9. Up / down counter if configured so that after (+) terminal input-(-) terminal input and the resulting value is (+), a high potential signal is output and when it is (-), a low potential signal is output. Compared with the value of the up counter 4, the subtracter 9 outputs a high potential signal until it becomes equal to the value of 3, and thereafter outputs a low potential signal. Outputs a pulse like D in FIG.

The output of the subtractor 9 is applied to the AND gate 6 and is ANDed with the horizontal drive pulse signal HD as shown in A of FIG. 5, so that the output of the AND gate 6 is shown as E of FIG. The output pulse of the AND gate 6 is amplified enough by the amplifier 7 so that the CCD can be reset, and then applied to the CCD substrate voltage V _SUB through the coupling capacitor 8.

That is, since there is no signal accumulation during the period in which the waveform pulse of FIG. 5E exists and signals are accumulated only in the pulse-free period, the shutter speed, which is the object of the present invention, can be controlled at high speed.

When viewed as a whole, the present invention continues to operate in negative field back and operates in priority to aperture driving, so the shutter speed is preferentially controlled.

The circuit of one embodiment of the present invention which does not receive the microcomputer control has been outlined above, and one embodiment of the present invention which receives the microcomputer control will be described below with reference to FIG.

2 has the same operation as that of FIG. 3, except that the electronic shutter speed control circuit can be controlled by the microcomputer and the simple comparator 54 without using the subtractor 9. Is a feature.

That is, the diaphragm drive voltage of the diaphragm drive voltage generation circuit 1 is detected by the illuminance detection circuit 2 as shown in FIG. 3, but the output of the NOR gate 24 is applied to the microcomputer.

Then, the outputs of the up / down counter 3 and the up counter 4 are converted into analog signals through the digital-analog converters 51 and 52 and then added to the comparator 54 for comparison.

Therefore, when the output of the up counter 4 becomes larger than the output of the up counter 4, the comparator 54 outputs the low potential signal (see the waveform of D in FIG. 5).

At this time, the up counter 4 is reset every vertical cycle as in FIG.

The output of the up / down counter 3 converted into an analog signal through the digital-analog converter 51 is applied to one end of the analog switch SW, and the output of the EVR 53 receiving the microcomputer data is also applied to one end of the analog switch SW. And selected according to the mode selection signal.

That is, since the analog switch SW is switched according to the mode selection signal of the microcomputer, the output of the up / down counter 3 or the output of the EVR 53 is selectively supplied to the non-inverting terminal (+) of the comparator 54. Is applied. At this time, the EVR53 receives data from the microcomputer and outputs an analog signal corresponding to the data. Therefore, if the microcomputer applies the programmed value to the EVR53 and selects the EVR53 with the analog switch SW, the electronic shutter speed control circuit. Operates at the programmed electronic shutter speed regardless of the operation of the illuminance detection circuit 2.

[0046]

[Effect of the device]

 As described above, according to the present invention, the electronic shutter speed can be varied when an object having a certain illuminance or higher is imaged by detecting the illuminance in the image pickup state with the diaphragm drive voltage and setting the appropriate electronic shutter speed first. A clearer image quality can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of an electronic shutter speed control circuit according to the present invention.

FIG. 2 is a circuit diagram of a preferred embodiment of an electronic shutter speed control circuit according to the present invention.

FIG. 3 is a circuit diagram of another preferred embodiment of the electronic shutter speed control circuit according to the present invention.

FIG. 4 is a graph showing the relationship between aperture opening and electronic shutter speed according to the present invention.

5A to 5E are waveform diagrams of respective portions of FIGS. 2 and 3.

FIG. 6 is a diagram for explaining the light accumulation operation of the solid-state image sensor in the normal mode and the high-speed shutter mode according to the present invention.

[Explanation of symbols]

 1 Aperture Drive Voltage Generation Circuit 2 Illuminance Detection Circuit 3 Up / Down Counter 4 Up Counter 5 Comparison Control Means 6 AND Gate 7 Amplifiers 21, 22, 23, 24, 54 Comparator 51, 52 Digital-Analog Converter

Claims (3)

[Scope of utility model registration request] In a video camera using a solid-state image sensor, an illuminance detecting means for detecting a high illuminance and a low illuminance by inputting an iris driving voltage and comparing the iris driving voltage with a set lower and upper reference illuminance. First generation means for up / down counting a horizontal clock pulse signal according to an output of the illuminance detection means to generate a comparison value proportional to a high illuminance and a low illuminance detection period, and the horizontal clock pulse signal A second generating means for generating a reference value for each vertical period by moving up and down, and comparing the outputs of the first and second generating means with each other, the solid state when the reference value is larger than the compared value. Comparing control means for controlling the light accumulation time of the solid-state image sensor by cutting off the supply of the horizontal clock pulse signal of the image sensor to the solid-state image sensor is provided for each vertical period. Electronic shutter speed control circuit of a video camera and controlling the shutter speed by varying positively according the light accumulating time of the fixed image sensor the illuminance of the subject. 2. The lower limit detector for detecting the low illuminance state by comparing the inputted iris driving voltage with the lower illuminance lower limit reference voltage, and the illuminance detecting means compares the inputted lower iris drive voltage with the upper illuminance upper limit reference voltage. 2. An upper limit detector for detecting a high illuminance state, and a gate for logically adding outputs of the lower limit and upper limit detectors to generate a holding control signal. Electronic camera shutter speed control circuit. 3. In a videoeostil camera using a solid-state imaging device, an illuminance detection for detecting high illuminance and low illuminance by inputting an iris driving voltage and comparing the iris driving voltage with a set lower and upper illuminance reference voltages. And a first generation for up / down counting the horizontal clock pulse signal of the solid-state image sensor according to the output of the illuminance detection means to generate a first comparison value proportional to the high illuminance and low illuminance detection periods. Means, third generating means for generating a second comparison value proportional to the selected shutter speed setting value, and for selectively outputting the outputs of the first and third generating means according to the mode setting. Selection means, second generation means for up-counting the horizontal clock pulse signal to generate a reference value for each vertical period, and output of the selection means and the second generation means. Force comparison and comparison for controlling the light accumulation time of the solid-state image sensor by blocking supply of the horizontal clock pulse signal of the solid-state image sensor to the solid-state image sensor when the reference value is larger than the comparison value An electronic shutter speed control circuit for a video camera, comprising a control means to control the shutter speed by adaptively varying the light accumulation time of the solid-state image sensor in each vertical period in response to the illuminance of the object.